diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f446xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f446xx.h
index 5215adb02a..80f7b7be2f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f446xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f446xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f446xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F446xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -936,19 +936,19 @@ typedef struct
 /** @addtogroup Peripheral_memory_map
   * @{
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE            ((uint32_t)0xA0001000U) /*!< QuadSPI registers base address                                            */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define QSPI_R_BASE            0xA0001000U /*!< QuadSPI registers base address                                            */
 
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address                                                          */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address                                                          */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -1056,24 +1056,24 @@ typedef struct
 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
 
 /*!< Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000U)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1196,334 +1196,334 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)        /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)        /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1531,30 +1531,30 @@ typedef struct
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1563,1320 +1563,1320 @@ typedef struct
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001U)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002U)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004U)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008U)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010U)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020U)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040U)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080U)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000U)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000U)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800U)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00U)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001U)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002U)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004U)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008U)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010U)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020U)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040U)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080U)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100U)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200U)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400U)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800U)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000U)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000U)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000U)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000U)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000U)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000U)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000U)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000U)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000U)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000U)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000U)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000U)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000U)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000U)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000U)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000U)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001U)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002U)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004U)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008U)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010U)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020U)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040U)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080U)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100U)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200U)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400U)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800U)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000U)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000U)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000U)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000U)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000U)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000U)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000U)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000U)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000U)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000U)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000U)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000U)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000U)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000U)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000U)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000U)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001U)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002U)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004U)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008U)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010U)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020U)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040U)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080U)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100U)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200U)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400U)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800U)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000U)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000U)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000U)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000U)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000U)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000U)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000U)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000U)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000U)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000U)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000U)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000U)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000U)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000U)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000U)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000U)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001U)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002U)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004U)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008U)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010U)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020U)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040U)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080U)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100U)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200U)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400U)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800U)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000U)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000U)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000U)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000U)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000U)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000U)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000U)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000U)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000U)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000U)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000U)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000U)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000U)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000U)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000U)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000U)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2885,56 +2885,56 @@ typedef struct
 /******************************************************************************/
 
 /*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        ((uint32_t)0x00000001U)       /*!< CEC Enable                              */
-#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002U)       /*!< CEC Tx Start Of Message                 */
-#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004U)       /*!< CEC Tx End Of Message                   */
+#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                              */
+#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message                 */
+#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message                   */
 
 /*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007U)       /*!< CEC Signal Free Time                    */
-#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008U)       /*!< CEC Tolerance                           */
-#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010U)       /*!< CEC Rx Stop                             */
-#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020U)       /*!< CEC Bit Rising Error generation         */
-#define  CEC_CFGR_LBPEGEN                    ((uint32_t)0x00000040U)       /*!< CEC Long Bit Period Error generation    */
-#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100U)       /*!< CEC Signal Free Time optional           */
-#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080U)       /*!< CEC Broadcast No error generation       */
-#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000U)       /*!< CEC Own Address                         */
-#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000U)       /*!< CEC Listen mode                         */
+#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time                    */
+#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                           */
+#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                             */
+#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation         */
+#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Bit Period Error generation    */
+#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional           */
+#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast No error generation       */
+#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                         */
+#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                         */
 
 /*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FFU)       /*!< CEC Tx Data                              */
+#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                              */
 
 /*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FFU)       /*!< CEC Rx Data                              */
+#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                              */
 
 /*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001U)       /*!< CEC Rx-Byte Received                      */
-#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002U)       /*!< CEC End Of Reception                      */
-#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004U)       /*!< CEC Rx-Overrun                            */
-#define  CEC_ISR_BRE                         ((uint32_t)0x00000008U)       /*!< CEC Rx Bit Rising Error                   */
-#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010U)       /*!< CEC Rx Short Bit period Error             */
-#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020U)       /*!< CEC Rx Long Bit period Error              */
-#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040U)       /*!< CEC Rx Missing Acknowledge                */
-#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080U)       /*!< CEC Arbitration Lost                      */
-#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100U)       /*!< CEC Tx Byte Request                       */
-#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200U)       /*!< CEC End of Transmission                   */
-#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400U)       /*!< CEC Tx-Buffer Underrun                    */
-#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800U)       /*!< CEC Tx-Error                              */
-#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000U)       /*!< CEC Tx Missing Acknowledge                */
+#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                      */
+#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                      */
+#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                            */
+#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                   */
+#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error             */
+#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error              */
+#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge                */
+#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                      */
+#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                       */
+#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                   */
+#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                    */
+#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                              */
+#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge                */
 
 /*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001U)       /*!< CEC Rx-Byte Received IT Enable            */
-#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002U)       /*!< CEC End Of Reception IT Enable            */
-#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004U)       /*!< CEC Rx-Overrun IT Enable                  */
-#define  CEC_IER_BREIE                       ((uint32_t)0x00000008U)       /*!< CEC Rx Bit Rising Error IT Enable         */
-#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010U)       /*!< CEC Rx Short Bit period Error IT Enable   */
-#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020U)       /*!< CEC Rx Long Bit period Error IT Enable    */
-#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040U)       /*!< CEC Rx Missing Acknowledge IT Enable      */
-#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080U)       /*!< CEC Arbitration Lost IT Enable            */
-#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100U)       /*!< CEC Tx Byte Request  IT Enable            */
-#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200U)       /*!< CEC End of Transmission IT Enable         */
-#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400U)       /*!< CEC Tx-Buffer Underrun IT Enable          */
-#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800U)       /*!< CEC Tx-Error IT Enable                    */
-#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000U)       /*!< CEC Tx Missing Acknowledge IT Enable      */
+#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable            */
+#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable            */
+#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable                  */
+#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable         */
+#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable   */
+#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable    */
+#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable            */
+#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable            */
+#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable         */
+#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                    */
+#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable      */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2942,15 +2942,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2958,92 +2958,92 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002U)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000U)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable*/
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01U)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02U)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFFU)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFFU)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FFU)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00U)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3057,51 +3057,60 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001U)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002U)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004U)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008U)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010U)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020U)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040U)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080U)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800U)
-#define DCMI_CR_OUTEN                        ((uint32_t)0x00002000U)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000U)
-#define DCMI_CR_BSM_0                        ((uint32_t)0x00010000U)
-#define DCMI_CR_BSM_1                        ((uint32_t)0x00020000U)
-#define DCMI_CR_OEBS                         ((uint32_t)0x00040000U)
-#define DCMI_CR_LSM                          ((uint32_t)0x00080000U)
-#define DCMI_CR_OELS                         ((uint32_t)0x00100000U)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_OUTEN                        0x00002000U
+#define DCMI_CR_ENABLE                       0x00004000U
+#define DCMI_CR_BSM_0                        0x00010000U
+#define DCMI_CR_BSM_1                        0x00020000U
+#define DCMI_CR_OEBS                         0x00040000U
+#define DCMI_CR_LSM                          0x00080000U
+#define DCMI_CR_OELS                         0x00100000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001U)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002U)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004U)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001U)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002U)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004U)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008U)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010U)
+/********************  Bits definition for DCMI_RIS register  ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001U)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002U)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004U)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008U)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010U)
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 
 /********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   ((uint32_t)0x00000001U)
-#define DCMI_MIS_OVR_MIS                     ((uint32_t)0x00000002U)
-#define DCMI_MIS_ERR_MIS                     ((uint32_t)0x00000004U)
-#define DCMI_MIS_VSYNC_MIS                   ((uint32_t)0x00000008U)
-#define DCMI_MIS_LINE_MIS                    ((uint32_t)0x00000010U)
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
@@ -3111,40 +3120,40 @@ typedef struct
 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001U)
-#define DCMI_ICR_OVR_ISC                     ((uint32_t)0x00000002U)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004U)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008U)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010U)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
 
 /********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        ((uint32_t)0x000000FFU)
-#define DCMI_ESCR_LSC                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESCR_LEC                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESCR_FEC                        ((uint32_t)0xFF000000U)
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
 
 /********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        ((uint32_t)0x000000FFU)
-#define DCMI_ESUR_LSU                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESUR_LEU                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESUR_FEU                        ((uint32_t)0xFF000000U)
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
 
 /********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  ((uint32_t)0x00003FFFU)
-#define DCMI_CWSTRT_VST                      ((uint32_t)0x1FFF0000U)
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
 
 /********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   ((uint32_t)0x00003FFFU)
-#define DCMI_CWSIZE_VLINE                    ((uint32_t)0x3FFF0000U)
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
 
 /********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        ((uint32_t)0x000000FFU)
-#define DCMI_DR_BYTE1                        ((uint32_t)0x0000FF00U)
-#define DCMI_DR_BYTE2                        ((uint32_t)0x00FF0000U)
-#define DCMI_DR_BYTE3                        ((uint32_t)0xFF000000U)
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3152,161 +3161,161 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3315,154 +3324,154 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3470,108 +3479,108 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008U)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009U)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000AU)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000BU)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000CU)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000DU)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000EU)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000FU)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
 #define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010U)
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000U) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000U) 
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3579,709 +3588,709 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000U)        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     ((uint32_t)0x00200000U)        /*!<Write FIFO Disable         */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
 
 /******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  ((uint32_t)0x000000FFU)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMWAIT2                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHOLD2                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHIZ2                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  ((uint32_t)0x000000FFU)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTWAIT2                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHOLD2                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHIZ2                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000U)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000U)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007U)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
                                             
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008U)        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
 
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010U)        /*!<Command target 1 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
 
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0U)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100U)        /*!<Bit 3 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
 
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00U)        /*!<MRD[12:0] bits (Mode register definition) */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
 
 /******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001U)        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
 
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFEU)        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
 
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000U)        /*!<RES interupt enable */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
 
 /******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001U)        /*!<Refresh error flag */
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
 
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006U)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004U)        /*!<Bit 1 */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
 
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018U)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020U)        /*!<Busy status */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4289,235 +4298,235 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -4537,22 +4546,22 @@ typedef struct
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -4572,57 +4581,57 @@ typedef struct
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -4630,97 +4639,97 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4728,103 +4737,101 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        ((uint32_t)0x00000001U)        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      ((uint32_t)0x00000002U)        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      ((uint32_t)0x00000004U)        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    ((uint32_t)0x00000008U)        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    ((uint32_t)0x00000010U)        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    ((uint32_t)0x00000020U)        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      ((uint32_t)0x00000040U)        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     ((uint32_t)0x00000080U)        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       ((uint32_t)0x00000F00U)        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    ((uint32_t)0x00001000U)        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_SWRST                     ((uint32_t)0x00002000U)        /*!< Software reset                      */
-#define  FMPI2C_CR1_TXDMAEN                   ((uint32_t)0x00004000U)        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   ((uint32_t)0x00008000U)        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       ((uint32_t)0x00010000U)        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 ((uint32_t)0x00020000U)        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_WUPEN                     ((uint32_t)0x00040000U)        /*!< Wakeup from STOP enable             */
-#define  FMPI2C_CR1_GCEN                      ((uint32_t)0x00080000U)        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    ((uint32_t)0x00100000U)        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    ((uint32_t)0x00200000U)        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   ((uint32_t)0x00400000U)        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     ((uint32_t)0x00800000U)        /*!< PEC enable                          */
+#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
+#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
+#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
+#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
+#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
+#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
+#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
+#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
+#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
+#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
+#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
+#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
+#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
+#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
+#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
+#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
+#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
+#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
+#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
 
 /******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      ((uint32_t)0x000003FFU)        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    ((uint32_t)0x00000400U)        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     ((uint32_t)0x00000800U)        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   ((uint32_t)0x00001000U)        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     ((uint32_t)0x00002000U)        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      ((uint32_t)0x00004000U)        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      ((uint32_t)0x00008000U)        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    ((uint32_t)0x00FF0000U)        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    ((uint32_t)0x01000000U)        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   ((uint32_t)0x02000000U)        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   ((uint32_t)0x04000000U)        /*!< Packet error checking byte                              */
+#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
+#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
+#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
+#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
+#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
+#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
+#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
+#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
+#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
+#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
+#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
 
 /*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      ((uint32_t)0x000003FFU)        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  ((uint32_t)0x00000400U)        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    ((uint32_t)0x00008000U)        /*!< Own address 1 enable      */
+#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
+#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
+#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
 
 /*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      ((uint32_t)0x000000FEU)        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   ((uint32_t)0x00000700U)        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    ((uint32_t)0x00008000U)        /*!< Own address 2 enable    */
+#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
+#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
+#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
 
 /*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  ((uint32_t)0x000000FFU)        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  ((uint32_t)0x0000FF00U)        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                ((uint32_t)0x000F0000U)        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                ((uint32_t)0x00F00000U)        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 ((uint32_t)0xF0000000U)        /*!< Timings prescaler             */
+#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
+#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
+#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
+#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
+#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
 
 /******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             ((uint32_t)0x00000FFFU)        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                ((uint32_t)0x00001000U)        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             ((uint32_t)0x00008000U)        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             ((uint32_t)0x0FFF0000U)        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               ((uint32_t)0x80000000U)        /*!< Extended clock timeout enable */
+#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
+#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
+#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
+#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
+#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
 
 /******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       ((uint32_t)0x00000001U)        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      ((uint32_t)0x00000002U)        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      ((uint32_t)0x00000004U)        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      ((uint32_t)0x00000008U)        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     ((uint32_t)0x00000010U)        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     ((uint32_t)0x00000020U)        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        ((uint32_t)0x00000040U)        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       ((uint32_t)0x00000080U)        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      ((uint32_t)0x00000100U)        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      ((uint32_t)0x00000200U)        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       ((uint32_t)0x00000400U)        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    ((uint32_t)0x00000800U)        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   ((uint32_t)0x00001000U)        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     ((uint32_t)0x00002000U)        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      ((uint32_t)0x00008000U)        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       ((uint32_t)0x00010000U)        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   ((uint32_t)0x00FE0000U)        /*!< Address match code (slave mode)  */
+#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
+#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
+#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
+#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
+#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
+#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
+#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
+#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
+#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
+#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
+#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
+#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
+#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
+#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
+#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
+#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
+#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
 
 /******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    ((uint32_t)0x00000008U)        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    ((uint32_t)0x00000010U)        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    ((uint32_t)0x00000020U)        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    ((uint32_t)0x00000100U)        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    ((uint32_t)0x00000200U)        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     ((uint32_t)0x00000400U)        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     ((uint32_t)0x00000800U)        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  ((uint32_t)0x00001000U)        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   ((uint32_t)0x00002000U)        /*!< Alert clear flag            */
+#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
+#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
+#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
+#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
+#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
+#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
+#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
+#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
+#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
 
 /******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      ((uint32_t)0x000000FFU)        /*!< PEC register */
+#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
 
 /******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   ((uint32_t)0x000000FFU)        /*!< 8-bit receive data */
+#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
 
 /******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   ((uint32_t)0x000000FFU)        /*!< 8-bit transmit data */
+#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4832,20 +4839,20 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -4854,41 +4861,41 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000U)     /*!< Over Drive enable                     */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000U)     /*!< Over Drive switch enabled             */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000U)     /*!< Under Drive enable in stop mode       */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000U)     /*!< Bit 0                                 */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000U)     /*!< Bit 1                                 */
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run         */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                     */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled             */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode       */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                                 */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                                 */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run         */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
@@ -4896,17 +4903,17 @@ typedef struct
 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000080U)     /*!< Enable WKUP pin 2                                */
-#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100U)     /*!< Enable WKUP pin 1                                */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000U)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000U)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000U)     /*!< Under Drive ready                                */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP2                       0x00000080U     /*!< Enable WKUP pin 2                                */
+#define  PWR_CSR_EWUP1                       0x00000100U     /*!< Enable WKUP pin 1                                */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -4917,133 +4924,133 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001U)            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002U)            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004U)            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008U)            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000010U)            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          ((uint32_t)0x00000040U)            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         ((uint32_t)0x00000080U)            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00001F00U)            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     ((uint32_t)0x00000800U)            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     ((uint32_t)0x00001000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000U)            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000U)            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000U)            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000U)            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000U)            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000U)            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000U)            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  ((uint32_t)0x04000000U)            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  ((uint32_t)0x08000000U)            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  ((uint32_t)0x10000000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  ((uint32_t)0x20000000U)            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  ((uint32_t)0x40000000U)            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  ((uint32_t)0x80000000U)            /*!< Bit 7 */
+#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
+#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
+#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
+#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
+#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
+#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
+#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
+#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
+#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
+#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
+#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
 
 /*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001U)            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700U)            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000U)            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     ((uint32_t)0x00040000U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     ((uint32_t)0x00080000U)            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     ((uint32_t)0x00100000U)            /*!< Bit 4 */
+#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
 
 /******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001U)             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002U)             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008U)             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010U)             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020U)             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00003F00U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     ((uint32_t)0x00000100U)             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     ((uint32_t)0x00000200U)             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     ((uint32_t)0x00000400U)             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     ((uint32_t)0x00000800U)             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     ((uint32_t)0x00001000U)             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     ((uint32_t)0x00002000U)             /*!< Bit 5 */
+#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
+#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
 
 /******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001U)             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002U)             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008U)             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010U)             /*!< Clear Timeout Flag           */
+#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
 
 /******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFFU)               /*!< DL[31:0]: Data Length */
+#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
 
 /******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FFU)            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                ((uint32_t)0x00000001U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                ((uint32_t)0x00000002U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                ((uint32_t)0x00000004U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                ((uint32_t)0x00000008U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                ((uint32_t)0x00000010U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                ((uint32_t)0x00000020U)            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                ((uint32_t)0x00000040U)            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                ((uint32_t)0x00000080U)            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300U)            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00U)            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000U)            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000U)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000U)            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000U)            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       ((uint32_t)0x00040000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       ((uint32_t)0x00080000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       ((uint32_t)0x00100000U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       ((uint32_t)0x00200000U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       ((uint32_t)0x00400000U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000U)            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000U)            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000U)            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         ((uint32_t)0x40000000U)            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000U)            /*!< DDRM: Double Data Rate Mode           */ 
+#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
+#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
+#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
+#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
 /******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFFU)            /*!< ADDRESS[31:0]: Address                */
+#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
 
 /******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFFU)            /*!< ALTERNATE[31:0]: Alternate Bytes      */
+#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
 
 /******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFFU)            /*!< DATA[31:0]: Data                      */
+#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
 
 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFFU)            /*!< MASK[31:0]: Status Mask               */
+#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
 
 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFFU)            /*!< MATCH[31:0]: Status Match             */
+#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
 
 /******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFFU)            /*!< INTERVAL[15:0]: Polling Interval      */
+#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
 
 /******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFFU)            /*!< TIMEOUT[15:0]: Timeout period         */
+#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5051,543 +5058,543 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000U)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
-#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x70000000U)
-#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x10000000U)
-#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x20000000U)
-#define  RCC_PLLCFGR_PLLR_2                  ((uint32_t)0x40000000U)
+#define  RCC_PLLCFGR_PLLR                    0x70000000U
+#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
+#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
+#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
 
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    ((uint32_t)0x00000003U)        /*!< PLL/PLLR selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
+#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   ((uint32_t)0x0000000CU)        /*!< PLL/PLLR used as system clock       */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
+#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040U)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000U)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000U)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB3RSTR_QSPIRST               ((uint32_t)0x00000002U)
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
+#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040U)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080U)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_SPDIFRXRST             ((uint32_t)0x00010000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_FMPI2C1RST             ((uint32_t)0x01000000U)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000U)
-#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x08000000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_CECRST                 0x08000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000U)
-#define  RCC_APB2RSTR_SAI2RST                ((uint32_t)0x00800000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_SAI2RST                0x00800000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
 
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000U)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000U)
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB3ENR_QSPIEN                 ((uint32_t)0x00000002U)
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040U)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080U)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_SPDIFRXEN               ((uint32_t)0x00010000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_FMPI2C1EN               ((uint32_t)0x01000000U)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000U)
-#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x08000000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_CECEN                   0x08000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200U)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB2ENR_SAI2EN                  ((uint32_t)0x00800000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_SAI2EN                  0x00800000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
 
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000U)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000U)
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB3LPENR_QSPILPEN             ((uint32_t)0x00000002U)
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
+#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010U)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020U)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040U)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080U)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_SPDIFRXLPEN           ((uint32_t)0x00010000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000U)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000U)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_FMPI2C1LPEN           ((uint32_t)0x01000000U)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000U)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB1LPENR_CECLPEN               ((uint32_t)0x08000000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_CECLPEN               0x08000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200U)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB2LPENR_SAI2LPEN              ((uint32_t)0x00800000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SP              ((uint32_t)0x00030000U)
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            ((uint32_t)0x00010000U)
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            ((uint32_t)0x00020000U)
+#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 
 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLSAICFGR_PLLSAIM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLSAICFGR_PLLSAIM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLSAICFGR_PLLSAIM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLSAICFGR_PLLSAIM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLSAICFGR_PLLSAIM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLSAICFGR_PLLSAIM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLSAICFGR_PLLSAIM              0x0000003FU
+#define  RCC_PLLSAICFGR_PLLSAIM_0            0x00000001U
+#define  RCC_PLLSAICFGR_PLLSAIM_1            0x00000002U
+#define  RCC_PLLSAICFGR_PLLSAIM_2            0x00000004U
+#define  RCC_PLLSAICFGR_PLLSAIM_3            0x00000008U
+#define  RCC_PLLSAICFGR_PLLSAIM_4            0x00000010U
+#define  RCC_PLLSAICFGR_PLLSAIM_5            0x00000020U
 
-#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
 
-#define  RCC_PLLSAICFGR_PLLSAIP              ((uint32_t)0x00030000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_0            ((uint32_t)0x00010000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_1            ((uint32_t)0x00020000U)
+#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
+#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
+#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
 
-#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001FU)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00U)
-#define  RCC_DCKCFGR_SAI1SRC                 ((uint32_t)0x00300000U)
-#define  RCC_DCKCFGR_SAI1SRC_0               ((uint32_t)0x00100000U)
-#define  RCC_DCKCFGR_SAI1SRC_1               ((uint32_t)0x00200000U)
-#define  RCC_DCKCFGR_SAI2SRC                 ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR_SAI2SRC_0               ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR_SAI2SRC_1               ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000U)
-#define  RCC_DCKCFGR_I2S1SRC                 ((uint32_t)0x06000000U)
-#define  RCC_DCKCFGR_I2S1SRC_0               ((uint32_t)0x02000000U)
-#define  RCC_DCKCFGR_I2S1SRC_1               ((uint32_t)0x04000000U)
-#define  RCC_DCKCFGR_I2S2SRC                 ((uint32_t)0x18000000U)
-#define  RCC_DCKCFGR_I2S2SRC_0               ((uint32_t)0x08000000U)
-#define  RCC_DCKCFGR_I2S2SRC_1               ((uint32_t)0x10000000U)
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_SAI1SRC                 0x00300000U
+#define  RCC_DCKCFGR_SAI1SRC_0               0x00100000U
+#define  RCC_DCKCFGR_SAI1SRC_1               0x00200000U
+#define  RCC_DCKCFGR_SAI2SRC                 0x00C00000U
+#define  RCC_DCKCFGR_SAI2SRC_0               0x00400000U
+#define  RCC_DCKCFGR_SAI2SRC_1               0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
+#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
+#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
+#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
+#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
+#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
+#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
 
 /********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          ((uint32_t)0x00000001U)
-#define  RCC_CKGATENR_AHB2APB2_CKEN          ((uint32_t)0x00000002U)
-#define  RCC_CKGATENR_CM4DBG_CKEN            ((uint32_t)0x00000004U)
-#define  RCC_CKGATENR_SPARE_CKEN             ((uint32_t)0x00000008U)
-#define  RCC_CKGATENR_SRAM_CKEN              ((uint32_t)0x00000010U)
-#define  RCC_CKGATENR_FLITF_CKEN             ((uint32_t)0x00000020U)
-#define  RCC_CKGATENR_RCC_CKEN               ((uint32_t)0x00000040U)
+#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
+#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
+#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
+#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
+#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
+#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
+#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
 
 /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR2_CECSEL                 ((uint32_t)0x04000000U)
-#define  RCC_DCKCFGR2_CK48MSEL               ((uint32_t)0x08000000U)
-#define  RCC_DCKCFGR2_SDIOSEL                ((uint32_t)0x10000000U)
-#define  RCC_DCKCFGR2_SPDIFRXSEL             ((uint32_t)0x20000000U)
+#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
+#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
+#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
+#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
+#define  RCC_DCKCFGR2_SPDIFRXSEL             0x20000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5595,379 +5602,379 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -5975,150 +5982,152 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003U)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
 
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030U)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
 
 /*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003U)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
 
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000CU)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
 
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0U)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080U)        /*!<Bit 2 */
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
 
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100U)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200U)        /*!<ClocK STRobing edge      */
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
 
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00U)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
 
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000U)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000U)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000U)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000U)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000U)        /*!<No Divider Configuration   */
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
 
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000U)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000U)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000U)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000U)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000U)        /*!<Bit 3  */
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
 
 /*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007U)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
 
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008U)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010U)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020U)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040U)        /*!<Muate value                      */
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
 
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80U)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100U)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200U)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400U)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800U)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000U)        /*!<Bit 5 */
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000U)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
 
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000U)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000U)        /*!<Bit 1 */
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
 
 /******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FFU)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
 
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00U)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000U)        /*!<Bit 6 */
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
 
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000U)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000U)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000U)        /*!<Frame Synchronization OFFset      */
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
 
 /******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001FU)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010U)        /*!<Bit 4 */
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
 
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0U)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
 
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00U)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
 
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000U)        /*!<SLOTEN[15:0] (Slot Enable)  */
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
 
 /*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001U)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002U)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004U)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008U)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010U)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020U)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040U)        /*!<Late frame synchronization detection interrupt enable          */
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
 
 /********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001U)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002U)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004U)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008U)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010U)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020U)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040U)         /*!<Late frame synchronization detection           */
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
 
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000U)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000U)         /*!<Bit 2 */
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
 
 /******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001U)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002U)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004U)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008U)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010U)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020U)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040U)        /*!<Clear Late frame synchronization detection           */
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
 
 /******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFFU)        
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
 
 /******************************************************************************/
 /*                                                                            */
@@ -6126,75 +6135,75 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SPDIFRX_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                  ((uint32_t)0x00000003U)        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                  ((uint32_t)0x00000004U)        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                   ((uint32_t)0x00000008U)        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                    ((uint32_t)0x00000030U)        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                     ((uint32_t)0x00000040U)        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                     ((uint32_t)0x00000080U)        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                    ((uint32_t)0x00000100U)        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                    ((uint32_t)0x00000200U)        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                  ((uint32_t)0x00000400U)        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                    ((uint32_t)0x00000800U)        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                     ((uint32_t)0x00003000U)        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                      ((uint32_t)0x00004000U)        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                    ((uint32_t)0x00070000U)        /*!<SPDIFRX input selection */
+#define  SPDIFRX_CR_SPDIFEN                  0x00000003U        /*!<Peripheral Block Enable                      */
+#define  SPDIFRX_CR_RXDMAEN                  0x00000004U        /*!<Receiver DMA Enable for data flow            */
+#define  SPDIFRX_CR_RXSTEO                   0x00000008U        /*!<Stereo Mode                                  */
+#define  SPDIFRX_CR_DRFMT                    0x00000030U        /*!<RX Data format                               */
+#define  SPDIFRX_CR_PMSK                     0x00000040U        /*!<Mask Parity error bit                        */
+#define  SPDIFRX_CR_VMSK                     0x00000080U        /*!<Mask of Validity bit                         */
+#define  SPDIFRX_CR_CUMSK                    0x00000100U        /*!<Mask of channel status and user bits         */
+#define  SPDIFRX_CR_PTMSK                    0x00000200U        /*!<Mask of Preamble Type bits                   */
+#define  SPDIFRX_CR_CBDMAEN                  0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
+#define  SPDIFRX_CR_CHSEL                    0x00000800U        /*!<Channel Selection                            */
+#define  SPDIFRX_CR_NBTR                     0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
+#define  SPDIFRX_CR_WFA                      0x00004000U        /*!<Wait For Activity     */
+#define  SPDIFRX_CR_INSEL                    0x00070000U        /*!<SPDIFRX input selection */
 
 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                   ((uint32_t)0x00000001U)        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE                  ((uint32_t)0x00000002U)        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                   ((uint32_t)0x00000004U)        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                    ((uint32_t)0x00000008U)        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                   ((uint32_t)0x00000010U)        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE                  ((uint32_t)0x00000020U)        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                    ((uint32_t)0x00000040U)        /*!<Serial Interface Error Interrupt Enable            */
+#define  SPDIFRX_IMR_RXNEIE                   0x00000001U        /*!<RXNE interrupt enable                              */
+#define  SPDIFRX_IMR_CSRNEIE                  0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
+#define  SPDIFRX_IMR_PERRIE                   0x00000004U        /*!<Parity error interrupt enable                      */
+#define  SPDIFRX_IMR_OVRIE                    0x00000008U        /*!<Overrun error Interrupt Enable                     */
+#define  SPDIFRX_IMR_SBLKIE                   0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
+#define  SPDIFRX_IMR_SYNCDIE                  0x00000020U        /*!<Synchronization Done                               */
+#define  SPDIFRX_IMR_IFEIE                    0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
 
 /*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   ((uint32_t)0x00000001U)       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  ((uint32_t)0x00000002U)       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   ((uint32_t)0x00000004U)       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    ((uint32_t)0x00000008U)       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    ((uint32_t)0x00000010U)       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  ((uint32_t)0x00000020U)       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   ((uint32_t)0x00000040U)       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   ((uint32_t)0x00000080U)       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   ((uint32_t)0x00000100U)       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 ((uint32_t)0x7FFF0000U)       /*!<Duration of 5 symbols counted with SPDIFRX_clk          */
+#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
+#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
+#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
+#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
+#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
+#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
+#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
+#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
+#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
+#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with SPDIFRX_clk          */
 
 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               ((uint32_t)0x00000004U)       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                ((uint32_t)0x00000008U)       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                ((uint32_t)0x00000010U)       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              ((uint32_t)0x00000020U)       /*!<Clears the Synchronization Done flag                 */
+#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
+#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
+#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
+#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    ((uint32_t)0x00FFFFFFU)        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    ((uint32_t)0x01000000U)        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     ((uint32_t)0x02000000U)        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     ((uint32_t)0x04000000U)        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     ((uint32_t)0x08000000U)        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    ((uint32_t)0x30000000U)        /*!<Preamble Type         */
+#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
+#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
+#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
+#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
+#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    ((uint32_t)0xFFFFFF00U)        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    ((uint32_t)0x00000030U)        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     ((uint32_t)0x00000008U)        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     ((uint32_t)0x00000004U)        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     ((uint32_t)0x00000002U)        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    ((uint32_t)0x00000001U)        /*!<Parity Error bit      */
+#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
+#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
+#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
+#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
+#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 ((uint32_t)0xFFFF0000U)        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 ((uint32_t)0x0000FFFFU)        /*!<Data value Channel A      */
+#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
+#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
 
 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                     ((uint32_t)0x0000FFFFU)        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                      ((uint32_t)0x00FF0000U)        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                     ((uint32_t)0x01000000U)        /*!<Start Of Block                  */
+#define  SPDIFRX_CSR_USR                     0x0000FFFFU        /*!<User data information           */
+#define  SPDIFRX_CSR_CS                      0x00FF0000U        /*!<Channel A status information    */
+#define  SPDIFRX_CSR_SOB                     0x01000000U        /*!<Start Of Block                  */
 
 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                 ((uint32_t)0x000013FFU)        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                 ((uint32_t)0x1FFF0000U)        /*!<Threshold HIGH     */
+#define  SPDIFRX_DIR_THI                 0x000013FFU        /*!<Threshold LOW      */
+#define  SPDIFRX_DIR_TLO                 0x1FFF0000U        /*!<Threshold HIGH     */
 
 
 /******************************************************************************/
@@ -6203,148 +6212,148 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6352,85 +6361,85 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 ((uint32_t)0x00001000U)            /*!<Asynchronous start enable */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6438,290 +6447,290 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
-#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100U) /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  ((uint32_t)0x00000C00U) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008U) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009U) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000AU) /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080U) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090U) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0U) /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
 
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600U) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800U) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900U) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00U) /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
 
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000U) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000U) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000U) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000U) /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006U) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008U) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009U) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000AU) /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060U) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080U) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090U) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0U) /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600U) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800U) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900U) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00U) /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
 
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000U) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000U) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000U) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000U) /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006U) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008U) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009U) /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060U) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080U) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090U) /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
 
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600U) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800U) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900U) /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
 
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000U) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000U) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000U) /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006U) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008U) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009U) /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
 
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060U) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008U) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009U) /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
 
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600U) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800U) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900U) /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
 
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000U) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000U) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000U) /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************  Bit definition for SYSCFG_CFGR register  ****************/  
-#define SYSCFG_CFGR_FMPI2C1_SCL         ((uint32_t)0x00000001U) /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         ((uint32_t)0x00000002U) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6729,298 +6738,298 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -7029,82 +7038,82 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7112,35 +7121,54 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -7149,46 +7177,46 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 
 /******************************************************************************/
@@ -7197,678 +7225,678 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                ((uint32_t)0x00000004U)         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               ((uint32_t)0x00000008U)         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 ((uint32_t)0x00000010U)         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                ((uint32_t)0x00000020U)         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 ((uint32_t)0x00000040U)         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                ((uint32_t)0x00000080U)         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    ((uint32_t)0x00001000U)         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 ((uint32_t)0x00080000U)         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  ((uint32_t)0x00100000U)         /*!< OTG version  */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
 
 /********************  Bit definition for USB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition for USB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  ((uint32_t)0x00100000U)            /*!< Change in ID pin input value           */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
 
 /********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status   */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status   */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
 
 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
 
 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                ((uint32_t)0x00000020U)            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
 
 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  ((uint32_t)0x08000000U)            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt        */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 ((uint32_t)0x08000000U)            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask        */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth                */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)         /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)           /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 ((uint32_t)0x00010000U)              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  ((uint32_t)0x00200000U)              /*!< USB VBUS Detection Enable */
+#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
 
 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
  
 /********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               ((uint32_t)0x00000001U)            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              ((uint32_t)0x00000002U)            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                ((uint32_t)0x0000003CU)            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             ((uint32_t)0x00000040U)            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              ((uint32_t)0x00000080U)            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            ((uint32_t)0x00000F00U)            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              ((uint32_t)0x00001000U)            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              ((uint32_t)0x00006000U)            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              ((uint32_t)0x00008000U)            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             ((uint32_t)0x00010000U)            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            ((uint32_t)0x001E0000U)            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             ((uint32_t)0x00E00000U)            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              ((uint32_t)0x01000000U)            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          ((uint32_t)0x0E000000U)            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              ((uint32_t)0x10000000U)            /*!< Enable best effort service latency                     */
+#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
 
 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
 
 /********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset                 */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power                 */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask                       */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
 
 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth                    */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
 
 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status                       */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake                  */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable                  */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
 
 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space available */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 ((uint32_t)0x00000020U)            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 
 /**
@@ -7943,10 +7971,12 @@ typedef struct
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
 
 /******************************* SAI Instances ********************************/
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
                                      ((PERIPH) == SAI1_Block_B) || \
                                      ((PERIPH) == SAI2_Block_A) || \
                                      ((PERIPH) == SAI2_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
 
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f4xx.h
index cc98c45fe4..a762f02f45 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.c
index da6261b3d7..3879e97c9a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -108,9 +108,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -341,7 +342,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -506,7 +507,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -695,7 +696,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -772,18 +773,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h
index e2fd78a835..fd93102bec 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f401xc.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -386,7 +386,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -663,17 +664,14 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0803FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                        */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(64 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                               */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                        */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                            */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                     */
+#define FLASH_END             0x0803FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -749,23 +747,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -857,334 +855,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1192,30 +1190,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1223,15 +1221,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1245,161 +1243,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1408,154 +1406,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1563,97 +1561,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1661,235 +1659,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1909,22 +1907,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1944,57 +1942,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2002,97 +2000,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2100,20 +2098,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2122,47 +2120,47 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2173,368 +2171,370 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2542,379 +2542,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2924,157 +2924,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3082,84 +3082,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3167,199 +3167,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3367,298 +3367,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3667,82 +3667,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3750,35 +3750,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3787,46 +3806,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3834,654 +3853,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h
index 6da9da3660..e4b91ec5c3 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c
index 5d23c5c0fd..a3dbba5ab7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -110,9 +110,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -339,7 +340,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -504,7 +505,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -693,7 +694,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -770,18 +771,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h
index 50a34c1556..e9625104d9 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h
@@ -2,19 +2,19 @@
   ******************************************************************************
   * @file    stm32f429xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F429xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
   *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
   *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -1054,21 +1054,21 @@ USB_OTG_HostChannelTypeDef;
 /** @addtogroup Peripheral_memory_map
   * @{
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x081FFFFF) /*!< FLASH end address */
-#define CCMDATARAM_END        ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -1077,137 +1077,137 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U) 
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
 #define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
 
 /*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
 
 /*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1339,360 +1339,365 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1701,1319 +1706,1319 @@ USB_OTG_HostChannelTypeDef;
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFF)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3021,15 +3026,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3037,90 +3042,92 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3134,213 +3141,260 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
-#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 
-/********************  Bits definition for DCMI_MISR register  ****************/
-#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
-#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
-#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
-#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
-#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
-#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
 /*                             DMA Controller                                 */
 /*                                                                            */
 /******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3351,141 +3405,165 @@ USB_OTG_HostChannelTypeDef;
 
 /********************  Bit definition for DMA2D_CR register  ******************/
 
-#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
 
 /********************  Bit definition for DMA2D_ISR register  *****************/
 
-#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
 
-/********************  Bit definition for DMA2D_IFSR register  ****************/
+/********************  Bit definition for DMA2D_IFCR register  ****************/
 
-#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
-#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
-#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
-#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
 
 /********************  Bit definition for DMA2D_FGMAR register  ***************/
 
-#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_FGOR register  ****************/
 
-#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_BGMAR register  ***************/
 
-#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGOR register  ****************/
 
-#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
 
-#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
-#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
-#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
 
 /********************  Bit definition for DMA2D_FGCOLR register  **************/
 
-#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
 
 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
 
-#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
-#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
-#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
 
 /********************  Bit definition for DMA2D_BGCOLR register  **************/
 
-#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
 
 /********************  Bit definition for DMA2D_FGCMAR register  **************/
 
-#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGCMAR register  **************/
 
-#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OPFCCR register  **************/
 
-#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
 
 /********************  Bit definition for DMA2D_OCOLR register  ***************/
 
 /*!<Mode_ARGB8888/RGB888 */
 
-#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
 
 /*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
 
 /*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
 
 /*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
 
 /********************  Bit definition for DMA2D_OMAR register  ****************/
 
-#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OOR register  *****************/
 
-#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_NLR register  *****************/
 
-#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
 
 /********************  Bit definition for DMA2D_LWR register  *****************/
 
-#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
 
 /********************  Bit definition for DMA2D_AMTCR register  ***************/
 
-#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
-#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
-
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
 
 /********************  Bit definition for DMA2D_FGCLUT register  **************/
                                                                      
@@ -3499,154 +3577,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3654,108 +3732,108 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
 #define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) 
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3763,1006 +3841,1006 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
 
 /******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty                                  */
+#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty                                  */
+#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty                                  */
+#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
+#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
+#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
+#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
                                             
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
 
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
 
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
 
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
 
 /******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
 
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
 
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
 
 /******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
 
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
 
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
 
 
 
@@ -4772,235 +4850,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -5020,22 +5098,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -5055,57 +5133,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5113,97 +5191,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000F)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5211,20 +5289,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -5235,145 +5313,148 @@ USB_OTG_HostChannelTypeDef;
 
 /********************  Bit definition for LTDC_SSCR register  *****************/
 
-#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
 
 /********************  Bit definition for LTDC_BPCR register  *****************/
 
-#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
 
 /********************  Bit definition for LTDC_AWCR register  *****************/
 
-#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
 
 /********************  Bit definition for LTDC_TWCR register  *****************/
 
-#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
 
 /********************  Bit definition for LTDC_GCR register  ******************/
 
-#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
-#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
 
 /********************  Bit definition for LTDC_SRCR register  *****************/
 
-#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
 
 /********************  Bit definition for LTDC_BCCR register  *****************/
 
-#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
 
 /********************  Bit definition for LTDC_IER register  ******************/
 
-#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
 
 /********************  Bit definition for LTDC_ISR register  ******************/
 
-#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_ICR register  ******************/
 
-#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_LIPCR register  ****************/
 
-#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
 
 /********************  Bit definition for LTDC_CPSR register  *****************/
 
-#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
 
 /********************  Bit definition for LTDC_CDSR register  *****************/
 
-#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
 
 /********************  Bit definition for LTDC_LxCR register  *****************/
 
-#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
 
 /********************  Bit definition for LTDC_LxWHPCR register  **************/
 
-#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
 
 /********************  Bit definition for LTDC_LxWVPCR register  **************/
 
-#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
 
 /********************  Bit definition for LTDC_LxCKCR register  ***************/
 
-#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
 
 /********************  Bit definition for LTDC_LxPFCR register  ***************/
 
-#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
 
 /********************  Bit definition for LTDC_LxCACR register  ***************/
 
-#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
 
 /********************  Bit definition for LTDC_LxDCCR register  ***************/
 
-#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
                                 
 /********************  Bit definition for LTDC_LxBFCR register  ***************/
 
-#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
 
 /********************  Bit definition for LTDC_LxCFBAR register  **************/
 
-#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
 
 /********************  Bit definition for LTDC_LxCFBLR register  **************/
 
-#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
 
 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
 
-#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
 
 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
 
-#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
 
 
 /******************************************************************************/
@@ -5382,39 +5463,39 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
@@ -5422,16 +5503,16 @@ USB_OTG_HostChannelTypeDef;
 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -5442,515 +5523,515 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
-#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
-#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
-#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
-#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
-#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
-#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
-#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
-#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
-#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
 
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
-#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
 
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
-#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
-#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
-#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
 
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
-#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
-#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
 
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
-#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
-#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
-#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 
 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040)
-#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080)
-#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100)
-#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200)
-#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400)
-#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800)
-#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000)
-#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000)
-#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000)
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
 
-#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000)
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000)
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000)
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000)
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000)
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
 
-#define  RCC_PLLSAICFGR_PLLSAIR              ((uint32_t)0x70000000)
-#define  RCC_PLLSAICFGR_PLLSAIR_0            ((uint32_t)0x10000000)
-#define  RCC_PLLSAICFGR_PLLSAIR_1            ((uint32_t)0x20000000)
-#define  RCC_PLLSAICFGR_PLLSAIR_2            ((uint32_t)0x40000000)
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
-#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
-#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
-#define  RCC_DCKCFGR_SAI1ASRC_0              ((uint32_t)0x00100000)
-#define  RCC_DCKCFGR_SAI1ASRC_1              ((uint32_t)0x00200000)
-#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
-#define  RCC_DCKCFGR_SAI1BSRC_0              ((uint32_t)0x00400000)
-#define  RCC_DCKCFGR_SAI1BSRC_1              ((uint32_t)0x00800000)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
+#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
+#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
+#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
+#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
+#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
+#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 
 /******************************************************************************/
@@ -5959,15 +6040,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5975,379 +6056,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -6355,150 +6436,152 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
 
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
 
 /*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
 
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
 
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
 
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
 
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
 
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
 
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000)        /*!<Bit 3  */
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
 
 /*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
 
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
 
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
 
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
 
 /******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
 
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
 
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
 
 /******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
-                                     
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
 
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
 
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
+
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
 
 /*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
 
 /********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
 
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000)         /*!<Bit 2 */
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
 
 /******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
 
 /******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
 
 
 /******************************************************************************/
@@ -6507,157 +6590,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6665,84 +6748,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6750,290 +6833,290 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
-#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100) /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
 
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000A) /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0) /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
 
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00) /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
 
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000) /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000A) /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0) /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00) /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
 
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000) /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009) /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090) /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
 
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900) /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
 
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000) /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009) /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
 
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009) /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
 
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900) /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
 
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000) /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7041,298 +7124,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFF)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -7341,82 +7424,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FF)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000F)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7424,35 +7507,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -7461,46 +7563,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -7508,91 +7610,91 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
 
 /* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
   
 /* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
 
 /* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
 
 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
@@ -7606,334 +7708,334 @@ USB_OTG_HostChannelTypeDef;
    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
 
 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
 
 /* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
 
 /* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
 
 /* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
 
 /* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
 
 /* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
 
 /* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
 
 /* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
 
 /* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
 
 /******************************************************************************/
 /*                Ethernet MMC Registers bits definition                      */
 /******************************************************************************/
 
 /* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
 
 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
 
 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
 
 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
 
 /******************************************************************************/
 /*               Ethernet PTP Registers bits definition                       */
 /******************************************************************************/
 
 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
 
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
 
 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
 
 /* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
 
 /* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
 
 /* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
 
 /* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
+#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
 
 /******************************************************************************/
 /*                 Ethernet DMA Registers bits definition                     */
 /******************************************************************************/
 
 /* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
 
 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
 
 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
 
 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
 
 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
 
 /* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
   /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
 
 /* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
 
 /* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
 
 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7941,654 +8043,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001)            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002)            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200)            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400)            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800)            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000)            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000)            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000)            /*!< B-session valid          */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003)            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004)            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100)            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000)            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000)            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000)            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002)            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004)            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008)            /*!< Global OUT NAK status   */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080)            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100)            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200)            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400)            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFF)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFF)            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001)            /*!< Suspend status   */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008)            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001E)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000)            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000)            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000)            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000)            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000)            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000)            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000)            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000)            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000)            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000)            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000)            /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001)            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002)            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010)            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020)            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFF)            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFF)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001)            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008)            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010)            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080)            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400)            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800)            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000)            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000)            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000)            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000)            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000)            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt        */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008)            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010)            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040)            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080)            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400)            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800)            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000)            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000)            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000)            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000)            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000)            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000)            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt mask        */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFF)            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFF)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000F)            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFF)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFF)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFF)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFF)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000)            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFF)            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000)            /*!< Endpoint 0 TxFIFO depth                */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFF)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFF)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FC)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFF)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002)            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000)            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000)            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000)            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000)            /*!< VBUS sensing disable option                                  */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002)            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFF)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001)            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002)            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004)            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010)            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020)            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040)            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080)            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100)            /*!< Port reset    */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFF)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007F)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFF)            /*!< IN endpoint TxFIFO space available */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFF)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FF)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 
 /**
@@ -8680,8 +8782,10 @@ USB_OTG_HostChannelTypeDef;
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
 
 /******************************* SAI Instances ********************************/
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
                                      ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
 
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
@@ -8969,15 +9073,15 @@ USB_OTG_HostChannelTypeDef;
 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
 
 /****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280 /* in Bytes */
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
 
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6    /* Including EP0 */
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096 /* in Bytes */
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
 
 /******************************************************************************/
 /*  For a painless codes migration between the STM32F4xx device product       */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h
index 29a3431e33..5ef1703d3d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -121,16 +121,16 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.4.2
+  * @brief CMSIS version number V2.5.0
   */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F4xx_CMSIS_DEVICE_VERSION        ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION))
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION))
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c
index 3aad0bae33..09b87318d4 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -109,9 +109,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -334,7 +335,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -499,7 +500,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -688,7 +689,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -755,17 +756,27 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00000201;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h
index 5c8214d2e6..f491be4263 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f469xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F469xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -1133,22 +1133,22 @@ typedef struct
 /** @addtogroup Peripheral_memory_map
   * @{
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(160 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x20028000U) /*!< SRAM2(32 KB) base address in the alias region                              */
-#define SRAM3_BASE            ((uint32_t)0x20030000U) /*!< SRAM3(128 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QuadSPI registers base address                                            */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22500000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         ((uint32_t)0x22600000U) /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x081FFFFFU) /*!< FLASH end address */
-#define CCMDATARAM_END        ((uint32_t)0x1000FFFFU) /*!< CCM data RAM end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(160 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x20028000U /*!< SRAM2(32 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20030000U /*!< SRAM3(128 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                            */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -1270,24 +1270,24 @@ typedef struct
 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
 
 /*!< Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000U)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1420,334 +1420,334 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)        /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)        /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1755,30 +1755,30 @@ typedef struct
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1787,1320 +1787,1320 @@ typedef struct
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001U)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002U)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004U)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008U)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010U)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020U)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040U)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080U)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000U)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000U)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800U)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00U)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001U)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002U)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004U)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008U)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010U)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020U)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040U)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080U)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100U)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200U)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400U)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800U)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000U)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000U)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000U)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000U)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000U)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000U)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000U)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000U)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000U)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000U)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000U)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000U)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000U)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000U)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000U)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000U)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001U)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002U)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004U)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008U)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010U)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020U)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040U)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080U)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100U)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200U)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400U)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800U)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000U)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000U)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000U)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000U)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000U)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000U)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000U)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000U)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000U)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000U)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000U)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000U)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000U)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000U)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000U)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000U)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001U)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002U)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004U)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008U)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010U)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020U)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040U)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080U)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100U)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200U)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400U)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800U)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000U)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000U)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000U)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000U)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000U)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000U)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000U)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000U)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000U)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000U)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000U)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000U)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000U)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000U)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000U)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000U)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001U)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002U)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004U)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008U)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010U)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020U)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040U)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080U)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100U)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200U)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400U)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800U)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000U)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000U)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000U)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000U)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000U)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000U)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000U)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000U)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000U)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000U)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000U)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000U)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000U)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000U)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000U)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000U)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3108,15 +3108,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 
 /******************************************************************************/
@@ -3125,92 +3125,92 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002U)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000U)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable*/
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01U)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02U)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFFU)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFFU)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FFU)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00U)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3224,51 +3224,59 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001U)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002U)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004U)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008U)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010U)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020U)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040U)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080U)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800U)
-#define DCMI_CR_OUTEN                        ((uint32_t)0x00002000U)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000U)
-#define DCMI_CR_BSM_0                        ((uint32_t)0x00010000U)
-#define DCMI_CR_BSM_1                        ((uint32_t)0x00020000U)
-#define DCMI_CR_OEBS                         ((uint32_t)0x00040000U)
-#define DCMI_CR_LSM                          ((uint32_t)0x00080000U)
-#define DCMI_CR_OELS                         ((uint32_t)0x00100000U)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_OUTEN                        0x00002000U
+#define DCMI_CR_ENABLE                       0x00004000U
+#define DCMI_CR_BSM_0                        0x00010000U
+#define DCMI_CR_BSM_1                        0x00020000U
+#define DCMI_CR_OEBS                         0x00040000U
+#define DCMI_CR_LSM                          0x00080000U
+#define DCMI_CR_OELS                         0x00100000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001U)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002U)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004U)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001U)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002U)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004U)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008U)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010U)
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001U)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002U)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004U)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008U)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010U)
-
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 /********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   ((uint32_t)0x00000001U)
-#define DCMI_MIS_OVR_MIS                     ((uint32_t)0x00000002U)
-#define DCMI_MIS_ERR_MIS                     ((uint32_t)0x00000004U)
-#define DCMI_MIS_VSYNC_MIS                   ((uint32_t)0x00000008U)
-#define DCMI_MIS_LINE_MIS                    ((uint32_t)0x00000010U)
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
@@ -3278,40 +3286,40 @@ typedef struct
 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001U)
-#define DCMI_ICR_OVR_ISC                     ((uint32_t)0x00000002U)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004U)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008U)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010U)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
 
 /********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        ((uint32_t)0x000000FFU)
-#define DCMI_ESCR_LSC                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESCR_LEC                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESCR_FEC                        ((uint32_t)0xFF000000U)
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
 
 /********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        ((uint32_t)0x000000FFU)
-#define DCMI_ESUR_LSU                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESUR_LEU                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESUR_FEU                        ((uint32_t)0xFF000000U)
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
 
 /********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  ((uint32_t)0x00003FFFU)
-#define DCMI_CWSTRT_VST                      ((uint32_t)0x1FFF0000U)
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
 
 /********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   ((uint32_t)0x00003FFFU)
-#define DCMI_CWSIZE_VLINE                    ((uint32_t)0x3FFF0000U)
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
 
 /********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        ((uint32_t)0x000000FFU)
-#define DCMI_DR_BYTE1                        ((uint32_t)0x0000FF00U)
-#define DCMI_DR_BYTE2                        ((uint32_t)0x00FF0000U)
-#define DCMI_DR_BYTE3                        ((uint32_t)0xFF000000U)
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3319,161 +3327,161 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3484,34 +3492,36 @@ typedef struct
 
 /********************  Bit definition for DMA2D_CR register  ******************/
 
-#define DMA2D_CR_START                     ((uint32_t)0x00000001U)               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002U)               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004U)               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100U)               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200U)               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400U)               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800U)               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000U)               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000U)               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      ((uint32_t)0x00030000U)               /*!< DMA2D Mode */
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
 
 /********************  Bit definition for DMA2D_ISR register  *****************/
 
-#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001U)               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002U)               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004U)               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008U)               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010U)               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020U)               /*!< Configuration Error Interrupt Flag */
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
 
 /********************  Bit definition for DMA2D_IFCR register  ****************/
 
-#define DMA2D_IFCR_CTEIF                   ((uint32_t)0x00000001U)               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   ((uint32_t)0x00000002U)               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   ((uint32_t)0x00000004U)               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  ((uint32_t)0x00000008U)               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  ((uint32_t)0x00000010U)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   ((uint32_t)0x00000020U)               /*!< Clears Configuration Error Interrupt Flag    */
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
 
 /* Legacy defines */
 #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
@@ -3523,110 +3533,124 @@ typedef struct
 
 /********************  Bit definition for DMA2D_FGMAR register  ***************/
 
-#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_FGOR register  ****************/
 
-#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_BGMAR register  ***************/
 
-#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGOR register  ****************/
 
-#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
 
-#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000FU)               /*!< Color mode */
-#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010U)               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020U)               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00U)               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000U)               /*!< Alpha mode */
-#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000U)               /*!< Alpha value */
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
 
 /********************  Bit definition for DMA2D_FGCOLR register  **************/
 
-#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FFU)               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00U)               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000U)               /*!< Red Value */   
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
 
 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
 
-#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000FU)               /*!< Color mode */
-#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010U)               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020U)               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00U)               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000U)               /*!< Alpha Mode */
-#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000U)               /*!< Alpha value */
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
 
 /********************  Bit definition for DMA2D_BGCOLR register  **************/
 
-#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FFU)               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00U)               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000U)               /*!< Red Value */
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
 
 /********************  Bit definition for DMA2D_FGCMAR register  **************/
 
-#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGCMAR register  **************/
 
-#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OPFCCR register  **************/
 
-#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007U)               /*!< Color mode */
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
 
 /********************  Bit definition for DMA2D_OCOLR register  ***************/
 
 /*!<Mode_ARGB8888/RGB888 */
 
-#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FFU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
 
 /*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800U)               /*!< Red Value */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
 
 /*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
 
 /*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
 
 /********************  Bit definition for DMA2D_OMAR register  ****************/
 
-#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OOR register  *****************/
 
-#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_NLR register  *****************/
 
-#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFFU)               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000U)               /*!< Pixel per Lines */
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
 
 /********************  Bit definition for DMA2D_LWR register  *****************/
 
-#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFFU)               /*!< Line Watermark */
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
 
 /********************  Bit definition for DMA2D_AMTCR register  ***************/
 
-#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001U)               /*!< Enable */
-#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00U)               /*!< Dead Time */
-
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
 
 /********************  Bit definition for DMA2D_FGCLUT register  **************/
                                                                      
@@ -3639,1188 +3663,1188 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for DSI_VR register  *****************/
-#define DSI_VR                         ((uint32_t)0x3133302AU)               /*!< DSI Host Version */
+#define DSI_VR                         0x3133302AU               /*!< DSI Host Version */
 
 /*******************  Bit definition for DSI_CR register  *****************/
-#define DSI_CR_EN                      ((uint32_t)0x00000001U)               /*!< DSI Host power up and reset */
+#define DSI_CR_EN                      0x00000001U               /*!< DSI Host power up and reset */
 
 /*******************  Bit definition for DSI_CCR register  ****************/
-#define DSI_CCR_TXECKDIV               ((uint32_t)0x000000FFU)               /*!< TX Escape Clock Division */
-#define DSI_CCR_TXECKDIV0              ((uint32_t)0x00000001U)
-#define DSI_CCR_TXECKDIV1              ((uint32_t)0x00000002U)
-#define DSI_CCR_TXECKDIV2              ((uint32_t)0x00000004U)
-#define DSI_CCR_TXECKDIV3              ((uint32_t)0x00000008U)
-#define DSI_CCR_TXECKDIV4              ((uint32_t)0x00000010U)
-#define DSI_CCR_TXECKDIV5              ((uint32_t)0x00000020U)
-#define DSI_CCR_TXECKDIV6              ((uint32_t)0x00000040U)
-#define DSI_CCR_TXECKDIV7              ((uint32_t)0x00000080U)
+#define DSI_CCR_TXECKDIV               0x000000FFU               /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0              0x00000001U
+#define DSI_CCR_TXECKDIV1              0x00000002U
+#define DSI_CCR_TXECKDIV2              0x00000004U
+#define DSI_CCR_TXECKDIV3              0x00000008U
+#define DSI_CCR_TXECKDIV4              0x00000010U
+#define DSI_CCR_TXECKDIV5              0x00000020U
+#define DSI_CCR_TXECKDIV6              0x00000040U
+#define DSI_CCR_TXECKDIV7              0x00000080U
 
-#define DSI_CCR_TOCKDIV                ((uint32_t)0x0000FF00U)               /*!< Timeout Clock Division */
-#define DSI_CCR_TOCKDIV0               ((uint32_t)0x00000100U)
-#define DSI_CCR_TOCKDIV1               ((uint32_t)0x00000200U)
-#define DSI_CCR_TOCKDIV2               ((uint32_t)0x00000400U)
-#define DSI_CCR_TOCKDIV3               ((uint32_t)0x00000800U)
-#define DSI_CCR_TOCKDIV4               ((uint32_t)0x00001000U)
-#define DSI_CCR_TOCKDIV5               ((uint32_t)0x00002000U)
-#define DSI_CCR_TOCKDIV6               ((uint32_t)0x00004000U)
-#define DSI_CCR_TOCKDIV7               ((uint32_t)0x00008000U)
+#define DSI_CCR_TOCKDIV                0x0000FF00U               /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0               0x00000100U
+#define DSI_CCR_TOCKDIV1               0x00000200U
+#define DSI_CCR_TOCKDIV2               0x00000400U
+#define DSI_CCR_TOCKDIV3               0x00000800U
+#define DSI_CCR_TOCKDIV4               0x00001000U
+#define DSI_CCR_TOCKDIV5               0x00002000U
+#define DSI_CCR_TOCKDIV6               0x00004000U
+#define DSI_CCR_TOCKDIV7               0x00008000U
 
 /*******************  Bit definition for DSI_LVCIDR register  *************/
-#define DSI_LVCIDR_VCID                ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
-#define DSI_LVCIDR_VCID0               ((uint32_t)0x00000001U)
-#define DSI_LVCIDR_VCID1               ((uint32_t)0x00000002U)
+#define DSI_LVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0               0x00000001U
+#define DSI_LVCIDR_VCID1               0x00000002U
 
 /*******************  Bit definition for DSI_LCOLCR register  *************/
-#define DSI_LCOLCR_COLC                ((uint32_t)0x0000000FU)               /*!< Color Coding */
-#define DSI_LCOLCR_COLC0               ((uint32_t)0x00000001U)
-#define DSI_LCOLCR_COLC1               ((uint32_t)0x00000020U)
-#define DSI_LCOLCR_COLC2               ((uint32_t)0x00000040U)
-#define DSI_LCOLCR_COLC3               ((uint32_t)0x00000080U)
+#define DSI_LCOLCR_COLC                0x0000000FU               /*!< Color Coding */
+#define DSI_LCOLCR_COLC0               0x00000001U
+#define DSI_LCOLCR_COLC1               0x00000020U
+#define DSI_LCOLCR_COLC2               0x00000040U
+#define DSI_LCOLCR_COLC3               0x00000080U
 
-#define DSI_LCOLCR_LPE                 ((uint32_t)0x00000100U)               /*!< Loosly Packet Enable */
+#define DSI_LCOLCR_LPE                 0x00000100U               /*!< Loosly Packet Enable */
 
 /*******************  Bit definition for DSI_LPCR register  ***************/
-#define DSI_LPCR_DEP                   ((uint32_t)0x00000001U)               /*!< Data Enable Polarity */
-#define DSI_LPCR_VSP                   ((uint32_t)0x00000002U)               /*!< VSYNC Polarity */
-#define DSI_LPCR_HSP                   ((uint32_t)0x00000004U)               /*!< HSYNC Polarity */
+#define DSI_LPCR_DEP                   0x00000001U               /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP                   0x00000002U               /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP                   0x00000004U               /*!< HSYNC Polarity */
 
 /*******************  Bit definition for DSI_LPMCR register  **************/
-#define DSI_LPMCR_VLPSIZE              ((uint32_t)0x000000FFU)               /*!< VACT Largest Packet Size */
-#define DSI_LPMCR_VLPSIZE0             ((uint32_t)0x00000001U)
-#define DSI_LPMCR_VLPSIZE1             ((uint32_t)0x00000002U)
-#define DSI_LPMCR_VLPSIZE2             ((uint32_t)0x00000004U)
-#define DSI_LPMCR_VLPSIZE3             ((uint32_t)0x00000008U)
-#define DSI_LPMCR_VLPSIZE4             ((uint32_t)0x00000010U)
-#define DSI_LPMCR_VLPSIZE5             ((uint32_t)0x00000020U)
-#define DSI_LPMCR_VLPSIZE6             ((uint32_t)0x00000040U)
-#define DSI_LPMCR_VLPSIZE7             ((uint32_t)0x00000080U)
+#define DSI_LPMCR_VLPSIZE              0x000000FFU               /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0             0x00000001U
+#define DSI_LPMCR_VLPSIZE1             0x00000002U
+#define DSI_LPMCR_VLPSIZE2             0x00000004U
+#define DSI_LPMCR_VLPSIZE3             0x00000008U
+#define DSI_LPMCR_VLPSIZE4             0x00000010U
+#define DSI_LPMCR_VLPSIZE5             0x00000020U
+#define DSI_LPMCR_VLPSIZE6             0x00000040U
+#define DSI_LPMCR_VLPSIZE7             0x00000080U
 
-#define DSI_LPMCR_LPSIZE               ((uint32_t)0x00FF0000U)               /*!< Largest Packet Size */
-#define DSI_LPMCR_LPSIZE0              ((uint32_t)0x00010000U)
-#define DSI_LPMCR_LPSIZE1              ((uint32_t)0x00020000U)
-#define DSI_LPMCR_LPSIZE2              ((uint32_t)0x00040000U)
-#define DSI_LPMCR_LPSIZE3              ((uint32_t)0x00080000U)
-#define DSI_LPMCR_LPSIZE4              ((uint32_t)0x00100000U)
-#define DSI_LPMCR_LPSIZE5              ((uint32_t)0x00200000U)
-#define DSI_LPMCR_LPSIZE6              ((uint32_t)0x00400000U)
-#define DSI_LPMCR_LPSIZE7              ((uint32_t)0x00800000U)
+#define DSI_LPMCR_LPSIZE               0x00FF0000U               /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0              0x00010000U
+#define DSI_LPMCR_LPSIZE1              0x00020000U
+#define DSI_LPMCR_LPSIZE2              0x00040000U
+#define DSI_LPMCR_LPSIZE3              0x00080000U
+#define DSI_LPMCR_LPSIZE4              0x00100000U
+#define DSI_LPMCR_LPSIZE5              0x00200000U
+#define DSI_LPMCR_LPSIZE6              0x00400000U
+#define DSI_LPMCR_LPSIZE7              0x00800000U
 
 /*******************  Bit definition for DSI_PCR register  ****************/
-#define DSI_PCR_ETTXE                  ((uint32_t)0x00000001U)               /*!< EoTp Transmission Enable */
-#define DSI_PCR_ETRXE                  ((uint32_t)0x00000002U)               /*!< EoTp Reception Enable */
-#define DSI_PCR_BTAE                   ((uint32_t)0x00000004U)               /*!< Bus Turn Around Enable */
-#define DSI_PCR_ECCRXE                 ((uint32_t)0x00000008U)               /*!< ECC Reception Enable */
-#define DSI_PCR_CRCRXE                 ((uint32_t)0x00000010U)               /*!< CRC Reception Enable */
+#define DSI_PCR_ETTXE                  0x00000001U               /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE                  0x00000002U               /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE                   0x00000004U               /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE                 0x00000008U               /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE                 0x00000010U               /*!< CRC Reception Enable */
 
 /*******************  Bit definition for DSI_GVCIDR register  *************/
-#define DSI_GVCIDR_VCID                ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
-#define DSI_GVCIDR_VCID0               ((uint32_t)0x00000001U)
-#define DSI_GVCIDR_VCID1               ((uint32_t)0x00000002U)
+#define DSI_GVCIDR_VCID                0x00000003U               /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0               0x00000001U
+#define DSI_GVCIDR_VCID1               0x00000002U
 
 /*******************  Bit definition for DSI_MCR register  ****************/
-#define DSI_MCR_CMDM                   ((uint32_t)0x00000001U)               /*!< Command Mode */
+#define DSI_MCR_CMDM                   0x00000001U               /*!< Command Mode */
 
 /*******************  Bit definition for DSI_VMCR register  ***************/
-#define DSI_VMCR_VMT                   ((uint32_t)0x00000003U)               /*!< Video Mode Type */
-#define DSI_VMCR_VMT0                  ((uint32_t)0x00000001U)
-#define DSI_VMCR_VMT1                  ((uint32_t)0x00000002U)
+#define DSI_VMCR_VMT                   0x00000003U               /*!< Video Mode Type */
+#define DSI_VMCR_VMT0                  0x00000001U
+#define DSI_VMCR_VMT1                  0x00000002U
 
-#define DSI_VMCR_LPVSAE                ((uint32_t)0x00000100U)               /*!< Low-Power Vertical Sync Active Enable */
-#define DSI_VMCR_LPVBPE                ((uint32_t)0x00000200U)               /*!< Low-power Vertical Back-Porch Enable */
-#define DSI_VMCR_LPVFPE                ((uint32_t)0x00000400U)               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCR_LPVAE                 ((uint32_t)0x00000800U)               /*!< Low-Power Vertical Active Enable */
-#define DSI_VMCR_LPHBPE                ((uint32_t)0x00001000U)               /*!< Low-Power Horizontal Back-Porch Enable */
-#define DSI_VMCR_LPHFPE                ((uint32_t)0x00002000U)               /*!< Low-Power Horizontal Front-Porch Enable */
-#define DSI_VMCR_FBTAAE                ((uint32_t)0x00004000U)               /*!< Frame Bus-Turn-Around Acknowledge Enable */
-#define DSI_VMCR_LPCE                  ((uint32_t)0x00008000U)               /*!< Low-Power Command Enable */
-#define DSI_VMCR_PGE                   ((uint32_t)0x00010000U)               /*!< Pattern Generator Enable */
-#define DSI_VMCR_PGM                   ((uint32_t)0x00100000U)               /*!< Pattern Generator Mode */
-#define DSI_VMCR_PGO                   ((uint32_t)0x01000000U)               /*!< Pattern Generator Orientation */
+#define DSI_VMCR_LPVSAE                0x00000100U               /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE                0x00000200U               /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE                0x00000400U               /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE                 0x00000800U               /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE                0x00001000U               /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE                0x00002000U               /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE                0x00004000U               /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE                  0x00008000U               /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE                   0x00010000U               /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM                   0x00100000U               /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO                   0x01000000U               /*!< Pattern Generator Orientation */
 
 /*******************  Bit definition for DSI_VPCR register  ***************/
-#define DSI_VPCR_VPSIZE                ((uint32_t)0x00003FFFU)               /*!< Video Packet Size */
-#define DSI_VPCR_VPSIZE0               ((uint32_t)0x00000001U)
-#define DSI_VPCR_VPSIZE1               ((uint32_t)0x00000002U)
-#define DSI_VPCR_VPSIZE2               ((uint32_t)0x00000004U)
-#define DSI_VPCR_VPSIZE3               ((uint32_t)0x00000008U)
-#define DSI_VPCR_VPSIZE4               ((uint32_t)0x00000010U)
-#define DSI_VPCR_VPSIZE5               ((uint32_t)0x00000020U)
-#define DSI_VPCR_VPSIZE6               ((uint32_t)0x00000040U)
-#define DSI_VPCR_VPSIZE7               ((uint32_t)0x00000080U)
-#define DSI_VPCR_VPSIZE8               ((uint32_t)0x00000100U)
-#define DSI_VPCR_VPSIZE9               ((uint32_t)0x00000200U)
-#define DSI_VPCR_VPSIZE10              ((uint32_t)0x00000400U)
-#define DSI_VPCR_VPSIZE11              ((uint32_t)0x00000800U)
-#define DSI_VPCR_VPSIZE12              ((uint32_t)0x00001000U)
-#define DSI_VPCR_VPSIZE13              ((uint32_t)0x00002000U)
+#define DSI_VPCR_VPSIZE                0x00003FFFU               /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0               0x00000001U
+#define DSI_VPCR_VPSIZE1               0x00000002U
+#define DSI_VPCR_VPSIZE2               0x00000004U
+#define DSI_VPCR_VPSIZE3               0x00000008U
+#define DSI_VPCR_VPSIZE4               0x00000010U
+#define DSI_VPCR_VPSIZE5               0x00000020U
+#define DSI_VPCR_VPSIZE6               0x00000040U
+#define DSI_VPCR_VPSIZE7               0x00000080U
+#define DSI_VPCR_VPSIZE8               0x00000100U
+#define DSI_VPCR_VPSIZE9               0x00000200U
+#define DSI_VPCR_VPSIZE10              0x00000400U
+#define DSI_VPCR_VPSIZE11              0x00000800U
+#define DSI_VPCR_VPSIZE12              0x00001000U
+#define DSI_VPCR_VPSIZE13              0x00002000U
 
 /*******************  Bit definition for DSI_VCCR register  ***************/
-#define DSI_VCCR_NUMC                  ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
-#define DSI_VCCR_NUMC0                 ((uint32_t)0x00000001U)
-#define DSI_VCCR_NUMC1                 ((uint32_t)0x00000002U)
-#define DSI_VCCR_NUMC2                 ((uint32_t)0x00000004U)
-#define DSI_VCCR_NUMC3                 ((uint32_t)0x00000008U)
-#define DSI_VCCR_NUMC4                 ((uint32_t)0x00000010U)
-#define DSI_VCCR_NUMC5                 ((uint32_t)0x00000020U)
-#define DSI_VCCR_NUMC6                 ((uint32_t)0x00000040U)
-#define DSI_VCCR_NUMC7                 ((uint32_t)0x00000080U)
-#define DSI_VCCR_NUMC8                 ((uint32_t)0x00000100U)
-#define DSI_VCCR_NUMC9                 ((uint32_t)0x00000200U)
-#define DSI_VCCR_NUMC10                ((uint32_t)0x00000400U)
-#define DSI_VCCR_NUMC11                ((uint32_t)0x00000800U)
-#define DSI_VCCR_NUMC12                ((uint32_t)0x00001000U)
+#define DSI_VCCR_NUMC                  0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0                 0x00000001U
+#define DSI_VCCR_NUMC1                 0x00000002U
+#define DSI_VCCR_NUMC2                 0x00000004U
+#define DSI_VCCR_NUMC3                 0x00000008U
+#define DSI_VCCR_NUMC4                 0x00000010U
+#define DSI_VCCR_NUMC5                 0x00000020U
+#define DSI_VCCR_NUMC6                 0x00000040U
+#define DSI_VCCR_NUMC7                 0x00000080U
+#define DSI_VCCR_NUMC8                 0x00000100U
+#define DSI_VCCR_NUMC9                 0x00000200U
+#define DSI_VCCR_NUMC10                0x00000400U
+#define DSI_VCCR_NUMC11                0x00000800U
+#define DSI_VCCR_NUMC12                0x00001000U
 
 /*******************  Bit definition for DSI_VNPCR register  **************/
-#define DSI_VNPCR_NPSIZE               ((uint32_t)0x00001FFFU)               /*!< Null Packet Size */
-#define DSI_VNPCR_NPSIZE0              ((uint32_t)0x00000001U)
-#define DSI_VNPCR_NPSIZE1              ((uint32_t)0x00000002U)
-#define DSI_VNPCR_NPSIZE2              ((uint32_t)0x00000004U)
-#define DSI_VNPCR_NPSIZE3              ((uint32_t)0x00000008U)
-#define DSI_VNPCR_NPSIZE4              ((uint32_t)0x00000010U)
-#define DSI_VNPCR_NPSIZE5              ((uint32_t)0x00000020U)
-#define DSI_VNPCR_NPSIZE6              ((uint32_t)0x00000040U)
-#define DSI_VNPCR_NPSIZE7              ((uint32_t)0x00000080U)
-#define DSI_VNPCR_NPSIZE8              ((uint32_t)0x00000100U)
-#define DSI_VNPCR_NPSIZE9              ((uint32_t)0x00000200U)
-#define DSI_VNPCR_NPSIZE10             ((uint32_t)0x00000400U)
-#define DSI_VNPCR_NPSIZE11             ((uint32_t)0x00000800U)
-#define DSI_VNPCR_NPSIZE12             ((uint32_t)0x00001000U)
+#define DSI_VNPCR_NPSIZE               0x00001FFFU               /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0              0x00000001U
+#define DSI_VNPCR_NPSIZE1              0x00000002U
+#define DSI_VNPCR_NPSIZE2              0x00000004U
+#define DSI_VNPCR_NPSIZE3              0x00000008U
+#define DSI_VNPCR_NPSIZE4              0x00000010U
+#define DSI_VNPCR_NPSIZE5              0x00000020U
+#define DSI_VNPCR_NPSIZE6              0x00000040U
+#define DSI_VNPCR_NPSIZE7              0x00000080U
+#define DSI_VNPCR_NPSIZE8              0x00000100U
+#define DSI_VNPCR_NPSIZE9              0x00000200U
+#define DSI_VNPCR_NPSIZE10             0x00000400U
+#define DSI_VNPCR_NPSIZE11             0x00000800U
+#define DSI_VNPCR_NPSIZE12             0x00001000U
 
 /*******************  Bit definition for DSI_VHSACR register  *************/
-#define DSI_VHSACR_HSA                 ((uint32_t)0x00000FFFU)               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACR_HSA0                ((uint32_t)0x00000001U)
-#define DSI_VHSACR_HSA1                ((uint32_t)0x00000002U)
-#define DSI_VHSACR_HSA2                ((uint32_t)0x00000004U)
-#define DSI_VHSACR_HSA3                ((uint32_t)0x00000008U)
-#define DSI_VHSACR_HSA4                ((uint32_t)0x00000010U)
-#define DSI_VHSACR_HSA5                ((uint32_t)0x00000020U)
-#define DSI_VHSACR_HSA6                ((uint32_t)0x00000040U)
-#define DSI_VHSACR_HSA7                ((uint32_t)0x00000080U)
-#define DSI_VHSACR_HSA8                ((uint32_t)0x00000100U)
-#define DSI_VHSACR_HSA9                ((uint32_t)0x00000200U)
-#define DSI_VHSACR_HSA10               ((uint32_t)0x00000400U)
-#define DSI_VHSACR_HSA11               ((uint32_t)0x00000800U)
+#define DSI_VHSACR_HSA                 0x00000FFFU               /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0                0x00000001U
+#define DSI_VHSACR_HSA1                0x00000002U
+#define DSI_VHSACR_HSA2                0x00000004U
+#define DSI_VHSACR_HSA3                0x00000008U
+#define DSI_VHSACR_HSA4                0x00000010U
+#define DSI_VHSACR_HSA5                0x00000020U
+#define DSI_VHSACR_HSA6                0x00000040U
+#define DSI_VHSACR_HSA7                0x00000080U
+#define DSI_VHSACR_HSA8                0x00000100U
+#define DSI_VHSACR_HSA9                0x00000200U
+#define DSI_VHSACR_HSA10               0x00000400U
+#define DSI_VHSACR_HSA11               0x00000800U
 
 /*******************  Bit definition for DSI_VHBPCR register  *************/
-#define DSI_VHBPCR_HBP                 ((uint32_t)0x00000FFFU)               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCR_HBP0                ((uint32_t)0x00000001U)
-#define DSI_VHBPCR_HBP1                ((uint32_t)0x00000002U)
-#define DSI_VHBPCR_HBP2                ((uint32_t)0x00000004U)
-#define DSI_VHBPCR_HBP3                ((uint32_t)0x00000008U)
-#define DSI_VHBPCR_HBP4                ((uint32_t)0x00000010U)
-#define DSI_VHBPCR_HBP5                ((uint32_t)0x00000020U)
-#define DSI_VHBPCR_HBP6                ((uint32_t)0x00000040U)
-#define DSI_VHBPCR_HBP7                ((uint32_t)0x00000080U)
-#define DSI_VHBPCR_HBP8                ((uint32_t)0x00000100U)
-#define DSI_VHBPCR_HBP9                ((uint32_t)0x00000200U)
-#define DSI_VHBPCR_HBP10               ((uint32_t)0x00000400U)
-#define DSI_VHBPCR_HBP11               ((uint32_t)0x00000800U)
+#define DSI_VHBPCR_HBP                 0x00000FFFU               /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0                0x00000001U
+#define DSI_VHBPCR_HBP1                0x00000002U
+#define DSI_VHBPCR_HBP2                0x00000004U
+#define DSI_VHBPCR_HBP3                0x00000008U
+#define DSI_VHBPCR_HBP4                0x00000010U
+#define DSI_VHBPCR_HBP5                0x00000020U
+#define DSI_VHBPCR_HBP6                0x00000040U
+#define DSI_VHBPCR_HBP7                0x00000080U
+#define DSI_VHBPCR_HBP8                0x00000100U
+#define DSI_VHBPCR_HBP9                0x00000200U
+#define DSI_VHBPCR_HBP10               0x00000400U
+#define DSI_VHBPCR_HBP11               0x00000800U
 
 /*******************  Bit definition for DSI_VLCR register  ***************/
-#define DSI_VLCR_HLINE                 ((uint32_t)0x00007FFFU)               /*!< Horizontal Line duration */
-#define DSI_VLCR_HLINE0                ((uint32_t)0x00000001U)
-#define DSI_VLCR_HLINE1                ((uint32_t)0x00000002U)
-#define DSI_VLCR_HLINE2                ((uint32_t)0x00000004U)
-#define DSI_VLCR_HLINE3                ((uint32_t)0x00000008U)
-#define DSI_VLCR_HLINE4                ((uint32_t)0x00000010U)
-#define DSI_VLCR_HLINE5                ((uint32_t)0x00000020U)
-#define DSI_VLCR_HLINE6                ((uint32_t)0x00000040U)
-#define DSI_VLCR_HLINE7                ((uint32_t)0x00000080U)
-#define DSI_VLCR_HLINE8                ((uint32_t)0x00000100U)
-#define DSI_VLCR_HLINE9                ((uint32_t)0x00000200U)
-#define DSI_VLCR_HLINE10               ((uint32_t)0x00000400U)
-#define DSI_VLCR_HLINE11               ((uint32_t)0x00000800U)
-#define DSI_VLCR_HLINE12               ((uint32_t)0x00001000U)
-#define DSI_VLCR_HLINE13               ((uint32_t)0x00002000U)
-#define DSI_VLCR_HLINE14               ((uint32_t)0x00004000U)
+#define DSI_VLCR_HLINE                 0x00007FFFU               /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0                0x00000001U
+#define DSI_VLCR_HLINE1                0x00000002U
+#define DSI_VLCR_HLINE2                0x00000004U
+#define DSI_VLCR_HLINE3                0x00000008U
+#define DSI_VLCR_HLINE4                0x00000010U
+#define DSI_VLCR_HLINE5                0x00000020U
+#define DSI_VLCR_HLINE6                0x00000040U
+#define DSI_VLCR_HLINE7                0x00000080U
+#define DSI_VLCR_HLINE8                0x00000100U
+#define DSI_VLCR_HLINE9                0x00000200U
+#define DSI_VLCR_HLINE10               0x00000400U
+#define DSI_VLCR_HLINE11               0x00000800U
+#define DSI_VLCR_HLINE12               0x00001000U
+#define DSI_VLCR_HLINE13               0x00002000U
+#define DSI_VLCR_HLINE14               0x00004000U
 
 /*******************  Bit definition for DSI_VVSACR register  *************/
-#define DSI_VVSACR_VSA                 ((uint32_t)0x000003FFU)               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACR_VSA0                ((uint32_t)0x00000001U)
-#define DSI_VVSACR_VSA1                ((uint32_t)0x00000002U)
-#define DSI_VVSACR_VSA2                ((uint32_t)0x00000004U)
-#define DSI_VVSACR_VSA3                ((uint32_t)0x00000008U)
-#define DSI_VVSACR_VSA4                ((uint32_t)0x00000010U)
-#define DSI_VVSACR_VSA5                ((uint32_t)0x00000020U)
-#define DSI_VVSACR_VSA6                ((uint32_t)0x00000040U)
-#define DSI_VVSACR_VSA7                ((uint32_t)0x00000080U)
-#define DSI_VVSACR_VSA8                ((uint32_t)0x00000100U)
-#define DSI_VVSACR_VSA9                ((uint32_t)0x00000200U)
+#define DSI_VVSACR_VSA                 0x000003FFU               /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0                0x00000001U
+#define DSI_VVSACR_VSA1                0x00000002U
+#define DSI_VVSACR_VSA2                0x00000004U
+#define DSI_VVSACR_VSA3                0x00000008U
+#define DSI_VVSACR_VSA4                0x00000010U
+#define DSI_VVSACR_VSA5                0x00000020U
+#define DSI_VVSACR_VSA6                0x00000040U
+#define DSI_VVSACR_VSA7                0x00000080U
+#define DSI_VVSACR_VSA8                0x00000100U
+#define DSI_VVSACR_VSA9                0x00000200U
 
 /*******************  Bit definition for DSI_VVBPCR register  *************/
-#define DSI_VVBPCR_VBP                 ((uint32_t)0x000003FFU)               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCR_VBP0                ((uint32_t)0x00000001U)
-#define DSI_VVBPCR_VBP1                ((uint32_t)0x00000002U)
-#define DSI_VVBPCR_VBP2                ((uint32_t)0x00000004U)
-#define DSI_VVBPCR_VBP3                ((uint32_t)0x00000008U)
-#define DSI_VVBPCR_VBP4                ((uint32_t)0x00000010U)
-#define DSI_VVBPCR_VBP5                ((uint32_t)0x00000020U)
-#define DSI_VVBPCR_VBP6                ((uint32_t)0x00000040U)
-#define DSI_VVBPCR_VBP7                ((uint32_t)0x00000080U)
-#define DSI_VVBPCR_VBP8                ((uint32_t)0x00000100U)
-#define DSI_VVBPCR_VBP9                ((uint32_t)0x00000200U)
+#define DSI_VVBPCR_VBP                 0x000003FFU               /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0                0x00000001U
+#define DSI_VVBPCR_VBP1                0x00000002U
+#define DSI_VVBPCR_VBP2                0x00000004U
+#define DSI_VVBPCR_VBP3                0x00000008U
+#define DSI_VVBPCR_VBP4                0x00000010U
+#define DSI_VVBPCR_VBP5                0x00000020U
+#define DSI_VVBPCR_VBP6                0x00000040U
+#define DSI_VVBPCR_VBP7                0x00000080U
+#define DSI_VVBPCR_VBP8                0x00000100U
+#define DSI_VVBPCR_VBP9                0x00000200U
 
 /*******************  Bit definition for DSI_VVFPCR register  *************/
-#define DSI_VVFPCR_VFP                 ((uint32_t)0x000003FFU)               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCR_VFP0                ((uint32_t)0x00000001U)
-#define DSI_VVFPCR_VFP1                ((uint32_t)0x00000002U)
-#define DSI_VVFPCR_VFP2                ((uint32_t)0x00000004U)
-#define DSI_VVFPCR_VFP3                ((uint32_t)0x00000008U)
-#define DSI_VVFPCR_VFP4                ((uint32_t)0x00000010U)
-#define DSI_VVFPCR_VFP5                ((uint32_t)0x00000020U)
-#define DSI_VVFPCR_VFP6                ((uint32_t)0x00000040U)
-#define DSI_VVFPCR_VFP7                ((uint32_t)0x00000080U)
-#define DSI_VVFPCR_VFP8                ((uint32_t)0x00000100U)
-#define DSI_VVFPCR_VFP9                ((uint32_t)0x00000200U)
+#define DSI_VVFPCR_VFP                 0x000003FFU               /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0                0x00000001U
+#define DSI_VVFPCR_VFP1                0x00000002U
+#define DSI_VVFPCR_VFP2                0x00000004U
+#define DSI_VVFPCR_VFP3                0x00000008U
+#define DSI_VVFPCR_VFP4                0x00000010U
+#define DSI_VVFPCR_VFP5                0x00000020U
+#define DSI_VVFPCR_VFP6                0x00000040U
+#define DSI_VVFPCR_VFP7                0x00000080U
+#define DSI_VVFPCR_VFP8                0x00000100U
+#define DSI_VVFPCR_VFP9                0x00000200U
 
 /*******************  Bit definition for DSI_VVACR register  **************/
-#define DSI_VVACR_VA                   ((uint32_t)0x00003FFFU)               /*!< Vertical Active duration */
-#define DSI_VVACR_VA0                  ((uint32_t)0x00000001U)
-#define DSI_VVACR_VA1                  ((uint32_t)0x00000002U)
-#define DSI_VVACR_VA2                  ((uint32_t)0x00000004U)
-#define DSI_VVACR_VA3                  ((uint32_t)0x00000008U)
-#define DSI_VVACR_VA4                  ((uint32_t)0x00000010U)
-#define DSI_VVACR_VA5                  ((uint32_t)0x00000020U)
-#define DSI_VVACR_VA6                  ((uint32_t)0x00000040U)
-#define DSI_VVACR_VA7                  ((uint32_t)0x00000080U)
-#define DSI_VVACR_VA8                  ((uint32_t)0x00000100U)
-#define DSI_VVACR_VA9                  ((uint32_t)0x00000200U)
-#define DSI_VVACR_VA10                 ((uint32_t)0x00000400U)
-#define DSI_VVACR_VA11                 ((uint32_t)0x00000800U)
-#define DSI_VVACR_VA12                 ((uint32_t)0x00001000U)
-#define DSI_VVACR_VA13                 ((uint32_t)0x00002000U)
+#define DSI_VVACR_VA                   0x00003FFFU               /*!< Vertical Active duration */
+#define DSI_VVACR_VA0                  0x00000001U
+#define DSI_VVACR_VA1                  0x00000002U
+#define DSI_VVACR_VA2                  0x00000004U
+#define DSI_VVACR_VA3                  0x00000008U
+#define DSI_VVACR_VA4                  0x00000010U
+#define DSI_VVACR_VA5                  0x00000020U
+#define DSI_VVACR_VA6                  0x00000040U
+#define DSI_VVACR_VA7                  0x00000080U
+#define DSI_VVACR_VA8                  0x00000100U
+#define DSI_VVACR_VA9                  0x00000200U
+#define DSI_VVACR_VA10                 0x00000400U
+#define DSI_VVACR_VA11                 0x00000800U
+#define DSI_VVACR_VA12                 0x00001000U
+#define DSI_VVACR_VA13                 0x00002000U
 
 /*******************  Bit definition for DSI_LCCR register  ***************/
-#define DSI_LCCR_CMDSIZE               ((uint32_t)0x0000FFFFU)               /*!< Command Size */
-#define DSI_LCCR_CMDSIZE0              ((uint32_t)0x00000001U)
-#define DSI_LCCR_CMDSIZE1              ((uint32_t)0x00000002U)
-#define DSI_LCCR_CMDSIZE2              ((uint32_t)0x00000004U)
-#define DSI_LCCR_CMDSIZE3              ((uint32_t)0x00000008U)
-#define DSI_LCCR_CMDSIZE4              ((uint32_t)0x00000010U)
-#define DSI_LCCR_CMDSIZE5              ((uint32_t)0x00000020U)
-#define DSI_LCCR_CMDSIZE6              ((uint32_t)0x00000040U)
-#define DSI_LCCR_CMDSIZE7              ((uint32_t)0x00000080U)
-#define DSI_LCCR_CMDSIZE8              ((uint32_t)0x00000100U)
-#define DSI_LCCR_CMDSIZE9              ((uint32_t)0x00000200U)
-#define DSI_LCCR_CMDSIZE10             ((uint32_t)0x00000400U)
-#define DSI_LCCR_CMDSIZE11             ((uint32_t)0x00000800U)
-#define DSI_LCCR_CMDSIZE12             ((uint32_t)0x00001000U)
-#define DSI_LCCR_CMDSIZE13             ((uint32_t)0x00002000U)
-#define DSI_LCCR_CMDSIZE14             ((uint32_t)0x00004000U)
-#define DSI_LCCR_CMDSIZE15             ((uint32_t)0x00008000U)
+#define DSI_LCCR_CMDSIZE               0x0000FFFFU               /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0              0x00000001U
+#define DSI_LCCR_CMDSIZE1              0x00000002U
+#define DSI_LCCR_CMDSIZE2              0x00000004U
+#define DSI_LCCR_CMDSIZE3              0x00000008U
+#define DSI_LCCR_CMDSIZE4              0x00000010U
+#define DSI_LCCR_CMDSIZE5              0x00000020U
+#define DSI_LCCR_CMDSIZE6              0x00000040U
+#define DSI_LCCR_CMDSIZE7              0x00000080U
+#define DSI_LCCR_CMDSIZE8              0x00000100U
+#define DSI_LCCR_CMDSIZE9              0x00000200U
+#define DSI_LCCR_CMDSIZE10             0x00000400U
+#define DSI_LCCR_CMDSIZE11             0x00000800U
+#define DSI_LCCR_CMDSIZE12             0x00001000U
+#define DSI_LCCR_CMDSIZE13             0x00002000U
+#define DSI_LCCR_CMDSIZE14             0x00004000U
+#define DSI_LCCR_CMDSIZE15             0x00008000U
 
 /*******************  Bit definition for DSI_CMCR register  ***************/
-#define DSI_CMCR_TEARE                 ((uint32_t)0x00000001U)               /*!< Tearing Effect Acknowledge Request Enable */
-#define DSI_CMCR_ARE                   ((uint32_t)0x00000002U)               /*!< Acknowledge Request Enable */
-#define DSI_CMCR_GSW0TX                ((uint32_t)0x00000100U)               /*!< Generic Short Write Zero parameters Transmission */
-#define DSI_CMCR_GSW1TX                ((uint32_t)0x00000200U)               /*!< Generic Short Write One parameters Transmission */
-#define DSI_CMCR_GSW2TX                ((uint32_t)0x00000400U)               /*!< Generic Short Write Two parameters Transmission */
-#define DSI_CMCR_GSR0TX                ((uint32_t)0x00000800U)               /*!< Generic Short Read Zero parameters Transmission */
-#define DSI_CMCR_GSR1TX                ((uint32_t)0x00001000U)               /*!< Generic Short Read One parameters Transmission */
-#define DSI_CMCR_GSR2TX                ((uint32_t)0x00002000U)               /*!< Generic Short Read Two parameters Transmission */
-#define DSI_CMCR_GLWTX                 ((uint32_t)0x00004000U)               /*!< Generic Long Write Transmission */
-#define DSI_CMCR_DSW0TX                ((uint32_t)0x00010000U)               /*!< DCS Short Write Zero parameter Transmission */
-#define DSI_CMCR_DSW1TX                ((uint32_t)0x00020000U)               /*!< DCS Short Read One parameter Transmission */
-#define DSI_CMCR_DSR0TX                ((uint32_t)0x00040000U)               /*!< DCS Short Read Zero parameter Transmission */
-#define DSI_CMCR_DLWTX                 ((uint32_t)0x00080000U)               /*!< DCS Long Write Transmission */
-#define DSI_CMCR_MRDPS                 ((uint32_t)0x01000000U)               /*!< Maximum Read Packet Size */
+#define DSI_CMCR_TEARE                 0x00000001U               /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE                   0x00000002U               /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX                0x00000100U               /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX                0x00000200U               /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX                0x00000400U               /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX                0x00000800U               /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX                0x00001000U               /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX                0x00002000U               /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX                 0x00004000U               /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX                0x00010000U               /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX                0x00020000U               /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX                0x00040000U               /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX                 0x00080000U               /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS                 0x01000000U               /*!< Maximum Read Packet Size */
 
 /*******************  Bit definition for DSI_GHCR register  ***************/
-#define DSI_GHCR_DT                    ((uint32_t)0x0000003FU)               /*!< Type */
-#define DSI_GHCR_DT0                   ((uint32_t)0x00000001U)
-#define DSI_GHCR_DT1                   ((uint32_t)0x00000002U)
-#define DSI_GHCR_DT2                   ((uint32_t)0x00000004U)
-#define DSI_GHCR_DT3                   ((uint32_t)0x00000008U)
-#define DSI_GHCR_DT4                   ((uint32_t)0x00000010U)
-#define DSI_GHCR_DT5                   ((uint32_t)0x00000020U)
+#define DSI_GHCR_DT                    0x0000003FU               /*!< Type */
+#define DSI_GHCR_DT0                   0x00000001U
+#define DSI_GHCR_DT1                   0x00000002U
+#define DSI_GHCR_DT2                   0x00000004U
+#define DSI_GHCR_DT3                   0x00000008U
+#define DSI_GHCR_DT4                   0x00000010U
+#define DSI_GHCR_DT5                   0x00000020U
 
-#define DSI_GHCR_VCID                  ((uint32_t)0x000000C0U)               /*!< Channel */
-#define DSI_GHCR_VCID0                 ((uint32_t)0x00000040U)
-#define DSI_GHCR_VCID1                 ((uint32_t)0x00000080U)
+#define DSI_GHCR_VCID                  0x000000C0U               /*!< Channel */
+#define DSI_GHCR_VCID0                 0x00000040U
+#define DSI_GHCR_VCID1                 0x00000080U
 
-#define DSI_GHCR_WCLSB                 ((uint32_t)0x0000FF00U)               /*!< WordCount LSB */
-#define DSI_GHCR_WCLSB0                ((uint32_t)0x00000100U)
-#define DSI_GHCR_WCLSB1                ((uint32_t)0x00000200U)
-#define DSI_GHCR_WCLSB2                ((uint32_t)0x00000400U)
-#define DSI_GHCR_WCLSB3                ((uint32_t)0x00000800U)
-#define DSI_GHCR_WCLSB4                ((uint32_t)0x00001000U)
-#define DSI_GHCR_WCLSB5                ((uint32_t)0x00002000U)
-#define DSI_GHCR_WCLSB6                ((uint32_t)0x00004000U)
-#define DSI_GHCR_WCLSB7                ((uint32_t)0x00008000U)
+#define DSI_GHCR_WCLSB                 0x0000FF00U               /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0                0x00000100U
+#define DSI_GHCR_WCLSB1                0x00000200U
+#define DSI_GHCR_WCLSB2                0x00000400U
+#define DSI_GHCR_WCLSB3                0x00000800U
+#define DSI_GHCR_WCLSB4                0x00001000U
+#define DSI_GHCR_WCLSB5                0x00002000U
+#define DSI_GHCR_WCLSB6                0x00004000U
+#define DSI_GHCR_WCLSB7                0x00008000U
 
-#define DSI_GHCR_WCMSB                 ((uint32_t)0x00FF0000U)               /*!< WordCount MSB */
-#define DSI_GHCR_WCMSB0                ((uint32_t)0x00010000U)
-#define DSI_GHCR_WCMSB1                ((uint32_t)0x00020000U)
-#define DSI_GHCR_WCMSB2                ((uint32_t)0x00040000U)
-#define DSI_GHCR_WCMSB3                ((uint32_t)0x00080000U)
-#define DSI_GHCR_WCMSB4                ((uint32_t)0x00100000U)
-#define DSI_GHCR_WCMSB5                ((uint32_t)0x00200000U)
-#define DSI_GHCR_WCMSB6                ((uint32_t)0x00400000U)
-#define DSI_GHCR_WCMSB7                ((uint32_t)0x00800000U)
+#define DSI_GHCR_WCMSB                 0x00FF0000U               /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0                0x00010000U
+#define DSI_GHCR_WCMSB1                0x00020000U
+#define DSI_GHCR_WCMSB2                0x00040000U
+#define DSI_GHCR_WCMSB3                0x00080000U
+#define DSI_GHCR_WCMSB4                0x00100000U
+#define DSI_GHCR_WCMSB5                0x00200000U
+#define DSI_GHCR_WCMSB6                0x00400000U
+#define DSI_GHCR_WCMSB7                0x00800000U
 
 /*******************  Bit definition for DSI_GPDR register  ***************/
-#define DSI_GPDR_DATA1                 ((uint32_t)0x000000FFU)               /*!< Payload Byte 1 */
-#define DSI_GPDR_DATA1_0               ((uint32_t)0x00000001U)
-#define DSI_GPDR_DATA1_1               ((uint32_t)0x00000002U)
-#define DSI_GPDR_DATA1_2               ((uint32_t)0x00000004U)
-#define DSI_GPDR_DATA1_3               ((uint32_t)0x00000008U)
-#define DSI_GPDR_DATA1_4               ((uint32_t)0x00000010U)
-#define DSI_GPDR_DATA1_5               ((uint32_t)0x00000020U)
-#define DSI_GPDR_DATA1_6               ((uint32_t)0x00000040U)
-#define DSI_GPDR_DATA1_7               ((uint32_t)0x00000080U)
+#define DSI_GPDR_DATA1                 0x000000FFU               /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0               0x00000001U
+#define DSI_GPDR_DATA1_1               0x00000002U
+#define DSI_GPDR_DATA1_2               0x00000004U
+#define DSI_GPDR_DATA1_3               0x00000008U
+#define DSI_GPDR_DATA1_4               0x00000010U
+#define DSI_GPDR_DATA1_5               0x00000020U
+#define DSI_GPDR_DATA1_6               0x00000040U
+#define DSI_GPDR_DATA1_7               0x00000080U
 
-#define DSI_GPDR_DATA2                 ((uint32_t)0x0000FF00U)               /*!< Payload Byte 2 */
-#define DSI_GPDR_DATA2_0               ((uint32_t)0x00000100U)
-#define DSI_GPDR_DATA2_1               ((uint32_t)0x00000200U)
-#define DSI_GPDR_DATA2_2               ((uint32_t)0x00000400U)
-#define DSI_GPDR_DATA2_3               ((uint32_t)0x00000800U)
-#define DSI_GPDR_DATA2_4               ((uint32_t)0x00001000U)
-#define DSI_GPDR_DATA2_5               ((uint32_t)0x00002000U)
-#define DSI_GPDR_DATA2_6               ((uint32_t)0x00004000U)
-#define DSI_GPDR_DATA2_7               ((uint32_t)0x00008000U)
+#define DSI_GPDR_DATA2                 0x0000FF00U               /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0               0x00000100U
+#define DSI_GPDR_DATA2_1               0x00000200U
+#define DSI_GPDR_DATA2_2               0x00000400U
+#define DSI_GPDR_DATA2_3               0x00000800U
+#define DSI_GPDR_DATA2_4               0x00001000U
+#define DSI_GPDR_DATA2_5               0x00002000U
+#define DSI_GPDR_DATA2_6               0x00004000U
+#define DSI_GPDR_DATA2_7               0x00008000U
 
-#define DSI_GPDR_DATA3                 ((uint32_t)0x00FF0000U)               /*!< Payload Byte 3 */
-#define DSI_GPDR_DATA3_0               ((uint32_t)0x00010000U)
-#define DSI_GPDR_DATA3_1               ((uint32_t)0x00020000U)
-#define DSI_GPDR_DATA3_2               ((uint32_t)0x00040000U)
-#define DSI_GPDR_DATA3_3               ((uint32_t)0x00080000U)
-#define DSI_GPDR_DATA3_4               ((uint32_t)0x00100000U)
-#define DSI_GPDR_DATA3_5               ((uint32_t)0x00200000U)
-#define DSI_GPDR_DATA3_6               ((uint32_t)0x00400000U)
-#define DSI_GPDR_DATA3_7               ((uint32_t)0x00800000U)
+#define DSI_GPDR_DATA3                 0x00FF0000U               /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0               0x00010000U
+#define DSI_GPDR_DATA3_1               0x00020000U
+#define DSI_GPDR_DATA3_2               0x00040000U
+#define DSI_GPDR_DATA3_3               0x00080000U
+#define DSI_GPDR_DATA3_4               0x00100000U
+#define DSI_GPDR_DATA3_5               0x00200000U
+#define DSI_GPDR_DATA3_6               0x00400000U
+#define DSI_GPDR_DATA3_7               0x00800000U
 
-#define DSI_GPDR_DATA4                 ((uint32_t)0xFF000000U)               /*!< Payload Byte 4 */
-#define DSI_GPDR_DATA4_0               ((uint32_t)0x01000000U)
-#define DSI_GPDR_DATA4_1               ((uint32_t)0x02000000U)
-#define DSI_GPDR_DATA4_2               ((uint32_t)0x04000000U)
-#define DSI_GPDR_DATA4_3               ((uint32_t)0x08000000U)
-#define DSI_GPDR_DATA4_4               ((uint32_t)0x10000000U)
-#define DSI_GPDR_DATA4_5               ((uint32_t)0x20000000U)
-#define DSI_GPDR_DATA4_6               ((uint32_t)0x40000000U)
-#define DSI_GPDR_DATA4_7               ((uint32_t)0x80000000U)
+#define DSI_GPDR_DATA4                 0xFF000000U               /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0               0x01000000U
+#define DSI_GPDR_DATA4_1               0x02000000U
+#define DSI_GPDR_DATA4_2               0x04000000U
+#define DSI_GPDR_DATA4_3               0x08000000U
+#define DSI_GPDR_DATA4_4               0x10000000U
+#define DSI_GPDR_DATA4_5               0x20000000U
+#define DSI_GPDR_DATA4_6               0x40000000U
+#define DSI_GPDR_DATA4_7               0x80000000U
 
 /*******************  Bit definition for DSI_GPSR register  ***************/
-#define DSI_GPSR_CMDFE                 ((uint32_t)0x00000001U)               /*!< Command FIFO Empty */
-#define DSI_GPSR_CMDFF                 ((uint32_t)0x00000002U)               /*!< Command FIFO Full */
-#define DSI_GPSR_PWRFE                 ((uint32_t)0x00000004U)               /*!< Payload Write FIFO Empty */
-#define DSI_GPSR_PWRFF                 ((uint32_t)0x00000008U)               /*!< Payload Write FIFO Full */
-#define DSI_GPSR_PRDFE                 ((uint32_t)0x00000010U)               /*!< Payload Read FIFO Empty */
-#define DSI_GPSR_PRDFF                 ((uint32_t)0x00000020U)               /*!< Payload Read FIFO Full */
-#define DSI_GPSR_RCB                   ((uint32_t)0x00000040U)               /*!< Read Command Busy */
+#define DSI_GPSR_CMDFE                 0x00000001U               /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF                 0x00000002U               /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE                 0x00000004U               /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF                 0x00000008U               /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE                 0x00000010U               /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF                 0x00000020U               /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB                   0x00000040U               /*!< Read Command Busy */
 
 /*******************  Bit definition for DSI_TCCR0 register  **************/
-#define DSI_TCCR0_LPRX_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-power Reception Timeout Counter */
-#define DSI_TCCR0_LPRX_TOCNT0          ((uint32_t)0x00000001U)
-#define DSI_TCCR0_LPRX_TOCNT1          ((uint32_t)0x00000002U)
-#define DSI_TCCR0_LPRX_TOCNT2          ((uint32_t)0x00000004U)
-#define DSI_TCCR0_LPRX_TOCNT3          ((uint32_t)0x00000008U)
-#define DSI_TCCR0_LPRX_TOCNT4          ((uint32_t)0x00000010U)
-#define DSI_TCCR0_LPRX_TOCNT5          ((uint32_t)0x00000020U)
-#define DSI_TCCR0_LPRX_TOCNT6          ((uint32_t)0x00000040U)
-#define DSI_TCCR0_LPRX_TOCNT7          ((uint32_t)0x00000080U)
-#define DSI_TCCR0_LPRX_TOCNT8          ((uint32_t)0x00000100U)
-#define DSI_TCCR0_LPRX_TOCNT9          ((uint32_t)0x00000200U)
-#define DSI_TCCR0_LPRX_TOCNT10         ((uint32_t)0x00000400U)
-#define DSI_TCCR0_LPRX_TOCNT11         ((uint32_t)0x00000800U)
-#define DSI_TCCR0_LPRX_TOCNT12         ((uint32_t)0x00001000U)
-#define DSI_TCCR0_LPRX_TOCNT13         ((uint32_t)0x00002000U)
-#define DSI_TCCR0_LPRX_TOCNT14         ((uint32_t)0x00004000U)
-#define DSI_TCCR0_LPRX_TOCNT15         ((uint32_t)0x00008000U)
+#define DSI_TCCR0_LPRX_TOCNT           0x0000FFFFU               /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0          0x00000001U
+#define DSI_TCCR0_LPRX_TOCNT1          0x00000002U
+#define DSI_TCCR0_LPRX_TOCNT2          0x00000004U
+#define DSI_TCCR0_LPRX_TOCNT3          0x00000008U
+#define DSI_TCCR0_LPRX_TOCNT4          0x00000010U
+#define DSI_TCCR0_LPRX_TOCNT5          0x00000020U
+#define DSI_TCCR0_LPRX_TOCNT6          0x00000040U
+#define DSI_TCCR0_LPRX_TOCNT7          0x00000080U
+#define DSI_TCCR0_LPRX_TOCNT8          0x00000100U
+#define DSI_TCCR0_LPRX_TOCNT9          0x00000200U
+#define DSI_TCCR0_LPRX_TOCNT10         0x00000400U
+#define DSI_TCCR0_LPRX_TOCNT11         0x00000800U
+#define DSI_TCCR0_LPRX_TOCNT12         0x00001000U
+#define DSI_TCCR0_LPRX_TOCNT13         0x00002000U
+#define DSI_TCCR0_LPRX_TOCNT14         0x00004000U
+#define DSI_TCCR0_LPRX_TOCNT15         0x00008000U
 
-#define DSI_TCCR0_HSTX_TOCNT           ((uint32_t)0xFFFF0000U)               /*!< High-Speed Transmission Timeout Counter */
-#define DSI_TCCR0_HSTX_TOCNT0          ((uint32_t)0x00010000U)
-#define DSI_TCCR0_HSTX_TOCNT1          ((uint32_t)0x00020000U)
-#define DSI_TCCR0_HSTX_TOCNT2          ((uint32_t)0x00040000U)
-#define DSI_TCCR0_HSTX_TOCNT3          ((uint32_t)0x00080000U)
-#define DSI_TCCR0_HSTX_TOCNT4          ((uint32_t)0x00100000U)
-#define DSI_TCCR0_HSTX_TOCNT5          ((uint32_t)0x00200000U)
-#define DSI_TCCR0_HSTX_TOCNT6          ((uint32_t)0x00400000U)
-#define DSI_TCCR0_HSTX_TOCNT7          ((uint32_t)0x00800000U)
-#define DSI_TCCR0_HSTX_TOCNT8          ((uint32_t)0x01000000U)
-#define DSI_TCCR0_HSTX_TOCNT9          ((uint32_t)0x02000000U)
-#define DSI_TCCR0_HSTX_TOCNT10         ((uint32_t)0x04000000U)
-#define DSI_TCCR0_HSTX_TOCNT11         ((uint32_t)0x08000000U)
-#define DSI_TCCR0_HSTX_TOCNT12         ((uint32_t)0x10000000U)
-#define DSI_TCCR0_HSTX_TOCNT13         ((uint32_t)0x20000000U)
-#define DSI_TCCR0_HSTX_TOCNT14         ((uint32_t)0x40000000U)
-#define DSI_TCCR0_HSTX_TOCNT15         ((uint32_t)0x80000000U)
+#define DSI_TCCR0_HSTX_TOCNT           0xFFFF0000U               /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0          0x00010000U
+#define DSI_TCCR0_HSTX_TOCNT1          0x00020000U
+#define DSI_TCCR0_HSTX_TOCNT2          0x00040000U
+#define DSI_TCCR0_HSTX_TOCNT3          0x00080000U
+#define DSI_TCCR0_HSTX_TOCNT4          0x00100000U
+#define DSI_TCCR0_HSTX_TOCNT5          0x00200000U
+#define DSI_TCCR0_HSTX_TOCNT6          0x00400000U
+#define DSI_TCCR0_HSTX_TOCNT7          0x00800000U
+#define DSI_TCCR0_HSTX_TOCNT8          0x01000000U
+#define DSI_TCCR0_HSTX_TOCNT9          0x02000000U
+#define DSI_TCCR0_HSTX_TOCNT10         0x04000000U
+#define DSI_TCCR0_HSTX_TOCNT11         0x08000000U
+#define DSI_TCCR0_HSTX_TOCNT12         0x10000000U
+#define DSI_TCCR0_HSTX_TOCNT13         0x20000000U
+#define DSI_TCCR0_HSTX_TOCNT14         0x40000000U
+#define DSI_TCCR0_HSTX_TOCNT15         0x80000000U
 
 /*******************  Bit definition for DSI_TCCR1 register  **************/
-#define DSI_TCCR1_HSRD_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< High-Speed Read Timeout Counter */
-#define DSI_TCCR1_HSRD_TOCNT0          ((uint32_t)0x00000001U)
-#define DSI_TCCR1_HSRD_TOCNT1          ((uint32_t)0x00000002U)
-#define DSI_TCCR1_HSRD_TOCNT2          ((uint32_t)0x00000004U)
-#define DSI_TCCR1_HSRD_TOCNT3          ((uint32_t)0x00000008U)
-#define DSI_TCCR1_HSRD_TOCNT4          ((uint32_t)0x00000010U)
-#define DSI_TCCR1_HSRD_TOCNT5          ((uint32_t)0x00000020U)
-#define DSI_TCCR1_HSRD_TOCNT6          ((uint32_t)0x00000040U)
-#define DSI_TCCR1_HSRD_TOCNT7          ((uint32_t)0x00000080U)
-#define DSI_TCCR1_HSRD_TOCNT8          ((uint32_t)0x00000100U)
-#define DSI_TCCR1_HSRD_TOCNT9          ((uint32_t)0x00000200U)
-#define DSI_TCCR1_HSRD_TOCNT10         ((uint32_t)0x00000400U)
-#define DSI_TCCR1_HSRD_TOCNT11         ((uint32_t)0x00000800U)
-#define DSI_TCCR1_HSRD_TOCNT12         ((uint32_t)0x00001000U)
-#define DSI_TCCR1_HSRD_TOCNT13         ((uint32_t)0x00002000U)
-#define DSI_TCCR1_HSRD_TOCNT14         ((uint32_t)0x00004000U)
-#define DSI_TCCR1_HSRD_TOCNT15         ((uint32_t)0x00008000U)
+#define DSI_TCCR1_HSRD_TOCNT           0x0000FFFFU               /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0          0x00000001U
+#define DSI_TCCR1_HSRD_TOCNT1          0x00000002U
+#define DSI_TCCR1_HSRD_TOCNT2          0x00000004U
+#define DSI_TCCR1_HSRD_TOCNT3          0x00000008U
+#define DSI_TCCR1_HSRD_TOCNT4          0x00000010U
+#define DSI_TCCR1_HSRD_TOCNT5          0x00000020U
+#define DSI_TCCR1_HSRD_TOCNT6          0x00000040U
+#define DSI_TCCR1_HSRD_TOCNT7          0x00000080U
+#define DSI_TCCR1_HSRD_TOCNT8          0x00000100U
+#define DSI_TCCR1_HSRD_TOCNT9          0x00000200U
+#define DSI_TCCR1_HSRD_TOCNT10         0x00000400U
+#define DSI_TCCR1_HSRD_TOCNT11         0x00000800U
+#define DSI_TCCR1_HSRD_TOCNT12         0x00001000U
+#define DSI_TCCR1_HSRD_TOCNT13         0x00002000U
+#define DSI_TCCR1_HSRD_TOCNT14         0x00004000U
+#define DSI_TCCR1_HSRD_TOCNT15         0x00008000U
 
 /*******************  Bit definition for DSI_TCCR2 register  **************/
-#define DSI_TCCR2_LPRD_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-Power Read Timeout Counter */
-#define DSI_TCCR2_LPRD_TOCNT0          ((uint32_t)0x00000001U)
-#define DSI_TCCR2_LPRD_TOCNT1          ((uint32_t)0x00000002U)
-#define DSI_TCCR2_LPRD_TOCNT2          ((uint32_t)0x00000004U)
-#define DSI_TCCR2_LPRD_TOCNT3          ((uint32_t)0x00000008U)
-#define DSI_TCCR2_LPRD_TOCNT4          ((uint32_t)0x00000010U)
-#define DSI_TCCR2_LPRD_TOCNT5          ((uint32_t)0x00000020U)
-#define DSI_TCCR2_LPRD_TOCNT6          ((uint32_t)0x00000040U)
-#define DSI_TCCR2_LPRD_TOCNT7          ((uint32_t)0x00000080U)
-#define DSI_TCCR2_LPRD_TOCNT8          ((uint32_t)0x00000100U)
-#define DSI_TCCR2_LPRD_TOCNT9          ((uint32_t)0x00000200U)
-#define DSI_TCCR2_LPRD_TOCNT10         ((uint32_t)0x00000400U)
-#define DSI_TCCR2_LPRD_TOCNT11         ((uint32_t)0x00000800U)
-#define DSI_TCCR2_LPRD_TOCNT12         ((uint32_t)0x00001000U)
-#define DSI_TCCR2_LPRD_TOCNT13         ((uint32_t)0x00002000U)
-#define DSI_TCCR2_LPRD_TOCNT14         ((uint32_t)0x00004000U)
-#define DSI_TCCR2_LPRD_TOCNT15         ((uint32_t)0x00008000U)
+#define DSI_TCCR2_LPRD_TOCNT           0x0000FFFFU               /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0          0x00000001U
+#define DSI_TCCR2_LPRD_TOCNT1          0x00000002U
+#define DSI_TCCR2_LPRD_TOCNT2          0x00000004U
+#define DSI_TCCR2_LPRD_TOCNT3          0x00000008U
+#define DSI_TCCR2_LPRD_TOCNT4          0x00000010U
+#define DSI_TCCR2_LPRD_TOCNT5          0x00000020U
+#define DSI_TCCR2_LPRD_TOCNT6          0x00000040U
+#define DSI_TCCR2_LPRD_TOCNT7          0x00000080U
+#define DSI_TCCR2_LPRD_TOCNT8          0x00000100U
+#define DSI_TCCR2_LPRD_TOCNT9          0x00000200U
+#define DSI_TCCR2_LPRD_TOCNT10         0x00000400U
+#define DSI_TCCR2_LPRD_TOCNT11         0x00000800U
+#define DSI_TCCR2_LPRD_TOCNT12         0x00001000U
+#define DSI_TCCR2_LPRD_TOCNT13         0x00002000U
+#define DSI_TCCR2_LPRD_TOCNT14         0x00004000U
+#define DSI_TCCR2_LPRD_TOCNT15         0x00008000U
 
 /*******************  Bit definition for DSI_TCCR3 register  **************/
-#define DSI_TCCR3_HSWR_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< High-Speed Write Timeout Counter */
-#define DSI_TCCR3_HSWR_TOCNT0          ((uint32_t)0x00000001U)
-#define DSI_TCCR3_HSWR_TOCNT1          ((uint32_t)0x00000002U)
-#define DSI_TCCR3_HSWR_TOCNT2          ((uint32_t)0x00000004U)
-#define DSI_TCCR3_HSWR_TOCNT3          ((uint32_t)0x00000008U)
-#define DSI_TCCR3_HSWR_TOCNT4          ((uint32_t)0x00000010U)
-#define DSI_TCCR3_HSWR_TOCNT5          ((uint32_t)0x00000020U)
-#define DSI_TCCR3_HSWR_TOCNT6          ((uint32_t)0x00000040U)
-#define DSI_TCCR3_HSWR_TOCNT7          ((uint32_t)0x00000080U)
-#define DSI_TCCR3_HSWR_TOCNT8          ((uint32_t)0x00000100U)
-#define DSI_TCCR3_HSWR_TOCNT9          ((uint32_t)0x00000200U)
-#define DSI_TCCR3_HSWR_TOCNT10         ((uint32_t)0x00000400U)
-#define DSI_TCCR3_HSWR_TOCNT11         ((uint32_t)0x00000800U)
-#define DSI_TCCR3_HSWR_TOCNT12         ((uint32_t)0x00001000U)
-#define DSI_TCCR3_HSWR_TOCNT13         ((uint32_t)0x00002000U)
-#define DSI_TCCR3_HSWR_TOCNT14         ((uint32_t)0x00004000U)
-#define DSI_TCCR3_HSWR_TOCNT15         ((uint32_t)0x00008000U)
+#define DSI_TCCR3_HSWR_TOCNT           0x0000FFFFU               /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0          0x00000001U
+#define DSI_TCCR3_HSWR_TOCNT1          0x00000002U
+#define DSI_TCCR3_HSWR_TOCNT2          0x00000004U
+#define DSI_TCCR3_HSWR_TOCNT3          0x00000008U
+#define DSI_TCCR3_HSWR_TOCNT4          0x00000010U
+#define DSI_TCCR3_HSWR_TOCNT5          0x00000020U
+#define DSI_TCCR3_HSWR_TOCNT6          0x00000040U
+#define DSI_TCCR3_HSWR_TOCNT7          0x00000080U
+#define DSI_TCCR3_HSWR_TOCNT8          0x00000100U
+#define DSI_TCCR3_HSWR_TOCNT9          0x00000200U
+#define DSI_TCCR3_HSWR_TOCNT10         0x00000400U
+#define DSI_TCCR3_HSWR_TOCNT11         0x00000800U
+#define DSI_TCCR3_HSWR_TOCNT12         0x00001000U
+#define DSI_TCCR3_HSWR_TOCNT13         0x00002000U
+#define DSI_TCCR3_HSWR_TOCNT14         0x00004000U
+#define DSI_TCCR3_HSWR_TOCNT15         0x00008000U
 
-#define DSI_TCCR3_PM                   ((uint32_t)0x01000000U)               /*!< Presp Mode */
+#define DSI_TCCR3_PM                   0x01000000U               /*!< Presp Mode */
 
 /*******************  Bit definition for DSI_TCCR4 register  **************/
-#define DSI_TCCR4_LPWR_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-Power Write Timeout Counter */
-#define DSI_TCCR4_LPWR_TOCNT0          ((uint32_t)0x00000001U)
-#define DSI_TCCR4_LPWR_TOCNT1          ((uint32_t)0x00000002U)
-#define DSI_TCCR4_LPWR_TOCNT2          ((uint32_t)0x00000004U)
-#define DSI_TCCR4_LPWR_TOCNT3          ((uint32_t)0x00000008U)
-#define DSI_TCCR4_LPWR_TOCNT4          ((uint32_t)0x00000010U)
-#define DSI_TCCR4_LPWR_TOCNT5          ((uint32_t)0x00000020U)
-#define DSI_TCCR4_LPWR_TOCNT6          ((uint32_t)0x00000040U)
-#define DSI_TCCR4_LPWR_TOCNT7          ((uint32_t)0x00000080U)
-#define DSI_TCCR4_LPWR_TOCNT8          ((uint32_t)0x00000100U)
-#define DSI_TCCR4_LPWR_TOCNT9          ((uint32_t)0x00000200U)
-#define DSI_TCCR4_LPWR_TOCNT10         ((uint32_t)0x00000400U)
-#define DSI_TCCR4_LPWR_TOCNT11         ((uint32_t)0x00000800U)
-#define DSI_TCCR4_LPWR_TOCNT12         ((uint32_t)0x00001000U)
-#define DSI_TCCR4_LPWR_TOCNT13         ((uint32_t)0x00002000U)
-#define DSI_TCCR4_LPWR_TOCNT14         ((uint32_t)0x00004000U)
-#define DSI_TCCR4_LPWR_TOCNT15         ((uint32_t)0x00008000U)
+#define DSI_TCCR4_LPWR_TOCNT           0x0000FFFFU               /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0          0x00000001U
+#define DSI_TCCR4_LPWR_TOCNT1          0x00000002U
+#define DSI_TCCR4_LPWR_TOCNT2          0x00000004U
+#define DSI_TCCR4_LPWR_TOCNT3          0x00000008U
+#define DSI_TCCR4_LPWR_TOCNT4          0x00000010U
+#define DSI_TCCR4_LPWR_TOCNT5          0x00000020U
+#define DSI_TCCR4_LPWR_TOCNT6          0x00000040U
+#define DSI_TCCR4_LPWR_TOCNT7          0x00000080U
+#define DSI_TCCR4_LPWR_TOCNT8          0x00000100U
+#define DSI_TCCR4_LPWR_TOCNT9          0x00000200U
+#define DSI_TCCR4_LPWR_TOCNT10         0x00000400U
+#define DSI_TCCR4_LPWR_TOCNT11         0x00000800U
+#define DSI_TCCR4_LPWR_TOCNT12         0x00001000U
+#define DSI_TCCR4_LPWR_TOCNT13         0x00002000U
+#define DSI_TCCR4_LPWR_TOCNT14         0x00004000U
+#define DSI_TCCR4_LPWR_TOCNT15         0x00008000U
 
 /*******************  Bit definition for DSI_TCCR5 register  **************/
-#define DSI_TCCR5_BTA_TOCNT            ((uint32_t)0x0000FFFFU)               /*!< Bus-Turn-Around Timeout Counter */
-#define DSI_TCCR5_BTA_TOCNT0           ((uint32_t)0x00000001U)
-#define DSI_TCCR5_BTA_TOCNT1           ((uint32_t)0x00000002U)
-#define DSI_TCCR5_BTA_TOCNT2           ((uint32_t)0x00000004U)
-#define DSI_TCCR5_BTA_TOCNT3           ((uint32_t)0x00000008U)
-#define DSI_TCCR5_BTA_TOCNT4           ((uint32_t)0x00000010U)
-#define DSI_TCCR5_BTA_TOCNT5           ((uint32_t)0x00000020U)
-#define DSI_TCCR5_BTA_TOCNT6           ((uint32_t)0x00000040U)
-#define DSI_TCCR5_BTA_TOCNT7           ((uint32_t)0x00000080U)
-#define DSI_TCCR5_BTA_TOCNT8           ((uint32_t)0x00000100U)
-#define DSI_TCCR5_BTA_TOCNT9           ((uint32_t)0x00000200U)
-#define DSI_TCCR5_BTA_TOCNT10          ((uint32_t)0x00000400U)
-#define DSI_TCCR5_BTA_TOCNT11          ((uint32_t)0x00000800U)
-#define DSI_TCCR5_BTA_TOCNT12          ((uint32_t)0x00001000U)
-#define DSI_TCCR5_BTA_TOCNT13          ((uint32_t)0x00002000U)
-#define DSI_TCCR5_BTA_TOCNT14          ((uint32_t)0x00004000U)
-#define DSI_TCCR5_BTA_TOCNT15          ((uint32_t)0x00008000U)
+#define DSI_TCCR5_BTA_TOCNT            0x0000FFFFU               /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0           0x00000001U
+#define DSI_TCCR5_BTA_TOCNT1           0x00000002U
+#define DSI_TCCR5_BTA_TOCNT2           0x00000004U
+#define DSI_TCCR5_BTA_TOCNT3           0x00000008U
+#define DSI_TCCR5_BTA_TOCNT4           0x00000010U
+#define DSI_TCCR5_BTA_TOCNT5           0x00000020U
+#define DSI_TCCR5_BTA_TOCNT6           0x00000040U
+#define DSI_TCCR5_BTA_TOCNT7           0x00000080U
+#define DSI_TCCR5_BTA_TOCNT8           0x00000100U
+#define DSI_TCCR5_BTA_TOCNT9           0x00000200U
+#define DSI_TCCR5_BTA_TOCNT10          0x00000400U
+#define DSI_TCCR5_BTA_TOCNT11          0x00000800U
+#define DSI_TCCR5_BTA_TOCNT12          0x00001000U
+#define DSI_TCCR5_BTA_TOCNT13          0x00002000U
+#define DSI_TCCR5_BTA_TOCNT14          0x00004000U
+#define DSI_TCCR5_BTA_TOCNT15          0x00008000U
 
 /*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                   ((uint32_t)0x00000003U)               /*!< 3D Mode */
-#define DSI_TDCR_3DM0                  ((uint32_t)0x00000001U)
-#define DSI_TDCR_3DM1                  ((uint32_t)0x00000002U)
+#define DSI_TDCR_3DM                   0x00000003U               /*!< 3D Mode */
+#define DSI_TDCR_3DM0                  0x00000001U
+#define DSI_TDCR_3DM1                  0x00000002U
 
-#define DSI_TDCR_3DF                   ((uint32_t)0x0000000CU)               /*!< 3D Format */
-#define DSI_TDCR_3DF0                  ((uint32_t)0x00000004U)
-#define DSI_TDCR_3DF1                  ((uint32_t)0x00000008U)
+#define DSI_TDCR_3DF                   0x0000000CU               /*!< 3D Format */
+#define DSI_TDCR_3DF0                  0x00000004U
+#define DSI_TDCR_3DF1                  0x00000008U
 
-#define DSI_TDCR_SVS                   ((uint32_t)0x00000010U)               /*!< Second VSYNC */
-#define DSI_TDCR_RF                    ((uint32_t)0x00000020U)               /*!< Right First */
-#define DSI_TDCR_S3DC                  ((uint32_t)0x00010000U)               /*!< Send 3D Control */
+#define DSI_TDCR_SVS                   0x00000010U               /*!< Second VSYNC */
+#define DSI_TDCR_RF                    0x00000020U               /*!< Right First */
+#define DSI_TDCR_S3DC                  0x00010000U               /*!< Send 3D Control */
 
 /*******************  Bit definition for DSI_CLCR register  ***************/
-#define DSI_CLCR_DPCC                  ((uint32_t)0x00000001U)               /*!< D-PHY Clock Control */
-#define DSI_CLCR_ACR                   ((uint32_t)0x00000002U)               /*!< Automatic Clocklane Control */
+#define DSI_CLCR_DPCC                  0x00000001U               /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR                   0x00000002U               /*!< Automatic Clocklane Control */
 
 /*******************  Bit definition for DSI_CLTCR register  **************/
-#define DSI_CLTCR_LP2HS_TIME           ((uint32_t)0x000003FFU)               /*!< Low-Power to High-Speed Time */
-#define DSI_CLTCR_LP2HS_TIME0          ((uint32_t)0x00000001U)
-#define DSI_CLTCR_LP2HS_TIME1          ((uint32_t)0x00000002U)
-#define DSI_CLTCR_LP2HS_TIME2          ((uint32_t)0x00000004U)
-#define DSI_CLTCR_LP2HS_TIME3          ((uint32_t)0x00000008U)
-#define DSI_CLTCR_LP2HS_TIME4          ((uint32_t)0x00000010U)
-#define DSI_CLTCR_LP2HS_TIME5          ((uint32_t)0x00000020U)
-#define DSI_CLTCR_LP2HS_TIME6          ((uint32_t)0x00000040U)
-#define DSI_CLTCR_LP2HS_TIME7          ((uint32_t)0x00000080U)
-#define DSI_CLTCR_LP2HS_TIME8          ((uint32_t)0x00000100U)
-#define DSI_CLTCR_LP2HS_TIME9          ((uint32_t)0x00000200U)
+#define DSI_CLTCR_LP2HS_TIME           0x000003FFU               /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0          0x00000001U
+#define DSI_CLTCR_LP2HS_TIME1          0x00000002U
+#define DSI_CLTCR_LP2HS_TIME2          0x00000004U
+#define DSI_CLTCR_LP2HS_TIME3          0x00000008U
+#define DSI_CLTCR_LP2HS_TIME4          0x00000010U
+#define DSI_CLTCR_LP2HS_TIME5          0x00000020U
+#define DSI_CLTCR_LP2HS_TIME6          0x00000040U
+#define DSI_CLTCR_LP2HS_TIME7          0x00000080U
+#define DSI_CLTCR_LP2HS_TIME8          0x00000100U
+#define DSI_CLTCR_LP2HS_TIME9          0x00000200U
 
-#define DSI_CLTCR_HS2LP_TIME           ((uint32_t)0x03FF0000U)               /*!< High-Speed to Low-Power Time */
-#define DSI_CLTCR_HS2LP_TIME0          ((uint32_t)0x00010000U)
-#define DSI_CLTCR_HS2LP_TIME1          ((uint32_t)0x00020000U)
-#define DSI_CLTCR_HS2LP_TIME2          ((uint32_t)0x00040000U)
-#define DSI_CLTCR_HS2LP_TIME3          ((uint32_t)0x00080000U)
-#define DSI_CLTCR_HS2LP_TIME4          ((uint32_t)0x00100000U)
-#define DSI_CLTCR_HS2LP_TIME5          ((uint32_t)0x00200000U)
-#define DSI_CLTCR_HS2LP_TIME6          ((uint32_t)0x00400000U)
-#define DSI_CLTCR_HS2LP_TIME7          ((uint32_t)0x00800000U)
-#define DSI_CLTCR_HS2LP_TIME8          ((uint32_t)0x01000000U)
-#define DSI_CLTCR_HS2LP_TIME9          ((uint32_t)0x02000000U)
+#define DSI_CLTCR_HS2LP_TIME           0x03FF0000U               /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0          0x00010000U
+#define DSI_CLTCR_HS2LP_TIME1          0x00020000U
+#define DSI_CLTCR_HS2LP_TIME2          0x00040000U
+#define DSI_CLTCR_HS2LP_TIME3          0x00080000U
+#define DSI_CLTCR_HS2LP_TIME4          0x00100000U
+#define DSI_CLTCR_HS2LP_TIME5          0x00200000U
+#define DSI_CLTCR_HS2LP_TIME6          0x00400000U
+#define DSI_CLTCR_HS2LP_TIME7          0x00800000U
+#define DSI_CLTCR_HS2LP_TIME8          0x01000000U
+#define DSI_CLTCR_HS2LP_TIME9          0x02000000U
 
 /*******************  Bit definition for DSI_DLTCR register  **************/
-#define DSI_DLTCR_MRD_TIME             ((uint32_t)0x00007FFFU)               /*!< Maximum Read Time */
-#define DSI_DLTCR_MRD_TIME0            ((uint32_t)0x00000001U)
-#define DSI_DLTCR_MRD_TIME1            ((uint32_t)0x00000002U)
-#define DSI_DLTCR_MRD_TIME2            ((uint32_t)0x00000004U)
-#define DSI_DLTCR_MRD_TIME3            ((uint32_t)0x00000008U)
-#define DSI_DLTCR_MRD_TIME4            ((uint32_t)0x00000010U)
-#define DSI_DLTCR_MRD_TIME5            ((uint32_t)0x00000020U)
-#define DSI_DLTCR_MRD_TIME6            ((uint32_t)0x00000040U)
-#define DSI_DLTCR_MRD_TIME7            ((uint32_t)0x00000080U)
-#define DSI_DLTCR_MRD_TIME8            ((uint32_t)0x00000100U)
-#define DSI_DLTCR_MRD_TIME9            ((uint32_t)0x00000200U)
-#define DSI_DLTCR_MRD_TIME10           ((uint32_t)0x00000400U)
-#define DSI_DLTCR_MRD_TIME11           ((uint32_t)0x00000800U)
-#define DSI_DLTCR_MRD_TIME12           ((uint32_t)0x00001000U)
-#define DSI_DLTCR_MRD_TIME13           ((uint32_t)0x00002000U)
-#define DSI_DLTCR_MRD_TIME14           ((uint32_t)0x00004000U)
+#define DSI_DLTCR_MRD_TIME             0x00007FFFU               /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0            0x00000001U
+#define DSI_DLTCR_MRD_TIME1            0x00000002U
+#define DSI_DLTCR_MRD_TIME2            0x00000004U
+#define DSI_DLTCR_MRD_TIME3            0x00000008U
+#define DSI_DLTCR_MRD_TIME4            0x00000010U
+#define DSI_DLTCR_MRD_TIME5            0x00000020U
+#define DSI_DLTCR_MRD_TIME6            0x00000040U
+#define DSI_DLTCR_MRD_TIME7            0x00000080U
+#define DSI_DLTCR_MRD_TIME8            0x00000100U
+#define DSI_DLTCR_MRD_TIME9            0x00000200U
+#define DSI_DLTCR_MRD_TIME10           0x00000400U
+#define DSI_DLTCR_MRD_TIME11           0x00000800U
+#define DSI_DLTCR_MRD_TIME12           0x00001000U
+#define DSI_DLTCR_MRD_TIME13           0x00002000U
+#define DSI_DLTCR_MRD_TIME14           0x00004000U
 
-#define DSI_DLTCR_LP2HS_TIME           ((uint32_t)0x00FF0000U)               /*!< Low-Power To High-Speed Time */
-#define DSI_DLTCR_LP2HS_TIME0          ((uint32_t)0x00010000U)
-#define DSI_DLTCR_LP2HS_TIME1          ((uint32_t)0x00020000U)
-#define DSI_DLTCR_LP2HS_TIME2          ((uint32_t)0x00040000U)
-#define DSI_DLTCR_LP2HS_TIME3          ((uint32_t)0x00080000U)
-#define DSI_DLTCR_LP2HS_TIME4          ((uint32_t)0x00100000U)
-#define DSI_DLTCR_LP2HS_TIME5          ((uint32_t)0x00200000U)
-#define DSI_DLTCR_LP2HS_TIME6          ((uint32_t)0x00400000U)
-#define DSI_DLTCR_LP2HS_TIME7          ((uint32_t)0x00800000U)
+#define DSI_DLTCR_LP2HS_TIME           0x00FF0000U               /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0          0x00010000U
+#define DSI_DLTCR_LP2HS_TIME1          0x00020000U
+#define DSI_DLTCR_LP2HS_TIME2          0x00040000U
+#define DSI_DLTCR_LP2HS_TIME3          0x00080000U
+#define DSI_DLTCR_LP2HS_TIME4          0x00100000U
+#define DSI_DLTCR_LP2HS_TIME5          0x00200000U
+#define DSI_DLTCR_LP2HS_TIME6          0x00400000U
+#define DSI_DLTCR_LP2HS_TIME7          0x00800000U
 
-#define DSI_DLTCR_HS2LP_TIME           ((uint32_t)0xFF000000U)               /*!< High-Speed To Low-Power Time */
-#define DSI_DLTCR_HS2LP_TIME0          ((uint32_t)0x01000000U)
-#define DSI_DLTCR_HS2LP_TIME1          ((uint32_t)0x02000000U)
-#define DSI_DLTCR_HS2LP_TIME2          ((uint32_t)0x04000000U)
-#define DSI_DLTCR_HS2LP_TIME3          ((uint32_t)0x08000000U)
-#define DSI_DLTCR_HS2LP_TIME4          ((uint32_t)0x10000000U)
-#define DSI_DLTCR_HS2LP_TIME5          ((uint32_t)0x20000000U)
-#define DSI_DLTCR_HS2LP_TIME6          ((uint32_t)0x40000000U)
-#define DSI_DLTCR_HS2LP_TIME7          ((uint32_t)0x80000000U)
+#define DSI_DLTCR_HS2LP_TIME           0xFF000000U               /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0          0x01000000U
+#define DSI_DLTCR_HS2LP_TIME1          0x02000000U
+#define DSI_DLTCR_HS2LP_TIME2          0x04000000U
+#define DSI_DLTCR_HS2LP_TIME3          0x08000000U
+#define DSI_DLTCR_HS2LP_TIME4          0x10000000U
+#define DSI_DLTCR_HS2LP_TIME5          0x20000000U
+#define DSI_DLTCR_HS2LP_TIME6          0x40000000U
+#define DSI_DLTCR_HS2LP_TIME7          0x80000000U
 
 /*******************  Bit definition for DSI_PCTLR register  **************/
-#define DSI_PCTLR_DEN                  ((uint32_t)0x00000002U)               /*!< Digital Enable */
-#define DSI_PCTLR_CKE                  ((uint32_t)0x00000004U)               /*!< Clock Enable */
+#define DSI_PCTLR_DEN                  0x00000002U               /*!< Digital Enable */
+#define DSI_PCTLR_CKE                  0x00000004U               /*!< Clock Enable */
 
 /*******************  Bit definition for DSI_PCONFR register  *************/
-#define DSI_PCONFR_NL                  ((uint32_t)0x00000003U)               /*!< Number of Lanes */
-#define DSI_PCONFR_NL0                 ((uint32_t)0x00000001U)
-#define DSI_PCONFR_NL1                 ((uint32_t)0x00000002U)
+#define DSI_PCONFR_NL                  0x00000003U               /*!< Number of Lanes */
+#define DSI_PCONFR_NL0                 0x00000001U
+#define DSI_PCONFR_NL1                 0x00000002U
 
-#define DSI_PCONFR_SW_TIME             ((uint32_t)0x0000FF00U)               /*!< Stop Wait Time */
-#define DSI_PCONFR_SW_TIME0            ((uint32_t)0x00000100U)
-#define DSI_PCONFR_SW_TIME1            ((uint32_t)0x00000200U)
-#define DSI_PCONFR_SW_TIME2            ((uint32_t)0x00000400U)
-#define DSI_PCONFR_SW_TIME3            ((uint32_t)0x00000800U)
-#define DSI_PCONFR_SW_TIME4            ((uint32_t)0x00001000U)
-#define DSI_PCONFR_SW_TIME5            ((uint32_t)0x00002000U)
-#define DSI_PCONFR_SW_TIME6            ((uint32_t)0x00004000U)
-#define DSI_PCONFR_SW_TIME7            ((uint32_t)0x00008000U)
+#define DSI_PCONFR_SW_TIME             0x0000FF00U               /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0            0x00000100U
+#define DSI_PCONFR_SW_TIME1            0x00000200U
+#define DSI_PCONFR_SW_TIME2            0x00000400U
+#define DSI_PCONFR_SW_TIME3            0x00000800U
+#define DSI_PCONFR_SW_TIME4            0x00001000U
+#define DSI_PCONFR_SW_TIME5            0x00002000U
+#define DSI_PCONFR_SW_TIME6            0x00004000U
+#define DSI_PCONFR_SW_TIME7            0x00008000U
 
 /*******************  Bit definition for DSI_PUCR register  ***************/
-#define DSI_PUCR_URCL                  ((uint32_t)0x00000001U)               /*!< ULPS Request on Clock Lane */
-#define DSI_PUCR_UECL                  ((uint32_t)0x00000002U)               /*!< ULPS Exit on Clock Lane */
-#define DSI_PUCR_URDL                  ((uint32_t)0x00000004U)               /*!< ULPS Request on Data Lane */
-#define DSI_PUCR_UEDL                  ((uint32_t)0x00000008U)               /*!< ULPS Exit on Data Lane */
+#define DSI_PUCR_URCL                  0x00000001U               /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL                  0x00000002U               /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL                  0x00000004U               /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL                  0x00000008U               /*!< ULPS Exit on Data Lane */
 
 /*******************  Bit definition for DSI_PTTCR register  **************/
-#define DSI_PTTCR_TX_TRIG              ((uint32_t)0x0000000FU)               /*!< Transmission Trigger */
-#define DSI_PTTCR_TX_TRIG0             ((uint32_t)0x00000001U)
-#define DSI_PTTCR_TX_TRIG1             ((uint32_t)0x00000002U)
-#define DSI_PTTCR_TX_TRIG2             ((uint32_t)0x00000004U)
-#define DSI_PTTCR_TX_TRIG3             ((uint32_t)0x00000008U)
+#define DSI_PTTCR_TX_TRIG              0x0000000FU               /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0             0x00000001U
+#define DSI_PTTCR_TX_TRIG1             0x00000002U
+#define DSI_PTTCR_TX_TRIG2             0x00000004U
+#define DSI_PTTCR_TX_TRIG3             0x00000008U
 
 /*******************  Bit definition for DSI_PSR register  ****************/
-#define DSI_PSR_PD                     ((uint32_t)0x00000002U)               /*!< PHY Direction */
-#define DSI_PSR_PSSC                   ((uint32_t)0x00000004U)               /*!< PHY Stop State Clock lane */
-#define DSI_PSR_UANC                   ((uint32_t)0x00000008U)               /*!< ULPS Active Not Clock lane */
-#define DSI_PSR_PSS0                   ((uint32_t)0x00000010U)               /*!< PHY Stop State lane 0 */
-#define DSI_PSR_UAN0                   ((uint32_t)0x00000020U)               /*!< ULPS Active Not lane 0 */
-#define DSI_PSR_RUE0                   ((uint32_t)0x00000040U)               /*!< RX ULPS Escape lane 0 */
-#define DSI_PSR_PSS1                   ((uint32_t)0x00000080U)               /*!< PHY Stop State lane 1 */
-#define DSI_PSR_UAN1                   ((uint32_t)0x00000100U)               /*!< ULPS Active Not lane 1 */
+#define DSI_PSR_PD                     0x00000002U               /*!< PHY Direction */
+#define DSI_PSR_PSSC                   0x00000004U               /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC                   0x00000008U               /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0                   0x00000010U               /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0                   0x00000020U               /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0                   0x00000040U               /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1                   0x00000080U               /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1                   0x00000100U               /*!< ULPS Active Not lane 1 */
 
 /*******************  Bit definition for DSI_ISR0 register  ***************/
-#define DSI_ISR0_AE0                   ((uint32_t)0x00000001U)               /*!< Acknowledge Error 0 */
-#define DSI_ISR0_AE1                   ((uint32_t)0x00000002U)               /*!< Acknowledge Error 1 */
-#define DSI_ISR0_AE2                   ((uint32_t)0x00000004U)               /*!< Acknowledge Error 2 */
-#define DSI_ISR0_AE3                   ((uint32_t)0x00000008U)               /*!< Acknowledge Error 3 */
-#define DSI_ISR0_AE4                   ((uint32_t)0x00000010U)               /*!< Acknowledge Error 4 */
-#define DSI_ISR0_AE5                   ((uint32_t)0x00000020U)               /*!< Acknowledge Error 5 */
-#define DSI_ISR0_AE6                   ((uint32_t)0x00000040U)               /*!< Acknowledge Error 6 */
-#define DSI_ISR0_AE7                   ((uint32_t)0x00000080U)               /*!< Acknowledge Error 7 */
-#define DSI_ISR0_AE8                   ((uint32_t)0x00000100U)               /*!< Acknowledge Error 8 */
-#define DSI_ISR0_AE9                   ((uint32_t)0x00000200U)               /*!< Acknowledge Error 9 */
-#define DSI_ISR0_AE10                  ((uint32_t)0x00000400U)               /*!< Acknowledge Error 10 */
-#define DSI_ISR0_AE11                  ((uint32_t)0x00000800U)               /*!< Acknowledge Error 11 */
-#define DSI_ISR0_AE12                  ((uint32_t)0x00001000U)               /*!< Acknowledge Error 12 */
-#define DSI_ISR0_AE13                  ((uint32_t)0x00002000U)               /*!< Acknowledge Error 13 */
-#define DSI_ISR0_AE14                  ((uint32_t)0x00004000U)               /*!< Acknowledge Error 14 */
-#define DSI_ISR0_AE15                  ((uint32_t)0x00008000U)               /*!< Acknowledge Error 15 */
-#define DSI_ISR0_PE0                   ((uint32_t)0x00010000U)               /*!< PHY Error 0 */
-#define DSI_ISR0_PE1                   ((uint32_t)0x00020000U)               /*!< PHY Error 1 */
-#define DSI_ISR0_PE2                   ((uint32_t)0x00040000U)               /*!< PHY Error 2 */
-#define DSI_ISR0_PE3                   ((uint32_t)0x00080000U)               /*!< PHY Error 3 */
-#define DSI_ISR0_PE4                   ((uint32_t)0x00100000U)               /*!< PHY Error 4 */
+#define DSI_ISR0_AE0                   0x00000001U               /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1                   0x00000002U               /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2                   0x00000004U               /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3                   0x00000008U               /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4                   0x00000010U               /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5                   0x00000020U               /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6                   0x00000040U               /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7                   0x00000080U               /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8                   0x00000100U               /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9                   0x00000200U               /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10                  0x00000400U               /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11                  0x00000800U               /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12                  0x00001000U               /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13                  0x00002000U               /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14                  0x00004000U               /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15                  0x00008000U               /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0                   0x00010000U               /*!< PHY Error 0 */
+#define DSI_ISR0_PE1                   0x00020000U               /*!< PHY Error 1 */
+#define DSI_ISR0_PE2                   0x00040000U               /*!< PHY Error 2 */
+#define DSI_ISR0_PE3                   0x00080000U               /*!< PHY Error 3 */
+#define DSI_ISR0_PE4                   0x00100000U               /*!< PHY Error 4 */
 
 /*******************  Bit definition for DSI_ISR1 register  ***************/
-#define DSI_ISR1_TOHSTX                ((uint32_t)0x00000001U)               /*!< Timeout High-Speed Transmission */
-#define DSI_ISR1_TOLPRX                ((uint32_t)0x00000002U)               /*!< Timeout Low-Power Reception */
-#define DSI_ISR1_ECCSE                 ((uint32_t)0x00000004U)               /*!< ECC Single-bit Error */
-#define DSI_ISR1_ECCME                 ((uint32_t)0x00000008U)               /*!< ECC Multi-bit Error */
-#define DSI_ISR1_CRCE                  ((uint32_t)0x00000010U)               /*!< CRC Error */
-#define DSI_ISR1_PSE                   ((uint32_t)0x00000020U)               /*!< Packet Size Error */
-#define DSI_ISR1_EOTPE                 ((uint32_t)0x00000040U)               /*!< EoTp Error */
-#define DSI_ISR1_LPWRE                 ((uint32_t)0x00000080U)               /*!< LTDC Payload Write Error */
-#define DSI_ISR1_GCWRE                 ((uint32_t)0x00000100U)               /*!< Generic Command Write Error */
-#define DSI_ISR1_GPWRE                 ((uint32_t)0x00000200U)               /*!< Generic Payload Write Error */
-#define DSI_ISR1_GPTXE                 ((uint32_t)0x00000400U)               /*!< Generic Payload Transmit Error */
-#define DSI_ISR1_GPRDE                 ((uint32_t)0x00000800U)               /*!< Generic Payload Read Error */
-#define DSI_ISR1_GPRXE                 ((uint32_t)0x00001000U)               /*!< Generic Payload Receive Error */
+#define DSI_ISR1_TOHSTX                0x00000001U               /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX                0x00000002U               /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE                 0x00000004U               /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME                 0x00000008U               /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE                  0x00000010U               /*!< CRC Error */
+#define DSI_ISR1_PSE                   0x00000020U               /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE                 0x00000040U               /*!< EoTp Error */
+#define DSI_ISR1_LPWRE                 0x00000080U               /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE                 0x00000100U               /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE                 0x00000200U               /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE                 0x00000400U               /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE                 0x00000800U               /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE                 0x00001000U               /*!< Generic Payload Receive Error */
 
 /*******************  Bit definition for DSI_IER0 register  ***************/
-#define DSI_IER0_AE0IE                 ((uint32_t)0x00000001U)               /*!< Acknowledge Error 0 Interrupt Enable */
-#define DSI_IER0_AE1IE                 ((uint32_t)0x00000002U)               /*!< Acknowledge Error 1 Interrupt Enable */
-#define DSI_IER0_AE2IE                 ((uint32_t)0x00000004U)               /*!< Acknowledge Error 2 Interrupt Enable */
-#define DSI_IER0_AE3IE                 ((uint32_t)0x00000008U)               /*!< Acknowledge Error 3 Interrupt Enable */
-#define DSI_IER0_AE4IE                 ((uint32_t)0x00000010U)               /*!< Acknowledge Error 4 Interrupt Enable */
-#define DSI_IER0_AE5IE                 ((uint32_t)0x00000020U)               /*!< Acknowledge Error 5 Interrupt Enable */
-#define DSI_IER0_AE6IE                 ((uint32_t)0x00000040U)               /*!< Acknowledge Error 6 Interrupt Enable */
-#define DSI_IER0_AE7IE                 ((uint32_t)0x00000080U)               /*!< Acknowledge Error 7 Interrupt Enable */
-#define DSI_IER0_AE8IE                 ((uint32_t)0x00000100U)               /*!< Acknowledge Error 8 Interrupt Enable */
-#define DSI_IER0_AE9IE                 ((uint32_t)0x00000200U)               /*!< Acknowledge Error 9 Interrupt Enable */
-#define DSI_IER0_AE10IE                ((uint32_t)0x00000400U)               /*!< Acknowledge Error 10 Interrupt Enable */
-#define DSI_IER0_AE11IE                ((uint32_t)0x00000800U)               /*!< Acknowledge Error 11 Interrupt Enable */
-#define DSI_IER0_AE12IE                ((uint32_t)0x00001000U)               /*!< Acknowledge Error 12 Interrupt Enable */
-#define DSI_IER0_AE13IE                ((uint32_t)0x00002000U)               /*!< Acknowledge Error 13 Interrupt Enable */
-#define DSI_IER0_AE14IE                ((uint32_t)0x00004000U)               /*!< Acknowledge Error 14 Interrupt Enable */
-#define DSI_IER0_AE15IE                ((uint32_t)0x00008000U)               /*!< Acknowledge Error 15 Interrupt Enable */
-#define DSI_IER0_PE0IE                 ((uint32_t)0x00010000U)               /*!< PHY Error 0 Interrupt Enable */
-#define DSI_IER0_PE1IE                 ((uint32_t)0x00020000U)               /*!< PHY Error 1 Interrupt Enable */
-#define DSI_IER0_PE2IE                 ((uint32_t)0x00040000U)               /*!< PHY Error 2 Interrupt Enable */
-#define DSI_IER0_PE3IE                 ((uint32_t)0x00080000U)               /*!< PHY Error 3 Interrupt Enable */
-#define DSI_IER0_PE4IE                 ((uint32_t)0x00100000U)               /*!< PHY Error 4 Interrupt Enable */
+#define DSI_IER0_AE0IE                 0x00000001U               /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE                 0x00000002U               /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE                 0x00000004U               /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE                 0x00000008U               /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE                 0x00000010U               /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE                 0x00000020U               /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE                 0x00000040U               /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE                 0x00000080U               /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE                 0x00000100U               /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE                 0x00000200U               /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE                0x00000400U               /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE                0x00000800U               /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE                0x00001000U               /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE                0x00002000U               /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE                0x00004000U               /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE                0x00008000U               /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE                 0x00010000U               /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE                 0x00020000U               /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE                 0x00040000U               /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE                 0x00080000U               /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE                 0x00100000U               /*!< PHY Error 4 Interrupt Enable */
 
 /*******************  Bit definition for DSI_IER1 register  ***************/
-#define DSI_IER1_TOHSTXIE              ((uint32_t)0x00000001U)               /*!< Timeout High-Speed Transmission Interrupt Enable */
-#define DSI_IER1_TOLPRXIE              ((uint32_t)0x00000002U)               /*!< Timeout Low-Power Reception Interrupt Enable */
-#define DSI_IER1_ECCSEIE               ((uint32_t)0x00000004U)               /*!< ECC Single-bit Error Interrupt Enable */
-#define DSI_IER1_ECCMEIE               ((uint32_t)0x00000008U)               /*!< ECC Multi-bit Error Interrupt Enable */
-#define DSI_IER1_CRCEIE                ((uint32_t)0x00000010U)               /*!< CRC Error Interrupt Enable */
-#define DSI_IER1_PSEIE                 ((uint32_t)0x00000020U)               /*!< Packet Size Error Interrupt Enable */
-#define DSI_IER1_EOTPEIE               ((uint32_t)0x00000040U)               /*!< EoTp Error Interrupt Enable */
-#define DSI_IER1_LPWREIE               ((uint32_t)0x00000080U)               /*!< LTDC Payload Write Error Interrupt Enable */
-#define DSI_IER1_GCWREIE               ((uint32_t)0x00000100U)               /*!< Generic Command Write Error Interrupt Enable */
-#define DSI_IER1_GPWREIE               ((uint32_t)0x00000200U)               /*!< Generic Payload Write Error Interrupt Enable */
-#define DSI_IER1_GPTXEIE               ((uint32_t)0x00000400U)               /*!< Generic Payload Transmit Error Interrupt Enable */
-#define DSI_IER1_GPRDEIE               ((uint32_t)0x00000800U)               /*!< Generic Payload Read Error Interrupt Enable */
-#define DSI_IER1_GPRXEIE               ((uint32_t)0x00001000U)               /*!< Generic Payload Receive Error Interrupt Enable */
+#define DSI_IER1_TOHSTXIE              0x00000001U               /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE              0x00000002U               /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE               0x00000004U               /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE               0x00000008U               /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE                0x00000010U               /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE                 0x00000020U               /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE               0x00000040U               /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE               0x00000080U               /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE               0x00000100U               /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE               0x00000200U               /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE               0x00000400U               /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE               0x00000800U               /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE               0x00001000U               /*!< Generic Payload Receive Error Interrupt Enable */
 
 /*******************  Bit definition for DSI_FIR0 register  ***************/
-#define DSI_FIR0_FAE0                  ((uint32_t)0x00000001U)               /*!< Force Acknowledge Error 0 */
-#define DSI_FIR0_FAE1                  ((uint32_t)0x00000002U)               /*!< Force Acknowledge Error 1 */
-#define DSI_FIR0_FAE2                  ((uint32_t)0x00000004U)               /*!< Force Acknowledge Error 2 */
-#define DSI_FIR0_FAE3                  ((uint32_t)0x00000008U)               /*!< Force Acknowledge Error 3 */
-#define DSI_FIR0_FAE4                  ((uint32_t)0x00000010U)               /*!< Force Acknowledge Error 4 */
-#define DSI_FIR0_FAE5                  ((uint32_t)0x00000020U)               /*!< Force Acknowledge Error 5 */
-#define DSI_FIR0_FAE6                  ((uint32_t)0x00000040U)               /*!< Force Acknowledge Error 6 */
-#define DSI_FIR0_FAE7                  ((uint32_t)0x00000080U)               /*!< Force Acknowledge Error 7 */
-#define DSI_FIR0_FAE8                  ((uint32_t)0x00000100U)               /*!< Force Acknowledge Error 8 */
-#define DSI_FIR0_FAE9                  ((uint32_t)0x00000200U)               /*!< Force Acknowledge Error 9 */
-#define DSI_FIR0_FAE10                 ((uint32_t)0x00000400U)               /*!< Force Acknowledge Error 10 */
-#define DSI_FIR0_FAE11                 ((uint32_t)0x00000800U)               /*!< Force Acknowledge Error 11 */
-#define DSI_FIR0_FAE12                 ((uint32_t)0x00001000U)               /*!< Force Acknowledge Error 12 */
-#define DSI_FIR0_FAE13                 ((uint32_t)0x00002000U)               /*!< Force Acknowledge Error 13 */
-#define DSI_FIR0_FAE14                 ((uint32_t)0x00004000U)               /*!< Force Acknowledge Error 14 */
-#define DSI_FIR0_FAE15                 ((uint32_t)0x00008000U)               /*!< Force Acknowledge Error 15 */
-#define DSI_FIR0_FPE0                  ((uint32_t)0x00010000U)               /*!< Force PHY Error 0 */
-#define DSI_FIR0_FPE1                  ((uint32_t)0x00020000U)               /*!< Force PHY Error 1 */
-#define DSI_FIR0_FPE2                  ((uint32_t)0x00040000U)               /*!< Force PHY Error 2 */
-#define DSI_FIR0_FPE3                  ((uint32_t)0x00080000U)               /*!< Force PHY Error 3 */
-#define DSI_FIR0_FPE4                  ((uint32_t)0x00100000U)               /*!< Force PHY Error 4 */
+#define DSI_FIR0_FAE0                  0x00000001U               /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1                  0x00000002U               /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2                  0x00000004U               /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3                  0x00000008U               /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4                  0x00000010U               /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5                  0x00000020U               /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6                  0x00000040U               /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7                  0x00000080U               /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8                  0x00000100U               /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9                  0x00000200U               /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10                 0x00000400U               /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11                 0x00000800U               /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12                 0x00001000U               /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13                 0x00002000U               /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14                 0x00004000U               /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15                 0x00008000U               /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0                  0x00010000U               /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1                  0x00020000U               /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2                  0x00040000U               /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3                  0x00080000U               /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4                  0x00100000U               /*!< Force PHY Error 4 */
 
 /*******************  Bit definition for DSI_FIR1 register  ***************/
-#define DSI_FIR1_FTOHSTX               ((uint32_t)0x00000001U)               /*!< Force Timeout High-Speed Transmission */
-#define DSI_FIR1_FTOLPRX               ((uint32_t)0x00000002U)               /*!< Force Timeout Low-Power Reception */
-#define DSI_FIR1_FECCSE                ((uint32_t)0x00000004U)               /*!< Force ECC Single-bit Error */
-#define DSI_FIR1_FECCME                ((uint32_t)0x00000008U)               /*!< Force ECC Multi-bit Error */
-#define DSI_FIR1_FCRCE                 ((uint32_t)0x00000010U)               /*!< Force CRC Error */
-#define DSI_FIR1_FPSE                  ((uint32_t)0x00000020U)               /*!< Force Packet Size Error */
-#define DSI_FIR1_FEOTPE                ((uint32_t)0x00000040U)               /*!< Force EoTp Error */
-#define DSI_FIR1_FLPWRE                ((uint32_t)0x00000080U)               /*!< Force LTDC Payload Write Error */
-#define DSI_FIR1_FGCWRE                ((uint32_t)0x00000100U)               /*!< Force Generic Command Write Error */
-#define DSI_FIR1_FGPWRE                ((uint32_t)0x00000200U)               /*!< Force Generic Payload Write Error */
-#define DSI_FIR1_FGPTXE                ((uint32_t)0x00000400U)               /*!< Force Generic Payload Transmit Error */
-#define DSI_FIR1_FGPRDE                ((uint32_t)0x00000800U)               /*!< Force Generic Payload Read Error */
-#define DSI_FIR1_FGPRXE                ((uint32_t)0x00001000U)               /*!< Force Generic Payload Receive Error */
+#define DSI_FIR1_FTOHSTX               0x00000001U               /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX               0x00000002U               /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE                0x00000004U               /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME                0x00000008U               /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE                 0x00000010U               /*!< Force CRC Error */
+#define DSI_FIR1_FPSE                  0x00000020U               /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE                0x00000040U               /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE                0x00000080U               /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE                0x00000100U               /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE                0x00000200U               /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE                0x00000400U               /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE                0x00000800U               /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE                0x00001000U               /*!< Force Generic Payload Receive Error */
 
 /*******************  Bit definition for DSI_VSCR register  ***************/
-#define DSI_VSCR_EN                    ((uint32_t)0x00000001U)               /*!< Enable */
-#define DSI_VSCR_UR                    ((uint32_t)0x00000100U)               /*!< Update Register */
+#define DSI_VSCR_EN                    0x00000001U               /*!< Enable */
+#define DSI_VSCR_UR                    0x00000100U               /*!< Update Register */
 
 /*******************  Bit definition for DSI_LCVCIDR register  ************/
-#define DSI_LCVCIDR_VCID               ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
-#define DSI_LCVCIDR_VCID0              ((uint32_t)0x00000001U)
-#define DSI_LCVCIDR_VCID1              ((uint32_t)0x00000002U)
+#define DSI_LCVCIDR_VCID               0x00000003U               /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0              0x00000001U
+#define DSI_LCVCIDR_VCID1              0x00000002U
 
 /*******************  Bit definition for DSI_LCCCR register  **************/
-#define DSI_LCCCR_COLC                 ((uint32_t)0x0000000FU)               /*!< Color Coding */
-#define DSI_LCCCR_COLC0                ((uint32_t)0x00000001U)
-#define DSI_LCCCR_COLC1                ((uint32_t)0x00000002U)
-#define DSI_LCCCR_COLC2                ((uint32_t)0x00000004U)
-#define DSI_LCCCR_COLC3                ((uint32_t)0x00000008U)
+#define DSI_LCCCR_COLC                 0x0000000FU               /*!< Color Coding */
+#define DSI_LCCCR_COLC0                0x00000001U
+#define DSI_LCCCR_COLC1                0x00000002U
+#define DSI_LCCCR_COLC2                0x00000004U
+#define DSI_LCCCR_COLC3                0x00000008U
 
-#define DSI_LCCCR_LPE                  ((uint32_t)0x00000100U)               /*!< Loosely Packed Enable */
+#define DSI_LCCCR_LPE                  0x00000100U               /*!< Loosely Packed Enable */
 
 /*******************  Bit definition for DSI_LPMCCR register  *************/
-#define DSI_LPMCCR_VLPSIZE             ((uint32_t)0x000000FFU)               /*!< VACT Largest Packet Size */
-#define DSI_LPMCCR_VLPSIZE0            ((uint32_t)0x00000001U)
-#define DSI_LPMCCR_VLPSIZE1            ((uint32_t)0x00000002U)
-#define DSI_LPMCCR_VLPSIZE2            ((uint32_t)0x00000004U)
-#define DSI_LPMCCR_VLPSIZE3            ((uint32_t)0x00000008U)
-#define DSI_LPMCCR_VLPSIZE4            ((uint32_t)0x00000010U)
-#define DSI_LPMCCR_VLPSIZE5            ((uint32_t)0x00000020U)
-#define DSI_LPMCCR_VLPSIZE6            ((uint32_t)0x00000040U)
-#define DSI_LPMCCR_VLPSIZE7            ((uint32_t)0x00000080U)
+#define DSI_LPMCCR_VLPSIZE             0x000000FFU               /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0            0x00000001U
+#define DSI_LPMCCR_VLPSIZE1            0x00000002U
+#define DSI_LPMCCR_VLPSIZE2            0x00000004U
+#define DSI_LPMCCR_VLPSIZE3            0x00000008U
+#define DSI_LPMCCR_VLPSIZE4            0x00000010U
+#define DSI_LPMCCR_VLPSIZE5            0x00000020U
+#define DSI_LPMCCR_VLPSIZE6            0x00000040U
+#define DSI_LPMCCR_VLPSIZE7            0x00000080U
 
-#define DSI_LPMCCR_LPSIZE              ((uint32_t)0x00FF0000U)               /*!< Largest Packet Size */
-#define DSI_LPMCCR_LPSIZE0             ((uint32_t)0x00010000U)
-#define DSI_LPMCCR_LPSIZE1             ((uint32_t)0x00020000U)
-#define DSI_LPMCCR_LPSIZE2             ((uint32_t)0x00040000U)
-#define DSI_LPMCCR_LPSIZE3             ((uint32_t)0x00080000U)
-#define DSI_LPMCCR_LPSIZE4             ((uint32_t)0x00100000U)
-#define DSI_LPMCCR_LPSIZE5             ((uint32_t)0x00200000U)
-#define DSI_LPMCCR_LPSIZE6             ((uint32_t)0x00400000U)
-#define DSI_LPMCCR_LPSIZE7             ((uint32_t)0x00800000U)
+#define DSI_LPMCCR_LPSIZE              0x00FF0000U               /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0             0x00010000U
+#define DSI_LPMCCR_LPSIZE1             0x00020000U
+#define DSI_LPMCCR_LPSIZE2             0x00040000U
+#define DSI_LPMCCR_LPSIZE3             0x00080000U
+#define DSI_LPMCCR_LPSIZE4             0x00100000U
+#define DSI_LPMCCR_LPSIZE5             0x00200000U
+#define DSI_LPMCCR_LPSIZE6             0x00400000U
+#define DSI_LPMCCR_LPSIZE7             0x00800000U
 
 /*******************  Bit definition for DSI_VMCCR register  **************/
-#define DSI_VMCCR_VMT                  ((uint32_t)0x00000003U)               /*!< Video Mode Type */
-#define DSI_VMCCR_VMT0                 ((uint32_t)0x00000001U)
-#define DSI_VMCCR_VMT1                 ((uint32_t)0x00000002U)
+#define DSI_VMCCR_VMT                  0x00000003U               /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0                 0x00000001U
+#define DSI_VMCCR_VMT1                 0x00000002U
 
-#define DSI_VMCCR_LPVSAE               ((uint32_t)0x00000100U)               /*!< Low-power Vertical Sync time Enable */
-#define DSI_VMCCR_LPVBPE               ((uint32_t)0x00000200U)               /*!< Low-power Vertical Back-porch Enable */
-#define DSI_VMCCR_LPVFPE               ((uint32_t)0x00000400U)               /*!< Low-power Vertical Front-porch Enable */
-#define DSI_VMCCR_LPVAE                ((uint32_t)0x00000800U)               /*!< Low-power Vertical Active Enable */
-#define DSI_VMCCR_LPHBPE               ((uint32_t)0x00001000U)               /*!< Low-power Horizontal Back-porch Enable */
-#define DSI_VMCCR_LPHFE                ((uint32_t)0x00002000U)               /*!< Low-power Horizontal Front-porch Enable */
-#define DSI_VMCCR_FBTAAE               ((uint32_t)0x00004000U)               /*!< Frame BTA Acknowledge Enable */
-#define DSI_VMCCR_LPCE                 ((uint32_t)0x00008000U)               /*!< Low-power Command Enable */
+#define DSI_VMCCR_LPVSAE               0x00000100U               /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE               0x00000200U               /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE               0x00000400U               /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE                0x00000800U               /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE               0x00001000U               /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE                0x00002000U               /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE               0x00004000U               /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE                 0x00008000U               /*!< Low-power Command Enable */
 
 /*******************  Bit definition for DSI_VPCCR register  **************/
-#define DSI_VPCCR_VPSIZE               ((uint32_t)0x00003FFFU)               /*!< Video Packet Size */
-#define DSI_VPCCR_VPSIZE0              ((uint32_t)0x00000001U)
-#define DSI_VPCCR_VPSIZE1              ((uint32_t)0x00000002U)
-#define DSI_VPCCR_VPSIZE2              ((uint32_t)0x00000004U)
-#define DSI_VPCCR_VPSIZE3              ((uint32_t)0x00000008U)
-#define DSI_VPCCR_VPSIZE4              ((uint32_t)0x00000010U)
-#define DSI_VPCCR_VPSIZE5              ((uint32_t)0x00000020U)
-#define DSI_VPCCR_VPSIZE6              ((uint32_t)0x00000040U)
-#define DSI_VPCCR_VPSIZE7              ((uint32_t)0x00000080U)
-#define DSI_VPCCR_VPSIZE8              ((uint32_t)0x00000100U)
-#define DSI_VPCCR_VPSIZE9              ((uint32_t)0x00000200U)
-#define DSI_VPCCR_VPSIZE10             ((uint32_t)0x00000400U)
-#define DSI_VPCCR_VPSIZE11             ((uint32_t)0x00000800U)
-#define DSI_VPCCR_VPSIZE12             ((uint32_t)0x00001000U)
-#define DSI_VPCCR_VPSIZE13             ((uint32_t)0x00002000U)
+#define DSI_VPCCR_VPSIZE               0x00003FFFU               /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0              0x00000001U
+#define DSI_VPCCR_VPSIZE1              0x00000002U
+#define DSI_VPCCR_VPSIZE2              0x00000004U
+#define DSI_VPCCR_VPSIZE3              0x00000008U
+#define DSI_VPCCR_VPSIZE4              0x00000010U
+#define DSI_VPCCR_VPSIZE5              0x00000020U
+#define DSI_VPCCR_VPSIZE6              0x00000040U
+#define DSI_VPCCR_VPSIZE7              0x00000080U
+#define DSI_VPCCR_VPSIZE8              0x00000100U
+#define DSI_VPCCR_VPSIZE9              0x00000200U
+#define DSI_VPCCR_VPSIZE10             0x00000400U
+#define DSI_VPCCR_VPSIZE11             0x00000800U
+#define DSI_VPCCR_VPSIZE12             0x00001000U
+#define DSI_VPCCR_VPSIZE13             0x00002000U
 
 /*******************  Bit definition for DSI_VCCCR register  **************/
-#define DSI_VCCCR_NUMC                 ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
-#define DSI_VCCCR_NUMC0                ((uint32_t)0x00000001U)
-#define DSI_VCCCR_NUMC1                ((uint32_t)0x00000002U)
-#define DSI_VCCCR_NUMC2                ((uint32_t)0x00000004U)
-#define DSI_VCCCR_NUMC3                ((uint32_t)0x00000008U)
-#define DSI_VCCCR_NUMC4                ((uint32_t)0x00000010U)
-#define DSI_VCCCR_NUMC5                ((uint32_t)0x00000020U)
-#define DSI_VCCCR_NUMC6                ((uint32_t)0x00000040U)
-#define DSI_VCCCR_NUMC7                ((uint32_t)0x00000080U)
-#define DSI_VCCCR_NUMC8                ((uint32_t)0x00000100U)
-#define DSI_VCCCR_NUMC9                ((uint32_t)0x00000200U)
-#define DSI_VCCCR_NUMC10               ((uint32_t)0x00000400U)
-#define DSI_VCCCR_NUMC11               ((uint32_t)0x00000800U)
-#define DSI_VCCCR_NUMC12               ((uint32_t)0x00001000U)
+#define DSI_VCCCR_NUMC                 0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0                0x00000001U
+#define DSI_VCCCR_NUMC1                0x00000002U
+#define DSI_VCCCR_NUMC2                0x00000004U
+#define DSI_VCCCR_NUMC3                0x00000008U
+#define DSI_VCCCR_NUMC4                0x00000010U
+#define DSI_VCCCR_NUMC5                0x00000020U
+#define DSI_VCCCR_NUMC6                0x00000040U
+#define DSI_VCCCR_NUMC7                0x00000080U
+#define DSI_VCCCR_NUMC8                0x00000100U
+#define DSI_VCCCR_NUMC9                0x00000200U
+#define DSI_VCCCR_NUMC10               0x00000400U
+#define DSI_VCCCR_NUMC11               0x00000800U
+#define DSI_VCCCR_NUMC12               0x00001000U
 
 /*******************  Bit definition for DSI_VNPCCR register  *************/
-#define DSI_VNPCCR_NPSIZE              ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
-#define DSI_VNPCCR_NPSIZE0             ((uint32_t)0x00000001U)
-#define DSI_VNPCCR_NPSIZE1             ((uint32_t)0x00000002U)
-#define DSI_VNPCCR_NPSIZE2             ((uint32_t)0x00000004U)
-#define DSI_VNPCCR_NPSIZE3             ((uint32_t)0x00000008U)
-#define DSI_VNPCCR_NPSIZE4             ((uint32_t)0x00000010U)
-#define DSI_VNPCCR_NPSIZE5             ((uint32_t)0x00000020U)
-#define DSI_VNPCCR_NPSIZE6             ((uint32_t)0x00000040U)
-#define DSI_VNPCCR_NPSIZE7             ((uint32_t)0x00000080U)
-#define DSI_VNPCCR_NPSIZE8             ((uint32_t)0x00000100U)
-#define DSI_VNPCCR_NPSIZE9             ((uint32_t)0x00000200U)
-#define DSI_VNPCCR_NPSIZE10            ((uint32_t)0x00000400U)
-#define DSI_VNPCCR_NPSIZE11            ((uint32_t)0x00000800U)
-#define DSI_VNPCCR_NPSIZE12            ((uint32_t)0x00001000U)
+#define DSI_VNPCCR_NPSIZE              0x00001FFFU               /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0             0x00000001U
+#define DSI_VNPCCR_NPSIZE1             0x00000002U
+#define DSI_VNPCCR_NPSIZE2             0x00000004U
+#define DSI_VNPCCR_NPSIZE3             0x00000008U
+#define DSI_VNPCCR_NPSIZE4             0x00000010U
+#define DSI_VNPCCR_NPSIZE5             0x00000020U
+#define DSI_VNPCCR_NPSIZE6             0x00000040U
+#define DSI_VNPCCR_NPSIZE7             0x00000080U
+#define DSI_VNPCCR_NPSIZE8             0x00000100U
+#define DSI_VNPCCR_NPSIZE9             0x00000200U
+#define DSI_VNPCCR_NPSIZE10            0x00000400U
+#define DSI_VNPCCR_NPSIZE11            0x00000800U
+#define DSI_VNPCCR_NPSIZE12            0x00001000U
 
 /*******************  Bit definition for DSI_VHSACCR register  ************/
-#define DSI_VHSACCR_HSA                ((uint32_t)0x00000FFFU)               /*!< Horizontal Synchronism Active duration */
-#define DSI_VHSACCR_HSA0               ((uint32_t)0x00000001U)
-#define DSI_VHSACCR_HSA1               ((uint32_t)0x00000002U)
-#define DSI_VHSACCR_HSA2               ((uint32_t)0x00000004U)
-#define DSI_VHSACCR_HSA3               ((uint32_t)0x00000008U)
-#define DSI_VHSACCR_HSA4               ((uint32_t)0x00000010U)
-#define DSI_VHSACCR_HSA5               ((uint32_t)0x00000020U)
-#define DSI_VHSACCR_HSA6               ((uint32_t)0x00000040U)
-#define DSI_VHSACCR_HSA7               ((uint32_t)0x00000080U)
-#define DSI_VHSACCR_HSA8               ((uint32_t)0x00000100U)
-#define DSI_VHSACCR_HSA9               ((uint32_t)0x00000200U)
-#define DSI_VHSACCR_HSA10              ((uint32_t)0x00000400U)
-#define DSI_VHSACCR_HSA11              ((uint32_t)0x00000800U)
+#define DSI_VHSACCR_HSA                0x00000FFFU               /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0               0x00000001U
+#define DSI_VHSACCR_HSA1               0x00000002U
+#define DSI_VHSACCR_HSA2               0x00000004U
+#define DSI_VHSACCR_HSA3               0x00000008U
+#define DSI_VHSACCR_HSA4               0x00000010U
+#define DSI_VHSACCR_HSA5               0x00000020U
+#define DSI_VHSACCR_HSA6               0x00000040U
+#define DSI_VHSACCR_HSA7               0x00000080U
+#define DSI_VHSACCR_HSA8               0x00000100U
+#define DSI_VHSACCR_HSA9               0x00000200U
+#define DSI_VHSACCR_HSA10              0x00000400U
+#define DSI_VHSACCR_HSA11              0x00000800U
 
 /*******************  Bit definition for DSI_VHBPCCR register  ************/
-#define DSI_VHBPCCR_HBP                ((uint32_t)0x00000FFFU)               /*!< Horizontal Back-Porch duration */
-#define DSI_VHBPCCR_HBP0               ((uint32_t)0x00000001U)
-#define DSI_VHBPCCR_HBP1               ((uint32_t)0x00000002U)
-#define DSI_VHBPCCR_HBP2               ((uint32_t)0x00000004U)
-#define DSI_VHBPCCR_HBP3               ((uint32_t)0x00000008U)
-#define DSI_VHBPCCR_HBP4               ((uint32_t)0x00000010U)
-#define DSI_VHBPCCR_HBP5               ((uint32_t)0x00000020U)
-#define DSI_VHBPCCR_HBP6               ((uint32_t)0x00000040U)
-#define DSI_VHBPCCR_HBP7               ((uint32_t)0x00000080U)
-#define DSI_VHBPCCR_HBP8               ((uint32_t)0x00000100U)
-#define DSI_VHBPCCR_HBP9               ((uint32_t)0x00000200U)
-#define DSI_VHBPCCR_HBP10              ((uint32_t)0x00000400U)
-#define DSI_VHBPCCR_HBP11              ((uint32_t)0x00000800U)
+#define DSI_VHBPCCR_HBP                0x00000FFFU               /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0               0x00000001U
+#define DSI_VHBPCCR_HBP1               0x00000002U
+#define DSI_VHBPCCR_HBP2               0x00000004U
+#define DSI_VHBPCCR_HBP3               0x00000008U
+#define DSI_VHBPCCR_HBP4               0x00000010U
+#define DSI_VHBPCCR_HBP5               0x00000020U
+#define DSI_VHBPCCR_HBP6               0x00000040U
+#define DSI_VHBPCCR_HBP7               0x00000080U
+#define DSI_VHBPCCR_HBP8               0x00000100U
+#define DSI_VHBPCCR_HBP9               0x00000200U
+#define DSI_VHBPCCR_HBP10              0x00000400U
+#define DSI_VHBPCCR_HBP11              0x00000800U
 
 /*******************  Bit definition for DSI_VLCCR register  **************/
-#define DSI_VLCCR_HLINE                ((uint32_t)0x00007FFFU)               /*!< Horizontal Line duration */
-#define DSI_VLCCR_HLINE0               ((uint32_t)0x00000001U)
-#define DSI_VLCCR_HLINE1               ((uint32_t)0x00000002U)
-#define DSI_VLCCR_HLINE2               ((uint32_t)0x00000004U)
-#define DSI_VLCCR_HLINE3               ((uint32_t)0x00000008U)
-#define DSI_VLCCR_HLINE4               ((uint32_t)0x00000010U)
-#define DSI_VLCCR_HLINE5               ((uint32_t)0x00000020U)
-#define DSI_VLCCR_HLINE6               ((uint32_t)0x00000040U)
-#define DSI_VLCCR_HLINE7               ((uint32_t)0x00000080U)
-#define DSI_VLCCR_HLINE8               ((uint32_t)0x00000100U)
-#define DSI_VLCCR_HLINE9               ((uint32_t)0x00000200U)
-#define DSI_VLCCR_HLINE10              ((uint32_t)0x00000400U)
-#define DSI_VLCCR_HLINE11              ((uint32_t)0x00000800U)
-#define DSI_VLCCR_HLINE12              ((uint32_t)0x00001000U)
-#define DSI_VLCCR_HLINE13              ((uint32_t)0x00002000U)
-#define DSI_VLCCR_HLINE14              ((uint32_t)0x00004000U)
+#define DSI_VLCCR_HLINE                0x00007FFFU               /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0               0x00000001U
+#define DSI_VLCCR_HLINE1               0x00000002U
+#define DSI_VLCCR_HLINE2               0x00000004U
+#define DSI_VLCCR_HLINE3               0x00000008U
+#define DSI_VLCCR_HLINE4               0x00000010U
+#define DSI_VLCCR_HLINE5               0x00000020U
+#define DSI_VLCCR_HLINE6               0x00000040U
+#define DSI_VLCCR_HLINE7               0x00000080U
+#define DSI_VLCCR_HLINE8               0x00000100U
+#define DSI_VLCCR_HLINE9               0x00000200U
+#define DSI_VLCCR_HLINE10              0x00000400U
+#define DSI_VLCCR_HLINE11              0x00000800U
+#define DSI_VLCCR_HLINE12              0x00001000U
+#define DSI_VLCCR_HLINE13              0x00002000U
+#define DSI_VLCCR_HLINE14              0x00004000U
 
 /*******************  Bit definition for DSI_VVSACCR register  ***************/
-#define DSI_VVSACCR_VSA                   ((uint32_t)0x000003FFU)               /*!< Vertical Synchronism Active duration */
-#define DSI_VVSACCR_VSA0                  ((uint32_t)0x00000001U)
-#define DSI_VVSACCR_VSA1                  ((uint32_t)0x00000002U)
-#define DSI_VVSACCR_VSA2                  ((uint32_t)0x00000004U)
-#define DSI_VVSACCR_VSA3                  ((uint32_t)0x00000008U)
-#define DSI_VVSACCR_VSA4                  ((uint32_t)0x00000010U)
-#define DSI_VVSACCR_VSA5                  ((uint32_t)0x00000020U)
-#define DSI_VVSACCR_VSA6                  ((uint32_t)0x00000040U)
-#define DSI_VVSACCR_VSA7                  ((uint32_t)0x00000080U)
-#define DSI_VVSACCR_VSA8                  ((uint32_t)0x00000100U)
-#define DSI_VVSACCR_VSA9                  ((uint32_t)0x00000200U)
+#define DSI_VVSACCR_VSA                   0x000003FFU               /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0                  0x00000001U
+#define DSI_VVSACCR_VSA1                  0x00000002U
+#define DSI_VVSACCR_VSA2                  0x00000004U
+#define DSI_VVSACCR_VSA3                  0x00000008U
+#define DSI_VVSACCR_VSA4                  0x00000010U
+#define DSI_VVSACCR_VSA5                  0x00000020U
+#define DSI_VVSACCR_VSA6                  0x00000040U
+#define DSI_VVSACCR_VSA7                  0x00000080U
+#define DSI_VVSACCR_VSA8                  0x00000100U
+#define DSI_VVSACCR_VSA9                  0x00000200U
 
 /*******************  Bit definition for DSI_VVBPCCR register  ************/
-#define DSI_VVBPCCR_VBP                ((uint32_t)0x000003FFU)               /*!< Vertical Back-Porch duration */
-#define DSI_VVBPCCR_VBP0               ((uint32_t)0x00000001U)
-#define DSI_VVBPCCR_VBP1               ((uint32_t)0x00000002U)
-#define DSI_VVBPCCR_VBP2               ((uint32_t)0x00000004U)
-#define DSI_VVBPCCR_VBP3               ((uint32_t)0x00000008U)
-#define DSI_VVBPCCR_VBP4               ((uint32_t)0x00000010U)
-#define DSI_VVBPCCR_VBP5               ((uint32_t)0x00000020U)
-#define DSI_VVBPCCR_VBP6               ((uint32_t)0x00000040U)
-#define DSI_VVBPCCR_VBP7               ((uint32_t)0x00000080U)
-#define DSI_VVBPCCR_VBP8               ((uint32_t)0x00000100U)
-#define DSI_VVBPCCR_VBP9               ((uint32_t)0x00000200U)
+#define DSI_VVBPCCR_VBP                0x000003FFU               /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0               0x00000001U
+#define DSI_VVBPCCR_VBP1               0x00000002U
+#define DSI_VVBPCCR_VBP2               0x00000004U
+#define DSI_VVBPCCR_VBP3               0x00000008U
+#define DSI_VVBPCCR_VBP4               0x00000010U
+#define DSI_VVBPCCR_VBP5               0x00000020U
+#define DSI_VVBPCCR_VBP6               0x00000040U
+#define DSI_VVBPCCR_VBP7               0x00000080U
+#define DSI_VVBPCCR_VBP8               0x00000100U
+#define DSI_VVBPCCR_VBP9               0x00000200U
 
 /*******************  Bit definition for DSI_VVFPCCR register  ************/
-#define DSI_VVFPCCR_VFP                ((uint32_t)0x000003FFU)               /*!< Vertical Front-Porch duration */
-#define DSI_VVFPCCR_VFP0               ((uint32_t)0x00000001U)
-#define DSI_VVFPCCR_VFP1               ((uint32_t)0x00000002U)
-#define DSI_VVFPCCR_VFP2               ((uint32_t)0x00000004U)
-#define DSI_VVFPCCR_VFP3               ((uint32_t)0x00000008U)
-#define DSI_VVFPCCR_VFP4               ((uint32_t)0x00000010U)
-#define DSI_VVFPCCR_VFP5               ((uint32_t)0x00000020U)
-#define DSI_VVFPCCR_VFP6               ((uint32_t)0x00000040U)
-#define DSI_VVFPCCR_VFP7               ((uint32_t)0x00000080U)
-#define DSI_VVFPCCR_VFP8               ((uint32_t)0x00000100U)
-#define DSI_VVFPCCR_VFP9               ((uint32_t)0x00000200U)
+#define DSI_VVFPCCR_VFP                0x000003FFU               /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0               0x00000001U
+#define DSI_VVFPCCR_VFP1               0x00000002U
+#define DSI_VVFPCCR_VFP2               0x00000004U
+#define DSI_VVFPCCR_VFP3               0x00000008U
+#define DSI_VVFPCCR_VFP4               0x00000010U
+#define DSI_VVFPCCR_VFP5               0x00000020U
+#define DSI_VVFPCCR_VFP6               0x00000040U
+#define DSI_VVFPCCR_VFP7               0x00000080U
+#define DSI_VVFPCCR_VFP8               0x00000100U
+#define DSI_VVFPCCR_VFP9               0x00000200U
 
 /*******************  Bit definition for DSI_VVACCR register  *************/
-#define DSI_VVACCR_VA                  ((uint32_t)0x00003FFFU)               /*!< Vertical Active duration */
-#define DSI_VVACCR_VA0                 ((uint32_t)0x00000001U)
-#define DSI_VVACCR_VA1                 ((uint32_t)0x00000002U)
-#define DSI_VVACCR_VA2                 ((uint32_t)0x00000004U)
-#define DSI_VVACCR_VA3                 ((uint32_t)0x00000008U)
-#define DSI_VVACCR_VA4                 ((uint32_t)0x00000010U)
-#define DSI_VVACCR_VA5                 ((uint32_t)0x00000020U)
-#define DSI_VVACCR_VA6                 ((uint32_t)0x00000040U)
-#define DSI_VVACCR_VA7                 ((uint32_t)0x00000080U)
-#define DSI_VVACCR_VA8                 ((uint32_t)0x00000100U)
-#define DSI_VVACCR_VA9                 ((uint32_t)0x00000200U)
-#define DSI_VVACCR_VA10                ((uint32_t)0x00000400U)
-#define DSI_VVACCR_VA11                ((uint32_t)0x00000800U)
-#define DSI_VVACCR_VA12                ((uint32_t)0x00001000U)
-#define DSI_VVACCR_VA13                ((uint32_t)0x00002000U)
+#define DSI_VVACCR_VA                  0x00003FFFU               /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0                 0x00000001U
+#define DSI_VVACCR_VA1                 0x00000002U
+#define DSI_VVACCR_VA2                 0x00000004U
+#define DSI_VVACCR_VA3                 0x00000008U
+#define DSI_VVACCR_VA4                 0x00000010U
+#define DSI_VVACCR_VA5                 0x00000020U
+#define DSI_VVACCR_VA6                 0x00000040U
+#define DSI_VVACCR_VA7                 0x00000080U
+#define DSI_VVACCR_VA8                 0x00000100U
+#define DSI_VVACCR_VA9                 0x00000200U
+#define DSI_VVACCR_VA10                0x00000400U
+#define DSI_VVACCR_VA11                0x00000800U
+#define DSI_VVACCR_VA12                0x00001000U
+#define DSI_VVACCR_VA13                0x00002000U
 
 /*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                  ((uint32_t)0x00000003U)               /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                 ((uint32_t)0x00000001U)
-#define DSI_TDCCR_3DM1                 ((uint32_t)0x00000002U)
+#define DSI_TDCCR_3DM                  0x00000003U               /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                 0x00000001U
+#define DSI_TDCCR_3DM1                 0x00000002U
 
-#define DSI_TDCCR_3DF                  ((uint32_t)0x0000000CU)               /*!< 3D Format */
-#define DSI_TDCCR_3DF0                 ((uint32_t)0x00000004U)
-#define DSI_TDCCR_3DF1                 ((uint32_t)0x00000008U)
+#define DSI_TDCCR_3DF                  0x0000000CU               /*!< 3D Format */
+#define DSI_TDCCR_3DF0                 0x00000004U
+#define DSI_TDCCR_3DF1                 0x00000008U
 
-#define DSI_TDCCR_SVS                  ((uint32_t)0x00000010U)               /*!< Second VSYNC */
-#define DSI_TDCCR_RF                   ((uint32_t)0x00000020U)               /*!< Right First */
-#define DSI_TDCCR_S3DC                 ((uint32_t)0x00010000U)               /*!< Send 3D Control */
+#define DSI_TDCCR_SVS                  0x00000010U               /*!< Second VSYNC */
+#define DSI_TDCCR_RF                   0x00000020U               /*!< Right First */
+#define DSI_TDCCR_S3DC                 0x00010000U               /*!< Send 3D Control */
 
 /*******************  Bit definition for DSI_WCFGR register  ***************/
-#define DSI_WCFGR_DSIM                   ((uint32_t)0x00000001U)              /*!< DSI Mode */
-#define DSI_WCFGR_COLMUX                 ((uint32_t)0x0000000EU)              /*!< Color Multiplexing */
-#define DSI_WCFGR_COLMUX0                ((uint32_t)0x00000002U)
-#define DSI_WCFGR_COLMUX1                ((uint32_t)0x00000004U)
-#define DSI_WCFGR_COLMUX2                ((uint32_t)0x00000008U)
+#define DSI_WCFGR_DSIM                   0x00000001U              /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX                 0x0000000EU              /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0                0x00000002U
+#define DSI_WCFGR_COLMUX1                0x00000004U
+#define DSI_WCFGR_COLMUX2                0x00000008U
 
-#define DSI_WCFGR_TESRC                  ((uint32_t)0x00000010U)              /*!< Tearing Effect Source */
-#define DSI_WCFGR_TEPOL                  ((uint32_t)0x00000020U)              /*!< Tearing Effect Polarity */
-#define DSI_WCFGR_AR                     ((uint32_t)0x00000040U)              /*!< Automatic Refresh */
-#define DSI_WCFGR_VSPOL                  ((uint32_t)0x00000080U)              /*!< VSync Polarity */
+#define DSI_WCFGR_TESRC                  0x00000010U              /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL                  0x00000020U              /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR                     0x00000040U              /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL                  0x00000080U              /*!< VSync Polarity */
 
 /*******************  Bit definition for DSI_WCR register  *****************/
-#define DSI_WCR_COLM                     ((uint32_t)0x00000001U)              /*!< Color Mode */
-#define DSI_WCR_SHTDN                    ((uint32_t)0x00000002U)              /*!< Shutdown */
-#define DSI_WCR_LTDCEN                   ((uint32_t)0x00000004U)              /*!< LTDC Enable */
-#define DSI_WCR_DSIEN                    ((uint32_t)0x00000008U)              /*!< DSI Enable */
+#define DSI_WCR_COLM                     0x00000001U              /*!< Color Mode */
+#define DSI_WCR_SHTDN                    0x00000002U              /*!< Shutdown */
+#define DSI_WCR_LTDCEN                   0x00000004U              /*!< LTDC Enable */
+#define DSI_WCR_DSIEN                    0x00000008U              /*!< DSI Enable */
 
 /*******************  Bit definition for DSI_WIER register  ****************/
-#define DSI_WIER_TEIE                    ((uint32_t)0x00000001U)              /*!< Tearing Effect Interrupt Enable */
-#define DSI_WIER_ERIE                    ((uint32_t)0x00000002U)              /*!< End of Refresh Interrupt Enable */
-#define DSI_WIER_PLLLIE                  ((uint32_t)0x00000200U)              /*!< PLL Lock Interrupt Enable */
-#define DSI_WIER_PLLUIE                  ((uint32_t)0x00000400U)              /*!< PLL Unlock Interrupt Enable */
-#define DSI_WIER_RRIE                    ((uint32_t)0x00002000U)              /*!< Regulator Ready Interrupt Enable */
+#define DSI_WIER_TEIE                    0x00000001U              /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE                    0x00000002U              /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE                  0x00000200U              /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE                  0x00000400U              /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE                    0x00002000U              /*!< Regulator Ready Interrupt Enable */
 
 /*******************  Bit definition for DSI_WISR register  ****************/
-#define DSI_WISR_TEIF                    ((uint32_t)0x00000001U)              /*!< Tearing Effect Interrupt Flag */
-#define DSI_WISR_ERIF                    ((uint32_t)0x00000002U)              /*!< End of Refresh Interrupt Flag */
-#define DSI_WISR_BUSY                    ((uint32_t)0x00000004U)              /*!< Busy Flag */
-#define DSI_WISR_PLLLS                   ((uint32_t)0x00000100U)              /*!< PLL Lock Status */
-#define DSI_WISR_PLLLIF                  ((uint32_t)0x00000200U)              /*!< PLL Lock Interrupt Flag */
-#define DSI_WISR_PLLUIF                  ((uint32_t)0x00000400U)              /*!< PLL Unlock Interrupt Flag */
-#define DSI_WISR_RRS                     ((uint32_t)0x00001000U)              /*!< Regulator Ready Flag */
-#define DSI_WISR_RRIF                    ((uint32_t)0x00002000U)              /*!< Regulator Ready Interrupt Flag */
+#define DSI_WISR_TEIF                    0x00000001U              /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF                    0x00000002U              /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY                    0x00000004U              /*!< Busy Flag */
+#define DSI_WISR_PLLLS                   0x00000100U              /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF                  0x00000200U              /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF                  0x00000400U              /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS                     0x00001000U              /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF                    0x00002000U              /*!< Regulator Ready Interrupt Flag */
 
 /*******************  Bit definition for DSI_WIFCR register  ***************/
-#define DSI_WIFCR_CTEIF                  ((uint32_t)0x00000001U)              /*!< Clear Tearing Effect Interrupt Flag */
-#define DSI_WIFCR_CERIF                  ((uint32_t)0x00000002U)              /*!< Clear End of Refresh Interrupt Flag */
-#define DSI_WIFCR_CPLLLIF                ((uint32_t)0x00000200U)              /*!< Clear PLL Lock Interrupt Flag */
-#define DSI_WIFCR_CPLLUIF                ((uint32_t)0x00000400U)              /*!< Clear PLL Unlock Interrupt Flag */
-#define DSI_WIFCR_CRRIF                  ((uint32_t)0x00002000U)              /*!< Clear Regulator Ready Interrupt Flag */
+#define DSI_WIFCR_CTEIF                  0x00000001U              /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF                  0x00000002U              /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF                0x00000200U              /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF                0x00000400U              /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF                  0x00002000U              /*!< Clear Regulator Ready Interrupt Flag */
 
 /*******************  Bit definition for DSI_WPCR0 register  ***************/
-#define DSI_WPCR0_UIX4                   ((uint32_t)0x0000003FU)              /*!< Unit Interval multiplied by 4 */
-#define DSI_WPCR0_UIX4_0                 ((uint32_t)0x00000001U)
-#define DSI_WPCR0_UIX4_1                 ((uint32_t)0x00000002U)
-#define DSI_WPCR0_UIX4_2                 ((uint32_t)0x00000004U)
-#define DSI_WPCR0_UIX4_3                 ((uint32_t)0x00000008U)
-#define DSI_WPCR0_UIX4_4                 ((uint32_t)0x00000010U)
-#define DSI_WPCR0_UIX4_5                 ((uint32_t)0x00000020U)
+#define DSI_WPCR0_UIX4                   0x0000003FU              /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0                 0x00000001U
+#define DSI_WPCR0_UIX4_1                 0x00000002U
+#define DSI_WPCR0_UIX4_2                 0x00000004U
+#define DSI_WPCR0_UIX4_3                 0x00000008U
+#define DSI_WPCR0_UIX4_4                 0x00000010U
+#define DSI_WPCR0_UIX4_5                 0x00000020U
 
-#define DSI_WPCR0_SWCL                   ((uint32_t)0x00000040U)              /*!< Swap pins on clock lane */
-#define DSI_WPCR0_SWDL0                  ((uint32_t)0x00000080U)              /*!< Swap pins on data lane 1 */
-#define DSI_WPCR0_SWDL1                  ((uint32_t)0x00000100U)              /*!< Swap pins on data lane 2 */
-#define DSI_WPCR0_HSICL                  ((uint32_t)0x00000200U)              /*!< Invert the high-speed data signal on clock lane */
-#define DSI_WPCR0_HSIDL0                 ((uint32_t)0x00000400U)              /*!< Invert the high-speed data signal on lane 1 */
-#define DSI_WPCR0_HSIDL1                 ((uint32_t)0x00000800U)              /*!< Invert the high-speed data signal on lane 2 */
-#define DSI_WPCR0_FTXSMCL                ((uint32_t)0x00001000U)              /*!< Force clock lane in TX stop mode */
-#define DSI_WPCR0_FTXSMDL                ((uint32_t)0x00002000U)              /*!< Force data lanes in TX stop mode */
-#define DSI_WPCR0_CDOFFDL                ((uint32_t)0x00004000U)              /*!< Contention detection OFF */
-#define DSI_WPCR0_TDDL                   ((uint32_t)0x00010000U)              /*!< Turn Disable Data Lanes */
-#define DSI_WPCR0_PDEN                   ((uint32_t)0x00040000U)              /*!< Pull-Down Enable */
-#define DSI_WPCR0_TCLKPREPEN             ((uint32_t)0x00080000U)              /*!< Timer for t-CLKPREP Enable */
-#define DSI_WPCR0_TCLKZEROEN             ((uint32_t)0x00100000U)              /*!< Timer for t-CLKZERO Enable */
-#define DSI_WPCR0_THSPREPEN              ((uint32_t)0x00200000U)              /*!< Timer for t-HSPREP Enable */
-#define DSI_WPCR0_THSTRAILEN             ((uint32_t)0x00400000U)              /*!< Timer for t-HSTRAIL Enable */
-#define DSI_WPCR0_THSZEROEN              ((uint32_t)0x00800000U)              /*!< Timer for t-HSZERO Enable */
-#define DSI_WPCR0_TLPXDEN                ((uint32_t)0x01000000U)              /*!< Timer for t-LPXD Enable */
-#define DSI_WPCR0_THSEXITEN              ((uint32_t)0x02000000U)              /*!< Timer for t-HSEXIT Enable */
-#define DSI_WPCR0_TLPXCEN                ((uint32_t)0x04000000U)              /*!< Timer for t-LPXC Enable */
-#define DSI_WPCR0_TCLKPOSTEN             ((uint32_t)0x08000000U)              /*!< Timer for t-CLKPOST Enable */
+#define DSI_WPCR0_SWCL                   0x00000040U              /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0                  0x00000080U              /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1                  0x00000100U              /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL                  0x00000200U              /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0                 0x00000400U              /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1                 0x00000800U              /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL                0x00001000U              /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL                0x00002000U              /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL                0x00004000U              /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL                   0x00010000U              /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN                   0x00040000U              /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN             0x00080000U              /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN             0x00100000U              /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN              0x00200000U              /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN             0x00400000U              /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN              0x00800000U              /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN                0x01000000U              /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN              0x02000000U              /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN                0x04000000U              /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN             0x08000000U              /*!< Timer for t-CLKPOST Enable */
 
 /*******************  Bit definition for DSI_WPCR1 register  ***************/
-#define DSI_WPCR1_HSTXDCL                ((uint32_t)0x00000003U)              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXDCL0               ((uint32_t)0x00000001U)
-#define DSI_WPCR1_HSTXDCL1               ((uint32_t)0x00000002U)
+#define DSI_WPCR1_HSTXDCL                0x00000003U              /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0               0x00000001U
+#define DSI_WPCR1_HSTXDCL1               0x00000002U
 
-#define DSI_WPCR1_HSTXDDL                ((uint32_t)0x0000000CU)              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXDDL0               ((uint32_t)0x00000004U)
-#define DSI_WPCR1_HSTXDDL1               ((uint32_t)0x00000008U)
+#define DSI_WPCR1_HSTXDDL                0x0000000CU              /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0               0x00000004U
+#define DSI_WPCR1_HSTXDDL1               0x00000008U
 
-#define DSI_WPCR1_LPSRCCL                ((uint32_t)0x000000C0U)              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
-#define DSI_WPCR1_LPSRCCL0               ((uint32_t)0x00000040U)
-#define DSI_WPCR1_LPSRCCL1               ((uint32_t)0x00000080U)
+#define DSI_WPCR1_LPSRCCL                0x000000C0U              /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0               0x00000040U
+#define DSI_WPCR1_LPSRCCL1               0x00000080U
 
-#define DSI_WPCR1_LPSRCDL                ((uint32_t)0x00000300U)              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
-#define DSI_WPCR1_LPSRCDL0               ((uint32_t)0x00000100U)
-#define DSI_WPCR1_LPSRCDL1               ((uint32_t)0x00000200U)
+#define DSI_WPCR1_LPSRCDL                0x00000300U              /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0               0x00000100U
+#define DSI_WPCR1_LPSRCDL1               0x00000200U
 
-#define DSI_WPCR1_SDDC                   ((uint32_t)0x00001000U)              /*!< SDD Control */
+#define DSI_WPCR1_SDDC                   0x00001000U              /*!< SDD Control */
 
-#define DSI_WPCR1_LPRXVCDL               ((uint32_t)0x0000C000U)              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
-#define DSI_WPCR1_LPRXVCDL0              ((uint32_t)0x00004000U)
-#define DSI_WPCR1_LPRXVCDL1              ((uint32_t)0x00008000U)
+#define DSI_WPCR1_LPRXVCDL               0x0000C000U              /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0              0x00004000U
+#define DSI_WPCR1_LPRXVCDL1              0x00008000U
 
-#define DSI_WPCR1_HSTXSRCCL              ((uint32_t)0x00030000U)              /*!< High-Speed Transmission Delay on Clock Lane */
-#define DSI_WPCR1_HSTXSRCCL0             ((uint32_t)0x00010000U)
-#define DSI_WPCR1_HSTXSRCCL1             ((uint32_t)0x00020000U)
+#define DSI_WPCR1_HSTXSRCCL              0x00030000U              /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0             0x00010000U
+#define DSI_WPCR1_HSTXSRCCL1             0x00020000U
 
-#define DSI_WPCR1_HSTXSRCDL              ((uint32_t)0x000C0000U)              /*!< High-Speed Transmission Delay on Data Lane */
-#define DSI_WPCR1_HSTXSRCDL0             ((uint32_t)0x00040000U)
-#define DSI_WPCR1_HSTXSRCDL1             ((uint32_t)0x00080000U)
+#define DSI_WPCR1_HSTXSRCDL              0x000C0000U              /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0             0x00040000U
+#define DSI_WPCR1_HSTXSRCDL1             0x00080000U
 
-#define DSI_WPCR1_FLPRXLPM               ((uint32_t)0x00400000U)              /*!< Forces LP Receiver in Low-Power Mode */
+#define DSI_WPCR1_FLPRXLPM               0x00400000U              /*!< Forces LP Receiver in Low-Power Mode */
 
-#define DSI_WPCR1_LPRXFT                 ((uint32_t)0x06000000U)              /*!< Low-Power RX low-pass Filtering Tuning */
-#define DSI_WPCR1_LPRXFT0                ((uint32_t)0x02000000U)
-#define DSI_WPCR1_LPRXFT1                ((uint32_t)0x04000000U)
+#define DSI_WPCR1_LPRXFT                 0x06000000U              /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0                0x02000000U
+#define DSI_WPCR1_LPRXFT1                0x04000000U
 
 /*******************  Bit definition for DSI_WPCR2 register  ***************/
-#define DSI_WPCR2_TCLKPREP               ((uint32_t)0x000000FFU)              /*!< t-CLKPREP */
-#define DSI_WPCR2_TCLKPREP0              ((uint32_t)0x00000001U)
-#define DSI_WPCR2_TCLKPREP1              ((uint32_t)0x00000002U)
-#define DSI_WPCR2_TCLKPREP2              ((uint32_t)0x00000004U)
-#define DSI_WPCR2_TCLKPREP3              ((uint32_t)0x00000008U)
-#define DSI_WPCR2_TCLKPREP4              ((uint32_t)0x00000010U)
-#define DSI_WPCR2_TCLKPREP5              ((uint32_t)0x00000020U)
-#define DSI_WPCR2_TCLKPREP6              ((uint32_t)0x00000040U)
-#define DSI_WPCR2_TCLKPREP7              ((uint32_t)0x00000080U)
+#define DSI_WPCR2_TCLKPREP               0x000000FFU              /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0              0x00000001U
+#define DSI_WPCR2_TCLKPREP1              0x00000002U
+#define DSI_WPCR2_TCLKPREP2              0x00000004U
+#define DSI_WPCR2_TCLKPREP3              0x00000008U
+#define DSI_WPCR2_TCLKPREP4              0x00000010U
+#define DSI_WPCR2_TCLKPREP5              0x00000020U
+#define DSI_WPCR2_TCLKPREP6              0x00000040U
+#define DSI_WPCR2_TCLKPREP7              0x00000080U
 
-#define DSI_WPCR2_TCLKZERO               ((uint32_t)0x0000FF00U)              /*!< t-CLKZERO */
-#define DSI_WPCR2_TCLKZERO0              ((uint32_t)0x00000100U)
-#define DSI_WPCR2_TCLKZERO1              ((uint32_t)0x00000200U)
-#define DSI_WPCR2_TCLKZERO2              ((uint32_t)0x00000400U)
-#define DSI_WPCR2_TCLKZERO3              ((uint32_t)0x00000800U)
-#define DSI_WPCR2_TCLKZERO4              ((uint32_t)0x00001000U)
-#define DSI_WPCR2_TCLKZERO5              ((uint32_t)0x00002000U)
-#define DSI_WPCR2_TCLKZERO6              ((uint32_t)0x00004000U)
-#define DSI_WPCR2_TCLKZERO7              ((uint32_t)0x00008000U)
+#define DSI_WPCR2_TCLKZERO               0x0000FF00U              /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0              0x00000100U
+#define DSI_WPCR2_TCLKZERO1              0x00000200U
+#define DSI_WPCR2_TCLKZERO2              0x00000400U
+#define DSI_WPCR2_TCLKZERO3              0x00000800U
+#define DSI_WPCR2_TCLKZERO4              0x00001000U
+#define DSI_WPCR2_TCLKZERO5              0x00002000U
+#define DSI_WPCR2_TCLKZERO6              0x00004000U
+#define DSI_WPCR2_TCLKZERO7              0x00008000U
 
-#define DSI_WPCR2_THSPREP                ((uint32_t)0x00FF0000U)              /*!< t-HSPREP */
-#define DSI_WPCR2_THSPREP0               ((uint32_t)0x00010000U)
-#define DSI_WPCR2_THSPREP1               ((uint32_t)0x00020000U)
-#define DSI_WPCR2_THSPREP2               ((uint32_t)0x00040000U)
-#define DSI_WPCR2_THSPREP3               ((uint32_t)0x00080000U)
-#define DSI_WPCR2_THSPREP4               ((uint32_t)0x00100000U)
-#define DSI_WPCR2_THSPREP5               ((uint32_t)0x00200000U)
-#define DSI_WPCR2_THSPREP6               ((uint32_t)0x00400000U)
-#define DSI_WPCR2_THSPREP7               ((uint32_t)0x00800000U)
+#define DSI_WPCR2_THSPREP                0x00FF0000U              /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0               0x00010000U
+#define DSI_WPCR2_THSPREP1               0x00020000U
+#define DSI_WPCR2_THSPREP2               0x00040000U
+#define DSI_WPCR2_THSPREP3               0x00080000U
+#define DSI_WPCR2_THSPREP4               0x00100000U
+#define DSI_WPCR2_THSPREP5               0x00200000U
+#define DSI_WPCR2_THSPREP6               0x00400000U
+#define DSI_WPCR2_THSPREP7               0x00800000U
 
-#define DSI_WPCR2_THSTRAIL               ((uint32_t)0xFF000000U)              /*!< t-HSTRAIL */
-#define DSI_WPCR2_THSTRAIL0              ((uint32_t)0x01000000U)
-#define DSI_WPCR2_THSTRAIL1              ((uint32_t)0x02000000U)
-#define DSI_WPCR2_THSTRAIL2              ((uint32_t)0x04000000U)
-#define DSI_WPCR2_THSTRAIL3              ((uint32_t)0x08000000U)
-#define DSI_WPCR2_THSTRAIL4              ((uint32_t)0x10000000U)
-#define DSI_WPCR2_THSTRAIL5              ((uint32_t)0x20000000U)
-#define DSI_WPCR2_THSTRAIL6              ((uint32_t)0x40000000U)
-#define DSI_WPCR2_THSTRAIL7              ((uint32_t)0x80000000U)
+#define DSI_WPCR2_THSTRAIL               0xFF000000U              /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0              0x01000000U
+#define DSI_WPCR2_THSTRAIL1              0x02000000U
+#define DSI_WPCR2_THSTRAIL2              0x04000000U
+#define DSI_WPCR2_THSTRAIL3              0x08000000U
+#define DSI_WPCR2_THSTRAIL4              0x10000000U
+#define DSI_WPCR2_THSTRAIL5              0x20000000U
+#define DSI_WPCR2_THSTRAIL6              0x40000000U
+#define DSI_WPCR2_THSTRAIL7              0x80000000U
 
 /*******************  Bit definition for DSI_WPCR3 register  ***************/
-#define DSI_WPCR3_THSZERO                ((uint32_t)0x000000FFU)              /*!< t-HSZERO */
-#define DSI_WPCR3_THSZERO0               ((uint32_t)0x00000001U)
-#define DSI_WPCR3_THSZERO1               ((uint32_t)0x00000002U)
-#define DSI_WPCR3_THSZERO2               ((uint32_t)0x00000004U)
-#define DSI_WPCR3_THSZERO3               ((uint32_t)0x00000008U)
-#define DSI_WPCR3_THSZERO4               ((uint32_t)0x00000010U)
-#define DSI_WPCR3_THSZERO5               ((uint32_t)0x00000020U)
-#define DSI_WPCR3_THSZERO6               ((uint32_t)0x00000040U)
-#define DSI_WPCR3_THSZERO7               ((uint32_t)0x00000080U)
+#define DSI_WPCR3_THSZERO                0x000000FFU              /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0               0x00000001U
+#define DSI_WPCR3_THSZERO1               0x00000002U
+#define DSI_WPCR3_THSZERO2               0x00000004U
+#define DSI_WPCR3_THSZERO3               0x00000008U
+#define DSI_WPCR3_THSZERO4               0x00000010U
+#define DSI_WPCR3_THSZERO5               0x00000020U
+#define DSI_WPCR3_THSZERO6               0x00000040U
+#define DSI_WPCR3_THSZERO7               0x00000080U
 
-#define DSI_WPCR3_TLPXD                  ((uint32_t)0x0000FF00U)              /*!< t-LPXD */
-#define DSI_WPCR3_TLPXD0                 ((uint32_t)0x00000100U)
-#define DSI_WPCR3_TLPXD1                 ((uint32_t)0x00000200U)
-#define DSI_WPCR3_TLPXD2                 ((uint32_t)0x00000400U)
-#define DSI_WPCR3_TLPXD3                 ((uint32_t)0x00000800U)
-#define DSI_WPCR3_TLPXD4                 ((uint32_t)0x00001000U)
-#define DSI_WPCR3_TLPXD5                 ((uint32_t)0x00002000U)
-#define DSI_WPCR3_TLPXD6                 ((uint32_t)0x00004000U)
-#define DSI_WPCR3_TLPXD7                 ((uint32_t)0x00008000U)
+#define DSI_WPCR3_TLPXD                  0x0000FF00U              /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0                 0x00000100U
+#define DSI_WPCR3_TLPXD1                 0x00000200U
+#define DSI_WPCR3_TLPXD2                 0x00000400U
+#define DSI_WPCR3_TLPXD3                 0x00000800U
+#define DSI_WPCR3_TLPXD4                 0x00001000U
+#define DSI_WPCR3_TLPXD5                 0x00002000U
+#define DSI_WPCR3_TLPXD6                 0x00004000U
+#define DSI_WPCR3_TLPXD7                 0x00008000U
 
-#define DSI_WPCR3_THSEXIT                ((uint32_t)0x00FF0000U)              /*!< t-HSEXIT */
-#define DSI_WPCR3_THSEXIT0               ((uint32_t)0x00010000U)
-#define DSI_WPCR3_THSEXIT1               ((uint32_t)0x00020000U)
-#define DSI_WPCR3_THSEXIT2               ((uint32_t)0x00040000U)
-#define DSI_WPCR3_THSEXIT3               ((uint32_t)0x00080000U)
-#define DSI_WPCR3_THSEXIT4               ((uint32_t)0x00100000U)
-#define DSI_WPCR3_THSEXIT5               ((uint32_t)0x00200000U)
-#define DSI_WPCR3_THSEXIT6               ((uint32_t)0x00400000U)
-#define DSI_WPCR3_THSEXIT7               ((uint32_t)0x00800000U)
+#define DSI_WPCR3_THSEXIT                0x00FF0000U              /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0               0x00010000U
+#define DSI_WPCR3_THSEXIT1               0x00020000U
+#define DSI_WPCR3_THSEXIT2               0x00040000U
+#define DSI_WPCR3_THSEXIT3               0x00080000U
+#define DSI_WPCR3_THSEXIT4               0x00100000U
+#define DSI_WPCR3_THSEXIT5               0x00200000U
+#define DSI_WPCR3_THSEXIT6               0x00400000U
+#define DSI_WPCR3_THSEXIT7               0x00800000U
 
-#define DSI_WPCR3_TLPXC                  ((uint32_t)0xFF000000U)              /*!< t-LPXC */
-#define DSI_WPCR3_TLPXC0                 ((uint32_t)0x01000000U)
-#define DSI_WPCR3_TLPXC1                 ((uint32_t)0x02000000U)
-#define DSI_WPCR3_TLPXC2                 ((uint32_t)0x04000000U)
-#define DSI_WPCR3_TLPXC3                 ((uint32_t)0x08000000U)
-#define DSI_WPCR3_TLPXC4                 ((uint32_t)0x10000000U)
-#define DSI_WPCR3_TLPXC5                 ((uint32_t)0x20000000U)
-#define DSI_WPCR3_TLPXC6                 ((uint32_t)0x40000000U)
-#define DSI_WPCR3_TLPXC7                 ((uint32_t)0x80000000U)
+#define DSI_WPCR3_TLPXC                  0xFF000000U              /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0                 0x01000000U
+#define DSI_WPCR3_TLPXC1                 0x02000000U
+#define DSI_WPCR3_TLPXC2                 0x04000000U
+#define DSI_WPCR3_TLPXC3                 0x08000000U
+#define DSI_WPCR3_TLPXC4                 0x10000000U
+#define DSI_WPCR3_TLPXC5                 0x20000000U
+#define DSI_WPCR3_TLPXC6                 0x40000000U
+#define DSI_WPCR3_TLPXC7                 0x80000000U
 
 /*******************  Bit definition for DSI_WPCR4 register  ***************/
-#define DSI_WPCR4_TCLKPOST               ((uint32_t)0x000000FFU)              /*!< t-CLKPOST */
-#define DSI_WPCR4_TCLKPOST0              ((uint32_t)0x00000001U)
-#define DSI_WPCR4_TCLKPOST1              ((uint32_t)0x00000002U)
-#define DSI_WPCR4_TCLKPOST2              ((uint32_t)0x00000004U)
-#define DSI_WPCR4_TCLKPOST3              ((uint32_t)0x00000008U)
-#define DSI_WPCR4_TCLKPOST4              ((uint32_t)0x00000010U)
-#define DSI_WPCR4_TCLKPOST5              ((uint32_t)0x00000020U)
-#define DSI_WPCR4_TCLKPOST6              ((uint32_t)0x00000040U)
-#define DSI_WPCR4_TCLKPOST7              ((uint32_t)0x00000080U)
+#define DSI_WPCR4_TCLKPOST               0x000000FFU              /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0              0x00000001U
+#define DSI_WPCR4_TCLKPOST1              0x00000002U
+#define DSI_WPCR4_TCLKPOST2              0x00000004U
+#define DSI_WPCR4_TCLKPOST3              0x00000008U
+#define DSI_WPCR4_TCLKPOST4              0x00000010U
+#define DSI_WPCR4_TCLKPOST5              0x00000020U
+#define DSI_WPCR4_TCLKPOST6              0x00000040U
+#define DSI_WPCR4_TCLKPOST7              0x00000080U
 
 /*******************  Bit definition for DSI_WRPCR register  ***************/
-#define DSI_WRPCR_PLLEN                  ((uint32_t)0x00000001U)              /*!< PLL Enable */
-#define DSI_WRPCR_PLL_NDIV               ((uint32_t)0x000001FCU)              /*!< PLL Loop Division Factor */
-#define DSI_WRPCR_PLL_NDIV0              ((uint32_t)0x00000004U)
-#define DSI_WRPCR_PLL_NDIV1              ((uint32_t)0x00000008U)
-#define DSI_WRPCR_PLL_NDIV2              ((uint32_t)0x00000010U)
-#define DSI_WRPCR_PLL_NDIV3              ((uint32_t)0x00000020U)
-#define DSI_WRPCR_PLL_NDIV4              ((uint32_t)0x00000040U)
-#define DSI_WRPCR_PLL_NDIV5              ((uint32_t)0x00000080U)
-#define DSI_WRPCR_PLL_NDIV6              ((uint32_t)0x00000100U)
+#define DSI_WRPCR_PLLEN                  0x00000001U              /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV               0x000001FCU              /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0              0x00000004U
+#define DSI_WRPCR_PLL_NDIV1              0x00000008U
+#define DSI_WRPCR_PLL_NDIV2              0x00000010U
+#define DSI_WRPCR_PLL_NDIV3              0x00000020U
+#define DSI_WRPCR_PLL_NDIV4              0x00000040U
+#define DSI_WRPCR_PLL_NDIV5              0x00000080U
+#define DSI_WRPCR_PLL_NDIV6              0x00000100U
 
-#define DSI_WRPCR_PLL_IDF                ((uint32_t)0x00007800U)              /*!< PLL Input Division Factor */
-#define DSI_WRPCR_PLL_IDF0               ((uint32_t)0x00000800U)
-#define DSI_WRPCR_PLL_IDF1               ((uint32_t)0x00001000U)
-#define DSI_WRPCR_PLL_IDF2               ((uint32_t)0x00002000U)
-#define DSI_WRPCR_PLL_IDF3               ((uint32_t)0x00004000U)
+#define DSI_WRPCR_PLL_IDF                0x00007800U              /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0               0x00000800U
+#define DSI_WRPCR_PLL_IDF1               0x00001000U
+#define DSI_WRPCR_PLL_IDF2               0x00002000U
+#define DSI_WRPCR_PLL_IDF3               0x00004000U
 
-#define DSI_WRPCR_PLL_ODF                ((uint32_t)0x00030000U)              /*!< PLL Output Division Factor */
-#define DSI_WRPCR_PLL_ODF0               ((uint32_t)0x00010000U)
-#define DSI_WRPCR_PLL_ODF1               ((uint32_t)0x00020000U)
+#define DSI_WRPCR_PLL_ODF                0x00030000U              /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0               0x00010000U
+#define DSI_WRPCR_PLL_ODF1               0x00020000U
 
-#define DSI_WRPCR_REGEN                  ((uint32_t)0x01000000U)              /*!< Regulator Enable */
+#define DSI_WRPCR_REGEN                  0x01000000U              /*!< Regulator Enable */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4828,154 +4852,154 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4983,108 +5007,108 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008U)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009U)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000AU)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000BU)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000CU)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000DU)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000EU)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000FU)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
 #define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010U)
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000U) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000U) 
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5092,709 +5116,709 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000U)        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     ((uint32_t)0x00200000U)        /*!<Write FIFO Disable         */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
 
 /******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  ((uint32_t)0x000000FFU)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMWAIT2                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHOLD2                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHIZ2                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  ((uint32_t)0x000000FFU)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTWAIT2                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHOLD2                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHIZ2                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000U)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000U)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007U)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
                                             
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008U)        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
 
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010U)        /*!<Command target 1 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
 
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0U)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100U)        /*!<Bit 3 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
 
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00U)        /*!<MRD[12:0] bits (Mode register definition) */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
 
 /******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001U)        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
 
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFEU)        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
 
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000U)        /*!<RES interupt enable */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
 
 /******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001U)        /*!<Refresh error flag */
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
 
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006U)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004U)        /*!<Bit 1 */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
 
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018U)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020U)        /*!<Busy status */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5802,235 +5826,235 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -6050,22 +6074,22 @@ typedef struct
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -6085,57 +6109,57 @@ typedef struct
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -6143,97 +6167,97 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6241,20 +6265,20 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -6265,148 +6289,148 @@ typedef struct
 
 /********************  Bit definition for LTDC_SSCR register  *****************/
 
-#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FFU)              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000U)              /*!< Horizontal Synchronization Width */
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
 
 /********************  Bit definition for LTDC_BPCR register  *****************/
 
-#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FFU)              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000U)              /*!< Accumulated Horizontal Back Porch */
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
 
 /********************  Bit definition for LTDC_AWCR register  *****************/
 
-#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FFU)              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000U)              /*!< Accumulated Active Width */
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
 
 /********************  Bit definition for LTDC_TWCR register  *****************/
 
-#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FFU)              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000U)              /*!< Total Width */
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
 
 /********************  Bit definition for LTDC_GCR register  ******************/
 
-#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001U)              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        ((uint32_t)0x00000070U)              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        ((uint32_t)0x00000700U)              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        ((uint32_t)0x00007000U)              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        ((uint32_t)0x00010000U)              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000U)              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000U)              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000U)              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000U)              /*!< Horizontal Synchronization Polarity */
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
 
 /* Legacy defines */
 #define LTDC_GCR_DTEN                       LTDC_GCR_DEN
 
 /********************  Bit definition for LTDC_SRCR register  *****************/
 
-#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001U)               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002U)               /*!< Vertical Blanking Reload */
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
 
 /********************  Bit definition for LTDC_BCCR register  *****************/
 
-#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FFU)              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00U)              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000U)              /*!< Background Red value */
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
 
 /********************  Bit definition for LTDC_IER register  ******************/
 
-#define LTDC_IER_LIE                        ((uint32_t)0x00000001U)              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       ((uint32_t)0x00000002U)              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004U)              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       ((uint32_t)0x00000008U)              /*!< Register Reload interrupt enable */
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
 
 /********************  Bit definition for LTDC_ISR register  ******************/
 
-#define LTDC_ISR_LIF                        ((uint32_t)0x00000001U)              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002U)              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004U)              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008U)              /*!< Register Reload interrupt Flag */
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_ICR register  ******************/
 
-#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001U)              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002U)              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004U)              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008U)              /*!< Clears Register Reload interrupt Flag */
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_LIPCR register  ****************/
 
-#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FFU)              /*!< Line Interrupt Position */
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
 
 /********************  Bit definition for LTDC_CPSR register  *****************/
 
-#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFFU)              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000U)              /*!< Current X Position */
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
 
 /********************  Bit definition for LTDC_CDSR register  *****************/
 
-#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001U)              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002U)              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004U)              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008U)              /*!< Horizontal Synchronization Status */
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
 
 /********************  Bit definition for LTDC_LxCR register  *****************/
 
-#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001U)              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002U)              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010U)              /*!< Color Lockup Table Enable */
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
 
 /********************  Bit definition for LTDC_LxWHPCR register  **************/
 
-#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFFU)              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000U)              /*!< Window Horizontal Stop Position */
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
 
 /********************  Bit definition for LTDC_LxWVPCR register  **************/
 
-#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFFU)              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000U)              /*!< Window Vertical Stop Position */
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
 
 /********************  Bit definition for LTDC_LxCKCR register  ***************/
 
-#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FFU)              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00U)              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000U)              /*!< Color Key Red value */
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
 
 /********************  Bit definition for LTDC_LxPFCR register  ***************/
 
-#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007U)              /*!< Pixel Format */
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
 
 /********************  Bit definition for LTDC_LxCACR register  ***************/
 
-#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FFU)              /*!< Constant Alpha */
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
 
 /********************  Bit definition for LTDC_LxDCCR register  ***************/
 
-#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FFU)              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00U)              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000U)              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000U)              /*!< Default Color Alpha */
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
                                 
 /********************  Bit definition for LTDC_LxBFCR register  ***************/
 
-#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007U)              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700U)              /*!< Blending Factor 1 */
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
 
 /********************  Bit definition for LTDC_LxCFBAR register  **************/
 
-#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFFU)              /*!< Color Frame Buffer Start Address */
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
 
 /********************  Bit definition for LTDC_LxCFBLR register  **************/
 
-#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFFU)              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000U)              /*!< Color Frame Buffer Pitch in bytes */
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
 
 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
 
-#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FFU)              /*!< Frame Buffer Line Number */
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
 
 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
 
-#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FFU)              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00U)              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000U)              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000U)              /*!< CLUT address */
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
 
 
 /******************************************************************************/
@@ -6415,39 +6439,39 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000U)     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000U)     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000U)     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000U)     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000U)     /*!< Bit 1                               */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
@@ -6455,17 +6479,17 @@ typedef struct
 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_WUPP                        ((uint32_t)0x00000080U)     /*!< WKUP pin Polarity                                */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000U)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000U)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000U)     /*!< Under Drive ready                                */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_WUPP                        0x00000080U     /*!< WKUP pin Polarity                                */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -6476,133 +6500,133 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001U)            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002U)            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004U)            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008U)            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000010U)            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          ((uint32_t)0x00000040U)            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         ((uint32_t)0x00000080U)            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00001F00U)            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     ((uint32_t)0x00000800U)            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     ((uint32_t)0x00001000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000U)            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000U)            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000U)            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000U)            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000U)            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000U)            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000U)            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  ((uint32_t)0x04000000U)            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  ((uint32_t)0x08000000U)            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  ((uint32_t)0x10000000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  ((uint32_t)0x20000000U)            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  ((uint32_t)0x40000000U)            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  ((uint32_t)0x80000000U)            /*!< Bit 7 */
+#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
+#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
+#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
+#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
+#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
+#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
+#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
+#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
+#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
+#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
+#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
 
 /*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001U)            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700U)            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000U)            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     ((uint32_t)0x00040000U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     ((uint32_t)0x00080000U)            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     ((uint32_t)0x00100000U)            /*!< Bit 4 */
+#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
 
 /******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001U)             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002U)             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008U)             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010U)             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020U)             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00003F00U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     ((uint32_t)0x00000100U)             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     ((uint32_t)0x00000200U)             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     ((uint32_t)0x00000400U)             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     ((uint32_t)0x00000800U)             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     ((uint32_t)0x00001000U)             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     ((uint32_t)0x00002000U)             /*!< Bit 5 */
+#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
+#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
 
 /******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001U)             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002U)             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008U)             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010U)             /*!< Clear Timeout Flag           */
+#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
 
 /******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFFU)               /*!< DL[31:0]: Data Length */
+#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
 
 /******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FFU)            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                ((uint32_t)0x00000001U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                ((uint32_t)0x00000002U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                ((uint32_t)0x00000004U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                ((uint32_t)0x00000008U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                ((uint32_t)0x00000010U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                ((uint32_t)0x00000020U)            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                ((uint32_t)0x00000040U)            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                ((uint32_t)0x00000080U)            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300U)            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00U)            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000U)            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000U)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000U)            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000U)            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       ((uint32_t)0x00040000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       ((uint32_t)0x00080000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       ((uint32_t)0x00100000U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       ((uint32_t)0x00200000U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       ((uint32_t)0x00400000U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000U)            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000U)            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000U)            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         ((uint32_t)0x40000000U)            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000U)            /*!< DDRM: Double Data Rate Mode           */ 
+#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
+#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
+#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
+#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
 /******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFFU)            /*!< ADDRESS[31:0]: Address                */
+#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
 
 /******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFFU)            /*!< ALTERNATE[31:0]: Alternate Bytes      */
+#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
 
 /******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFFU)            /*!< DATA[31:0]: Data                      */
+#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
 
 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFFU)            /*!< MASK[31:0]: Status Mask               */
+#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
 
 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFFU)            /*!< MATCH[31:0]: Status Match             */
+#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
 
 /******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFFU)            /*!< INTERVAL[15:0]: Polling Interval      */
+#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
 
 /******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFFU)            /*!< TIMEOUT[15:0]: Timeout period         */
+#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6610,535 +6634,535 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000U)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
-#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x70000000U)
-#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x10000000U)
-#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x20000000U)
-#define  RCC_PLLCFGR_PLLR_2                  ((uint32_t)0x40000000U)
+#define  RCC_PLLCFGR_PLLR                    0x70000000U
+#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
+#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
+#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
 
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040U)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000U)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000U)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100U)
-#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200U)
-#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
-#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000U)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000U)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB3RSTR_QSPIRST               ((uint32_t)0x00000002U)
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
+#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040U)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080U)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000U)
-#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000U)
-#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
-#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000U)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000U)
-#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000U)
-#define  RCC_APB2RSTR_DSIRST                 ((uint32_t)0x08000000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
+#define  RCC_APB2RSTR_DSIRST                 0x08000000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100U)
-#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200U)
-#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
 
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
-#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000U)
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
 
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000U)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000U)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000U)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000U)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000U)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000U)
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB3ENR_QSPIEN                 ((uint32_t)0x00000002U)
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040U)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080U)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000U)
-#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000U)
-#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200U)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000U)
-#define  RCC_APB2ENR_DSIEN                   ((uint32_t)0x08000000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
+#define  RCC_APB2ENR_DSIEN                   0x08000000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
 
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000U)
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
 
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000U)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000U)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000U)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000U)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000U)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000U)
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040U)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB3LPENR_QSPILPEN             ((uint32_t)0x00000002U)
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
+#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010U)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020U)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040U)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080U)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000U)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000U)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000U)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
-#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000U)
-#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200U)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
-#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB2LPENR_DSILPEN               ((uint32_t)0x08000000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
+#define  RCC_APB2LPENR_DSILPEN               0x08000000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 
 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
 
-#define  RCC_PLLSAICFGR_PLLSAIP              ((uint32_t)0x00030000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_0            ((uint32_t)0x00010000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_1            ((uint32_t)0x00020000U)
+#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
+#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
+#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
 
-#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
 
-#define  RCC_PLLSAICFGR_PLLSAIR              ((uint32_t)0x70000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001FU)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00U)
-#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000U)
-#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000U)
-#define  RCC_DCKCFGR_SAI1ASRC_0              ((uint32_t)0x00100000U)
-#define  RCC_DCKCFGR_SAI1ASRC_1              ((uint32_t)0x00200000U)
-#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR_SAI1BSRC_0              ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR_SAI1BSRC_1              ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000U)
-#define  RCC_DCKCFGR_CK48MSEL                ((uint32_t)0x08000000U)
-#define  RCC_DCKCFGR_SDIOSEL                 ((uint32_t)0x10000000U)
-#define  RCC_DCKCFGR_DSISEL                  ((uint32_t)0x20000000U)
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
+#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
+#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
+#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
+#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
+#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
+#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
+#define  RCC_DCKCFGR_CK48MSEL                0x08000000U
+#define  RCC_DCKCFGR_SDIOSEL                 0x10000000U
+#define  RCC_DCKCFGR_DSISEL                  0x20000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -7146,15 +7170,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004U)
-#define RNG_CR_IE                            ((uint32_t)0x00000008U)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001U)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002U)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004U)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020U)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040U)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -7162,379 +7186,379 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -7542,150 +7566,152 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003U)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
 
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030U)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
 
 /*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003U)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
 
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000CU)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
 
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0U)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080U)        /*!<Bit 2 */
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
 
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100U)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200U)        /*!<ClocK STRobing edge      */
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
 
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00U)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
 
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000U)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000U)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000U)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000U)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000U)        /*!<No Divider Configuration   */
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
 
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000U)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000U)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000U)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000U)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000U)        /*!<Bit 3  */
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
 
 /*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007U)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
 
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008U)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010U)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020U)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040U)        /*!<Muate value                      */
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
 
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80U)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100U)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200U)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400U)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800U)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000U)        /*!<Bit 5 */
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000U)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
 
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000U)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000U)        /*!<Bit 1 */
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
 
 /******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FFU)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
 
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00U)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000U)        /*!<Bit 6 */
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
 
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000U)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000U)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000U)        /*!<Frame Synchronization OFFset      */
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
 
 /******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001FU)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010U)        /*!<Bit 4 */
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
 
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0U)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
 
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00U)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
 
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000U)        /*!<SLOTEN[15:0] (Slot Enable)  */
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
 
 /*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001U)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002U)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004U)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008U)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010U)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020U)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040U)        /*!<Late frame synchronization detection interrupt enable          */
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
 
 /********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001U)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002U)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004U)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008U)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010U)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020U)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040U)         /*!<Late frame synchronization detection           */
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
 
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000U)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000U)         /*!<Bit 2 */
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
 
 /******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001U)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002U)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004U)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008U)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010U)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020U)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040U)        /*!<Clear Late frame synchronization detection           */
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
 
 /******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFFU)        
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
 
 
 /******************************************************************************/
@@ -7694,148 +7720,148 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7843,85 +7869,85 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 ((uint32_t)0x00001000U)            /*!<Asynchronous start enable */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7929,288 +7955,288 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
-#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100U) /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  ((uint32_t)0x00000C00U) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
 
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000U) /*!<Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008U) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009U) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000AU) /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080U) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090U) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0U) /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
 
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600U) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800U) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900U) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00U) /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
 
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000U) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000U) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000U) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000U) /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006U) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008U) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009U) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000AU) /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060U) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080U) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090U) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0U) /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600U) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800U) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900U) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00U) /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
 
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000U) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000U) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000U) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000U) /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006U) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008U) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009U) /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060U) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080U) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090U) /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
 
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600U) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800U) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900U) /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
 
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000U) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000U) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000U) /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006U) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008U) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009U) /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
 
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060U) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008U) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009U) /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
 
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600U) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800U) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900U) /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
 
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000U) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000U) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000U) /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -8218,298 +8244,298 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -8518,82 +8544,82 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -8601,35 +8627,54 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -8638,46 +8683,46 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -8685,91 +8730,91 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000U)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000U)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000U)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000U)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000U)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000U)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000U)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000U)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000U)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000U)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000U)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000U)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000U)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000U)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000U)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800U)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400U)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200U)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080U)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060U)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000U)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020U)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040U)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060U)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010U)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008U)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004U)  /* Receiver enable */
+  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
 
 /* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000U)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400U)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200U)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100U)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0U)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040U)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080U)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0U)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020U)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010U)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008U)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004U)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002U)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001U)  /* Promiscuous mode */
+#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFFU)  /* Hash table high */
+#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFFU)  /* Hash table low */
+#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800U)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0U)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001CU)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000U)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004U)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008U)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000CU)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010U)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002U)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001U)  /* MII busy */ 
+#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
   
 /* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFFU)  /* MII data: read/write data from/to PHY */
+#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000U)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080U)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030U)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000U)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010U)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020U)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030U)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008U)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004U)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002U)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001U)  /* Flow control busy/backpressure activate */
+#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
 
 /* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000U)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFFU)  /* VLAN tag identifier (for receive frames) */
+#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
 
 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFFU)  /* Wake-up frame filter register data */
+#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
@@ -8783,334 +8828,334 @@ typedef struct
    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
 
 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000U)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200U)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040U)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020U)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004U)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002U)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001U)  /* Power Down */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
 
 /* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200U)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040U)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020U)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010U)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008U)  /* PMT status */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
 
 /* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200U)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008U)  /* PMT interrupt mask */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
 
 /* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFFU)  /* MAC address0 high */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
 
 /* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFFU)  /* MAC address0 low */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
 
 /* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFFU)  /* MAC address1 high */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFFU)  /* MAC address1 low */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
 
 /* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFFU)  /* MAC address1 high */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFFU)  /* MAC address2 low */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
 
 /* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFFU)  /* MAC address3 high */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
 
 /* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFFU)  /* MAC address3 low */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
 
 /******************************************************************************/
 /*                Ethernet MMC Registers bits definition                      */
 /******************************************************************************/
 
 /* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020U)  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010U)  /* MMC counter preset */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008U)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004U)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002U)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001U)  /* Counters Reset */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000U)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040U)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020U)  /* Set when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000U)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000U)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000U)  /* Set when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000U)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040U)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020U)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000U)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000U)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000U)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFFU)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFFU)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFFU)  /* Number of good frames transmitted. */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
 
 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFFU)  /* Number of frames received with CRC error. */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
 
 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFFU)  /* Number of frames received with alignment (dribble) error */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
 
 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFFU)  /* Number of good unicast frames received. */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
 
 /******************************************************************************/
 /*               Ethernet PTP Registers bits definition                       */
 /******************************************************************************/
 
 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000U)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000U)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000U)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000U)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000U)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800U)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400U)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200U)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100U)  /* Time stamp snapshot for all received frames enable */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
 
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020U)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010U)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008U)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004U)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002U)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001U)  /* Time stamp enable */
+#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
 
 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FFU)  /* System time Sub-second increment value */
+#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
 
 /* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFFU)  /* System Time second */
+#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000U)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFFU)  /* System Time sub-seconds */
+#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFFU)  /* Time stamp update seconds */
+#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000U)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFFU)  /* Time stamp update sub-seconds */
+#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFFU)  /* Time stamp addend */
+#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
 
 /* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFFU)  /* Target time stamp high */
+#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
 
 /* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFFU)  /* Target time stamp low */
+#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
 
 /* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020U)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010U)  /* Time stamp seconds overflow */
+#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
 
 /******************************************************************************/
 /*                 Ethernet DMA Registers bits definition                     */
 /******************************************************************************/
 
 /* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000U)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000U)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000U)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000U)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000U)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000U)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00U)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080U)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007CU)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002U)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001U)  /* Software reset */
+#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
 
 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFFU)  /* Transmit poll demand */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
 
 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFFU)  /* Receive poll demand  */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
 
 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFFU)  /* Start of receive list */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
 
 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFFU)  /* Start of transmit list */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
 
 /* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000U)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000U)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000U)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000U)  /* Error bits status */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
   /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000U)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000U)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000U)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000U)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000U)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000U)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000U)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000U)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000U)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000U)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000U)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000U)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000U)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000U)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000U)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000U)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000U)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000U)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000U)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000U)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000U)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400U)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200U)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100U)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080U)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040U)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020U)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010U)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008U)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004U)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002U)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001U)  /* Transmit status */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
 
 /* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000U)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000U)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000U)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000U)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000U)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000U)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000U)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000U)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000U)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000U)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000U)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000U)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000U)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000U)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000U)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080U)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040U)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018U)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000U)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008U)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010U)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018U)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004U)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002U)  /* Start/stop receive */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
 
 /* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000U)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000U)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000U)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000U)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400U)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200U)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100U)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080U)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040U)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020U)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010U)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008U)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004U)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002U)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001U)  /* Transmit interrupt enable */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
 
 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000U)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000U)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000U)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFFU)  /* Number of frames missed by the controller */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFFU)  /* Host transmit descriptor address pointer */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFFU)  /* Host receive descriptor address pointer */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFFU)  /* Host transmit buffer address pointer */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFFU)  /* Host receive buffer address pointer */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
 
 /******************************************************************************/
 /*                                                                            */
@@ -9118,678 +9163,678 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                ((uint32_t)0x00000004U)         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               ((uint32_t)0x00000008U)         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 ((uint32_t)0x00000010U)         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                ((uint32_t)0x00000020U)         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 ((uint32_t)0x00000040U)         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                ((uint32_t)0x00000080U)         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    ((uint32_t)0x00001000U)         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 ((uint32_t)0x00080000U)         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  ((uint32_t)0x00100000U)         /*!< OTG version  */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  ((uint32_t)0x00100000U)            /*!< Change in ID pin input value           */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status   */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status   */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                ((uint32_t)0x00000020U)            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  ((uint32_t)0x08000000U)            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt        */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 ((uint32_t)0x08000000U)            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask        */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth                */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)         /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)           /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 ((uint32_t)0x00010000U)              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  ((uint32_t)0x00200000U)              /*!< USB VBUS Detection Enable */
+#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
  
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               ((uint32_t)0x00000001U)            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              ((uint32_t)0x00000002U)            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                ((uint32_t)0x0000003CU)            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             ((uint32_t)0x00000040U)            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              ((uint32_t)0x00000080U)            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            ((uint32_t)0x00000F00U)            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              ((uint32_t)0x00001000U)            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              ((uint32_t)0x00006000U)            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              ((uint32_t)0x00008000U)            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             ((uint32_t)0x00010000U)            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            ((uint32_t)0x001E0000U)            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             ((uint32_t)0x00E00000U)            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              ((uint32_t)0x01000000U)            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          ((uint32_t)0x0E000000U)            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              ((uint32_t)0x10000000U)            /*!< Enable best effort service latency                     */
+#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset                 */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power                 */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask                       */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth                    */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status                       */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake                  */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable                  */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space available */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 ((uint32_t)0x00000020U)            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 
 /**
@@ -9881,8 +9926,10 @@ typedef struct
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
 
 /******************************* SAI Instances ********************************/
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
                                      ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
 
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx.h
index bcf4df4362..fa17bf2f3a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c
index 14e967f0eb..d3cdb0fa83 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -109,9 +109,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -334,7 +335,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -499,7 +500,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -688,7 +689,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -765,18 +766,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h
index ef4aeb1b16..dea62528ba 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f411xe.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
@@ -387,7 +387,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -665,17 +666,14 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(128 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -752,23 +750,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -861,334 +859,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1196,30 +1194,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1227,15 +1225,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1249,161 +1247,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1412,154 +1410,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1567,97 +1565,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1665,235 +1663,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1913,22 +1911,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1948,57 +1946,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2006,97 +2004,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2104,20 +2102,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2126,50 +2124,50 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2180,381 +2178,382 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2562,379 +2561,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2944,157 +2943,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3102,84 +3101,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3187,199 +3186,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3387,298 +3386,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3687,82 +3686,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3770,35 +3769,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3807,46 +3825,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3854,654 +3872,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx.h
index ef74b7a35e..00021fa5e5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c
index 0288dfc685..21da3d3392 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -111,9 +111,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -340,7 +341,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -505,7 +506,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -694,7 +695,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -771,18 +772,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h
index ef4aeb1b16..dea62528ba 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f411xe.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
@@ -387,7 +387,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -665,17 +666,14 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(128 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -752,23 +750,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -861,334 +859,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1196,30 +1194,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1227,15 +1225,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1249,161 +1247,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1412,154 +1410,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1567,97 +1565,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1665,235 +1663,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1913,22 +1911,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1948,57 +1946,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2006,97 +2004,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2104,20 +2102,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2126,50 +2124,50 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2180,381 +2178,382 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2562,379 +2561,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2944,157 +2943,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3102,84 +3101,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3187,199 +3186,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3387,298 +3386,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3687,82 +3686,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3770,35 +3769,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3807,46 +3825,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3854,654 +3872,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h
index ef74b7a35e..00021fa5e5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c
index 03136e2ec5..221944b748 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -110,9 +110,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -341,7 +342,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -506,7 +507,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -695,7 +696,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -772,18 +773,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h
index 08a2bae7f8..b849ee462d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f405xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F405xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -841,19 +841,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000U) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x080FFFFFU) /*!< FLASH end address */
-#define CCMDATARAM_END        ((uint32_t)0x1000FFFFU) /*!< CCM data RAM end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -954,24 +954,24 @@ USB_OTG_HostChannelTypeDef;
 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000U)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1085,334 +1085,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1420,30 +1420,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1452,1319 +1452,1319 @@ USB_OTG_HostChannelTypeDef;
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001U)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002U)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004U)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008U)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010U)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020U)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040U)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080U)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000U)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000U)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800U)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00U)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001U)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002U)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004U)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008U)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010U)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020U)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040U)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080U)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100U)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200U)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400U)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800U)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000U)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000U)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000U)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000U)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000U)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000U)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000U)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000U)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000U)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000U)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000U)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000U)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000U)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000U)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000U)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000U)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001U)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002U)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004U)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008U)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010U)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020U)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040U)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080U)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100U)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200U)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400U)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800U)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000U)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000U)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000U)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000U)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000U)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000U)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000U)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000U)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000U)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000U)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000U)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000U)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000U)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000U)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000U)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000U)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001U)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002U)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004U)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008U)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010U)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020U)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040U)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080U)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100U)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200U)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400U)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800U)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000U)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000U)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000U)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000U)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000U)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000U)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000U)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000U)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000U)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000U)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000U)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000U)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000U)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000U)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000U)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000U)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001U)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002U)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004U)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008U)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010U)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020U)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040U)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080U)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100U)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200U)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400U)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800U)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000U)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000U)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000U)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000U)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000U)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000U)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000U)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000U)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000U)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000U)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000U)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000U)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000U)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000U)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000U)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000U)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2772,15 +2772,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 
 /******************************************************************************/
@@ -2789,92 +2789,92 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002U)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000U)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable*/
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01U)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02U)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFFU)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFFU)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FFU)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00U)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2888,161 +2888,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3051,154 +3051,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3206,97 +3206,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3304,826 +3304,826 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable                     */
+#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
+#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable                     */
+#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable                     */
+#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable                     */
+#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type */
+#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type */
+#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type */
+#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty */
+#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
 
 /*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty */
+#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
 
 /*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty */
+#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
+#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
+#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
+#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
+#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
+#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
+#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
 
 /******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FFU)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FFU)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FFU)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FFU)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FFU)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FFU)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FFU)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00U)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000U)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000U)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4131,235 +4131,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -4379,22 +4379,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -4414,57 +4414,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -4472,97 +4472,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4570,20 +4570,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -4592,42 +4592,42 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          ((uint32_t)0x00004000U)     /*!< VOS bit (Regulator voltage scaling output selection) */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
+#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -4638,430 +4638,430 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
-#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001U)
+#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040U)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080U)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000U)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000U)
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
-#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001U)
+#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040U)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080U)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200U)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000U)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040U)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
-#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001U)
+#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010U)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020U)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040U)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080U)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000U)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000U)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000U)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200U)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5069,15 +5069,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004U)
-#define RNG_CR_IE                            ((uint32_t)0x00000008U)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001U)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002U)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004U)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020U)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040U)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5085,379 +5085,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -5467,157 +5467,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5625,84 +5625,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5710,245 +5710,245 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000U) /*!<Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008U) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080U) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600U) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800U) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000U) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000U) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006U) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008U) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060U) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080U) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600U) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800U) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000U) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000U) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006U) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008U) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060U) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080U) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600U) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800U) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000U) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000U) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006U) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060U) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600U) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000U) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5956,298 +5956,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -6256,82 +6256,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6339,35 +6339,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -6376,46 +6395,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -6423,654 +6442,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h
index bb4426f5b5..76a17f04f9 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   #define STM32F405xx   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c
index 962df6ee42..e6fe388fbc 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -95,9 +95,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -316,7 +317,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -481,7 +482,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -670,7 +671,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -747,18 +748,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h
index ef4aeb1b16..dea62528ba 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f411xe.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
@@ -387,7 +387,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -665,17 +666,14 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(128 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -752,23 +750,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -861,334 +859,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1196,30 +1194,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1227,15 +1225,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1249,161 +1247,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1412,154 +1410,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1567,97 +1565,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1665,235 +1663,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1913,22 +1911,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1948,57 +1946,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2006,97 +2004,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2104,20 +2102,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2126,50 +2124,50 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2180,381 +2178,382 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2562,379 +2561,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2944,157 +2943,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3102,84 +3101,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3187,199 +3186,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3387,298 +3386,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3687,82 +3686,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3770,35 +3769,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3807,46 +3825,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3854,654 +3872,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h
index 1c8f48a105..52d82dc201 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c
index 9e876cc9a8..9664a1ca58 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -111,9 +111,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -346,7 +347,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -511,7 +512,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -700,7 +701,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -777,18 +778,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h
index 2cf7a3d924..7829cf1618 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f401xe.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F401xExx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
@@ -386,7 +386,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -659,21 +660,17 @@ typedef struct
 }
 USB_OTG_HostChannelTypeDef;
 
-    
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(96 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -749,23 +746,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -857,334 +854,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1192,30 +1189,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1223,15 +1220,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1245,161 +1242,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1408,154 +1405,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1563,97 +1560,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1661,235 +1658,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1909,22 +1906,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1944,57 +1941,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2002,97 +1999,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2100,20 +2097,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2122,47 +2119,47 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2173,368 +2170,370 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2542,379 +2541,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2924,157 +2923,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3082,84 +3081,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3167,199 +3166,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3367,298 +3366,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3667,82 +3666,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3750,35 +3749,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3787,46 +3805,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3834,654 +3852,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h
index 640e8e7770..9cb772f942 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
index 5d23c5c0fd..a3dbba5ab7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -110,9 +110,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -339,7 +340,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -504,7 +505,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -693,7 +694,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -770,18 +771,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h
index 1be7ce1007..1847a12c50 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f410rx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f410rx.h
index b79a611199..a1bce4eb26 100755
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f410rx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f410rx.h
@@ -2,19 +2,19 @@
   ******************************************************************************
   * @file    stm32f410rx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F410Rx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
   *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
+  *           - peripherals registers declarations and bits definition
   *           - Macros to access peripheral’s registers hardware
   *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -578,12 +578,12 @@ typedef struct
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(32 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(32 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                             */
-#define FLASH_END             ((uint32_t)0x0801FFFF) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(32 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define FLASH_END             0x0801FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -591,67 +591,67 @@ typedef struct
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
 
 /*!< APB1 peripherals */
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define RNG_BASE              (PERIPH_BASE + 0x80000)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define RNG_BASE              (PERIPH_BASE + 0x80000U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000U
 
 /**
   * @}
@@ -735,360 +735,365 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1096,15 +1101,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1117,160 +1122,162 @@ typedef struct
 /*                             DMA Controller                                 */
 /*                                                                            */
 /******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1279,160 +1286,160 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1440,97 +1447,97 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1538,306 +1545,306 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1845,97 +1852,97 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000F)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1943,103 +1950,101 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        ((uint32_t)0x00000001)        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      ((uint32_t)0x00000002)        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      ((uint32_t)0x00000004)        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    ((uint32_t)0x00000008)        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    ((uint32_t)0x00000010)        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     ((uint32_t)0x00000080)        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    ((uint32_t)0x00001000)        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_SWRST                     ((uint32_t)0x00002000)        /*!< Software reset                      */
-#define  FMPI2C_CR1_TXDMAEN                   ((uint32_t)0x00004000)        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   ((uint32_t)0x00008000)        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       ((uint32_t)0x00010000)        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 ((uint32_t)0x00020000)        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_WUPEN                     ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable             */
-#define  FMPI2C_CR1_GCEN                      ((uint32_t)0x00080000)        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    ((uint32_t)0x00100000)        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   ((uint32_t)0x00400000)        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     ((uint32_t)0x00800000)        /*!< PEC enable                          */
+#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
+#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
+#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
+#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
+#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
+#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
+#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
+#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
+#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
+#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
+#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
+#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
+#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
+#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
+#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
+#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
+#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
+#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
+#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
 
 /******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      ((uint32_t)0x000003FF)        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    ((uint32_t)0x00000400)        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     ((uint32_t)0x00002000)        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      ((uint32_t)0x00004000)        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      ((uint32_t)0x00008000)        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    ((uint32_t)0x00FF0000)        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    ((uint32_t)0x01000000)        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   ((uint32_t)0x04000000)        /*!< Packet error checking byte                              */
+#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
+#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
+#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
+#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
+#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
+#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
+#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
+#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
+#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
+#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
+#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
 
 /*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      ((uint32_t)0x000003FF)        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    ((uint32_t)0x00008000)        /*!< Own address 1 enable      */
+#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
+#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
+#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
 
 /*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   ((uint32_t)0x00000700)        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    ((uint32_t)0x00008000)        /*!< Own address 2 enable    */
+#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
+#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
+#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
 
 /*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  ((uint32_t)0x000000FF)        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                ((uint32_t)0x000F0000)        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                ((uint32_t)0x00F00000)        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 ((uint32_t)0xF0000000)        /*!< Timings prescaler             */
+#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
+#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
+#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
+#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
+#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
 
 /******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             ((uint32_t)0x00000FFF)        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                ((uint32_t)0x00001000)        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             ((uint32_t)0x00008000)        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             ((uint32_t)0x0FFF0000)        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
+#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
+#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
+#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
+#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
 
 /******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       ((uint32_t)0x00000001)        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      ((uint32_t)0x00000002)        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      ((uint32_t)0x00000004)        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      ((uint32_t)0x00000008)        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     ((uint32_t)0x00000010)        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     ((uint32_t)0x00000020)        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        ((uint32_t)0x00000040)        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       ((uint32_t)0x00000080)        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      ((uint32_t)0x00000100)        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      ((uint32_t)0x00000200)        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    ((uint32_t)0x00000800)        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     ((uint32_t)0x00002000)        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      ((uint32_t)0x00008000)        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode)  */
+#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
+#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
+#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
+#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
+#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
+#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
+#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
+#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
+#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
+#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
+#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
+#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
+#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
+#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
+#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
+#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
+#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
 
 /******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    ((uint32_t)0x00000008)        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    ((uint32_t)0x00000010)        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    ((uint32_t)0x00000020)        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    ((uint32_t)0x00000100)        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     ((uint32_t)0x00000800)        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  ((uint32_t)0x00001000)        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   ((uint32_t)0x00002000)        /*!< Alert clear flag            */
+#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
+#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
+#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
+#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
+#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
+#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
+#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
+#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
+#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
 
 /******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      ((uint32_t)0x000000FF)        /*!< PEC register */
+#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
 
 /******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
 
 /******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2047,20 +2052,20 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2069,50 +2074,50 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2123,347 +2128,347 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
-#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x70000000)
-#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x10000000)
-#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x20000000)
-#define  RCC_PLLCFGR_PLLR_2                  ((uint32_t)0x40000000)
+#define  RCC_PLLCFGR_PLLR                    0x70000000U
+#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
+#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
+#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< MCO1EN configuration */
-#define  RCC_CFGR_MCO1EN                     ((uint32_t)0x00000100)        /*!< MCO1EN bit */
+#define  RCC_CFGR_MCO1EN                     0x00000100U        /*!< MCO1EN bit */
 
 /*!< MCO2EN configuration */
-#define  RCC_CFGR_MCO2EN                     ((uint32_t)0x00000200)        /*!< MCO2EN bit */
+#define  RCC_CFGR_MCO2EN                     0x00000200U        /*!< MCO2EN bit */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
-#define  RCC_AHB1RSTR_RNGRST                 ((uint32_t)0x80000000)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_RNGRST                 0x80000000U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
-#define  RCC_APB1RSTR_LPTIM1RST              ((uint32_t)0x00000200)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_FMPI2C1RST             ((uint32_t)0x01000000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
-#define  RCC_AHB1ENR_RNGEN                   ((uint32_t)0x80000000)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_RNGEN                   0x80000000U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
-#define  RCC_APB1ENR_LPTIM1EN                ((uint32_t)0x00000200)
-#define  RCC_APB1ENR_RTCAPBEN                ((uint32_t)0x00000400)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_FMPI2C1EN               ((uint32_t)0x01000000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
+#define  RCC_APB1ENR_RTCAPBEN                0x00000400U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_EXTITEN                 ((uint32_t)0x00008000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_EXTITEN                 0x00008000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
-#define  RCC_AHB1LPENR_RNGLPEN               ((uint32_t)0x80000000)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_RNGLPEN               0x80000000U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
-#define  RCC_APB1LPENR_LPTIM1LPEN            ((uint32_t)0x00000200)
-#define  RCC_APB1LPENR_RTCAPBLPEN            ((uint32_t)0x00000400)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_FMPI2C1LPEN           ((uint32_t)0x01000000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
+#define  RCC_APB1LPENR_RTCAPBLPEN            0x00000400U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_EXTITLPEN             ((uint32_t)0x00008000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_EXTITLPEN             0x00008000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
-#define  RCC_DCKCFGR_I2SSRC                  ((uint32_t)0x06000000)
-#define  RCC_DCKCFGR_I2SSRC_0                ((uint32_t)0x02000000)
-#define  RCC_DCKCFGR_I2SSRC_1                ((uint32_t)0x04000000)
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
+#define  RCC_DCKCFGR_I2SSRC                  0x06000000U
+#define  RCC_DCKCFGR_I2SSRC_0                0x02000000U
+#define  RCC_DCKCFGR_I2SSRC_1                0x04000000U
 
 /********************  Bit definition for RCC_CKGATENR register  **************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          ((uint32_t)0x00000001)
-#define  RCC_CKGATENR_AHB2APB2_CKEN          ((uint32_t)0x00000002)
-#define  RCC_CKGATENR_CM4DBG_CKEN            ((uint32_t)0x00000004)
-#define  RCC_CKGATENR_SPARE_CKEN             ((uint32_t)0x00000008)
-#define  RCC_CKGATENR_SRAM_CKEN              ((uint32_t)0x00000010)
-#define  RCC_CKGATENR_FLITF_CKEN             ((uint32_t)0x00000020)
-#define  RCC_CKGATENR_RCC_CKEN               ((uint32_t)0x00000040)
+#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
+#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
+#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
+#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
+#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
+#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
+#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
 
 /********************  Bit definition for RCC_DCKCFGR2 register  **************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             ((uint32_t)0x00C00000)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           ((uint32_t)0x00400000)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           ((uint32_t)0x00800000)
-#define  RCC_DCKCFGR2_LPTIM1SEL              ((uint32_t)0xC0000000)
-#define  RCC_DCKCFGR2_LPTIM1SEL_0            ((uint32_t)0x40000000)
-#define  RCC_DCKCFGR2_LPTIM1SEL_1            ((uint32_t)0x80000000)
+#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
+#define  RCC_DCKCFGR2_LPTIM1SEL              0xC0000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x40000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x80000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2471,15 +2476,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2487,379 +2492,379 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -2867,84 +2872,84 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2952,175 +2957,175 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************  Bit definition for SYSCFG_CFGR register  *****************/
-#define SYSCFG_CFGR_FMPI2C1_SCL         ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
 
 /******************  Bit definition for SYSCFG_CFGR2 register  *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK        ((uint32_t)0x00000001) /*!<Core Lockup lock */
-#define SYSCFG_CFGR2_PVD_LOCK           ((uint32_t)0x00000004) /*!<PVD Lock         */
+#define SYSCFG_CFGR2_LOCKUP_LOCK        0x00000001U /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK           0x00000004U /*!<PVD Lock         */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3128,295 +3133,295 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFF)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3424,86 +3429,86 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for LPTIM_ISR register  *******************/
-#define  LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match                       */
-#define  LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match                    */
-#define  LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event         */
-#define  LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK          */
-#define  LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK       */
-#define  LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */
-#define  LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */
+#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
+#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
+#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
+#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
+#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
+#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
+#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
 
 /******************  Bit definition for LPTIM_ICR register  *******************/
-#define  LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag                       */
-#define  LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag                    */
-#define  LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag         */
-#define  LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag          */
-#define  LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag       */
-#define  LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */
-#define  LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */
+#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
+#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
+#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
+#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
+#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
+#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
+#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
 
 /******************  Bit definition for LPTIM_IER register ********************/
-#define  LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable                       */
-#define  LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable                    */
-#define  LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable         */
-#define  LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable          */
-#define  LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable       */
-#define  LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */
-#define  LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */
+#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
+#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
+#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
+#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
+#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
+#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
+#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
 
 /******************  Bit definition for LPTIM_CFGR register *******************/
-#define  LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */
+#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
 
-#define  LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define  LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */
+#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
+#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
 
-#define  LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define  LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */
-#define  LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */
+#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
 
-#define  LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define  LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
 
-#define  LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define  LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */
-#define  LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */
-#define  LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */
+#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
+#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
+#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
+#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
 
-#define  LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define  LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */
-#define  LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */
+#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
 
-#define  LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define  LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */
-#define  LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
 
-#define  LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable           */
-#define  LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape          */
-#define  LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */
-#define  LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode         */
-#define  LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable     */     
-#define  LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable     */          
+#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
+#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
+#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
+#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
+#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
+#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
 
 /******************  Bit definition for LPTIM_CR register  ********************/
-#define  LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable                 */
-#define  LPTIM_CR_SNGSTRT                       ((uint32_t)0x00080002)             /*!< Timer start in single mode     */
-#define  LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */
+#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
+#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
+#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
 
 /******************  Bit definition for LPTIM_CMP register  *******************/
-#define  LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register     */
+#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
 
 /******************  Bit definition for LPTIM_ARR register  *******************/
-#define  LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */
+#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
 
 /******************  Bit definition for LPTIM_CNT register  *******************/
-#define  LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register     */
+#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
 
 /******************  Bit definition for LPTIM_OR register  *******************/
-#define  LPTIM_OR_OR                           ((uint32_t)0x00000003)               /*!< LPTIMER[1:0] bits (Remap selection) */
-#define  LPTIM_OR_OR_0                         ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  LPTIM_OR_OR_1                         ((uint32_t)0x00000002)               /*!< Bit 1 */
+#define  LPTIM_OR_OR                           0x00000003U               /*!< LPTIMER[1:0] bits (Remap selection) */
+#define  LPTIM_OR_OR_0                         0x00000001U               /*!< Bit 0 */
+#define  LPTIM_OR_OR_1                         0x00000002U               /*!< Bit 1 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3511,82 +3516,82 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FF)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000F)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3594,35 +3599,54 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3630,124 +3654,126 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 /******************************************************************************/
 /*                                                                            */
 /*                                DBG                                         */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f4xx.h
index aa284edfca..e3376a9f9b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -77,8 +77,9 @@
 #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
-	!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-	!defined (STM32F479xx)
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,16 +121,16 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.4.2
+  * @brief CMSIS version number V2.5.0
   */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F4xx_CMSIS_DEVICE_VERSION        ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION))
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION))
 
 /**
   * @}
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.c
index 790f362b28..5e05224363 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -95,9 +95,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -324,7 +325,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -489,7 +490,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -678,7 +679,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -755,18 +756,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.h
old mode 100755
new mode 100644
index 3fb34198c2..0b8a72d9ef
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h
index ef4aeb1b16..dea62528ba 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f411xe.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 
   *
   *          This file contains:
@@ -387,7 +387,8 @@ typedef struct
   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-
+  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */
+  __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                          Address offset: 0x8C */
 } RCC_TypeDef;
 
 /** 
@@ -665,17 +666,14 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(128 KB) base address in the alias region                             */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region                          */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -752,23 +750,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -861,334 +859,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1196,30 +1194,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1227,15 +1225,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1249,161 +1247,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -1412,154 +1410,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1567,97 +1565,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -1665,235 +1663,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1913,22 +1911,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -1948,57 +1946,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2006,97 +2004,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2104,20 +2102,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2126,50 +2124,50 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2180,381 +2178,382 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -2562,379 +2561,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -2944,157 +2943,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3102,84 +3101,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3187,199 +3186,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3387,298 +3386,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3687,82 +3686,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3770,35 +3769,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3807,46 +3825,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3854,654 +3872,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h
index 1c8f48a105..52d82dc201 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c
index 3bbd9127f5..4e1f5e62a5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -111,9 +111,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -340,7 +341,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -505,7 +506,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -694,7 +695,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -771,18 +772,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h
index 5215adb02a..80f7b7be2f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f446xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F446xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -936,19 +936,19 @@ typedef struct
 /** @addtogroup Peripheral_memory_map
   * @{
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC registers base address                                                 */
-#define QSPI_R_BASE            ((uint32_t)0xA0001000U) /*!< QuadSPI registers base address                                            */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define QSPI_R_BASE            0xA0001000U /*!< QuadSPI registers base address                                            */
 
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x0807FFFFU) /*!< FLASH end address                                                          */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x0807FFFFU /*!< FLASH end address                                                          */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -1056,24 +1056,24 @@ typedef struct
 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
 
 /*!< Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000U)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1196,334 +1196,334 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)        /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)        /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1531,30 +1531,30 @@ typedef struct
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1563,1320 +1563,1320 @@ typedef struct
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001U)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002U)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004U)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008U)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010U)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020U)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040U)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080U)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000U)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000U)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800U)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00U)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001U)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002U)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004U)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008U)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010U)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020U)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040U)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080U)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100U)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200U)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400U)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800U)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000U)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000U)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000U)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000U)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000U)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000U)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000U)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000U)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000U)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000U)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000U)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000U)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000U)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000U)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000U)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000U)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001U)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002U)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004U)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008U)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010U)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020U)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040U)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080U)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100U)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200U)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400U)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800U)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000U)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000U)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000U)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000U)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000U)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000U)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000U)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000U)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000U)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000U)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000U)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000U)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000U)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000U)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000U)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000U)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001U)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002U)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004U)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008U)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010U)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020U)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040U)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080U)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100U)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200U)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400U)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800U)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000U)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000U)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000U)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000U)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000U)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000U)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000U)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000U)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000U)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000U)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000U)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000U)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000U)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000U)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000U)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000U)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001U)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002U)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004U)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008U)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010U)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020U)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040U)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080U)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100U)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200U)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400U)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800U)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000U)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000U)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000U)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000U)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000U)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000U)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000U)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000U)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000U)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000U)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000U)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000U)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000U)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000U)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000U)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000U)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2885,56 +2885,56 @@ typedef struct
 /******************************************************************************/
 
 /*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        ((uint32_t)0x00000001U)       /*!< CEC Enable                              */
-#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002U)       /*!< CEC Tx Start Of Message                 */
-#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004U)       /*!< CEC Tx End Of Message                   */
+#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                              */
+#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message                 */
+#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message                   */
 
 /*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007U)       /*!< CEC Signal Free Time                    */
-#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008U)       /*!< CEC Tolerance                           */
-#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010U)       /*!< CEC Rx Stop                             */
-#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020U)       /*!< CEC Bit Rising Error generation         */
-#define  CEC_CFGR_LBPEGEN                    ((uint32_t)0x00000040U)       /*!< CEC Long Bit Period Error generation    */
-#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100U)       /*!< CEC Signal Free Time optional           */
-#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080U)       /*!< CEC Broadcast No error generation       */
-#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000U)       /*!< CEC Own Address                         */
-#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000U)       /*!< CEC Listen mode                         */
+#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time                    */
+#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                           */
+#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                             */
+#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation         */
+#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Bit Period Error generation    */
+#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional           */
+#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast No error generation       */
+#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                         */
+#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                         */
 
 /*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FFU)       /*!< CEC Tx Data                              */
+#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                              */
 
 /*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FFU)       /*!< CEC Rx Data                              */
+#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                              */
 
 /*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001U)       /*!< CEC Rx-Byte Received                      */
-#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002U)       /*!< CEC End Of Reception                      */
-#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004U)       /*!< CEC Rx-Overrun                            */
-#define  CEC_ISR_BRE                         ((uint32_t)0x00000008U)       /*!< CEC Rx Bit Rising Error                   */
-#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010U)       /*!< CEC Rx Short Bit period Error             */
-#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020U)       /*!< CEC Rx Long Bit period Error              */
-#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040U)       /*!< CEC Rx Missing Acknowledge                */
-#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080U)       /*!< CEC Arbitration Lost                      */
-#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100U)       /*!< CEC Tx Byte Request                       */
-#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200U)       /*!< CEC End of Transmission                   */
-#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400U)       /*!< CEC Tx-Buffer Underrun                    */
-#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800U)       /*!< CEC Tx-Error                              */
-#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000U)       /*!< CEC Tx Missing Acknowledge                */
+#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                      */
+#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                      */
+#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                            */
+#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                   */
+#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error             */
+#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error              */
+#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge                */
+#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                      */
+#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                       */
+#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                   */
+#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                    */
+#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                              */
+#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge                */
 
 /*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001U)       /*!< CEC Rx-Byte Received IT Enable            */
-#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002U)       /*!< CEC End Of Reception IT Enable            */
-#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004U)       /*!< CEC Rx-Overrun IT Enable                  */
-#define  CEC_IER_BREIE                       ((uint32_t)0x00000008U)       /*!< CEC Rx Bit Rising Error IT Enable         */
-#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010U)       /*!< CEC Rx Short Bit period Error IT Enable   */
-#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020U)       /*!< CEC Rx Long Bit period Error IT Enable    */
-#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040U)       /*!< CEC Rx Missing Acknowledge IT Enable      */
-#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080U)       /*!< CEC Arbitration Lost IT Enable            */
-#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100U)       /*!< CEC Tx Byte Request  IT Enable            */
-#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200U)       /*!< CEC End of Transmission IT Enable         */
-#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400U)       /*!< CEC Tx-Buffer Underrun IT Enable          */
-#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800U)       /*!< CEC Tx-Error IT Enable                    */
-#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000U)       /*!< CEC Tx Missing Acknowledge IT Enable      */
+#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable            */
+#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable            */
+#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable                  */
+#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable         */
+#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable   */
+#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable    */
+#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable            */
+#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable            */
+#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable         */
+#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                    */
+#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable      */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2942,15 +2942,15 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2958,92 +2958,92 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002U)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000U)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable*/
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01U)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02U)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFFU)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFFU)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FFU)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00U)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3057,51 +3057,60 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001U)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002U)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004U)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008U)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010U)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020U)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040U)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080U)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800U)
-#define DCMI_CR_OUTEN                        ((uint32_t)0x00002000U)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000U)
-#define DCMI_CR_BSM_0                        ((uint32_t)0x00010000U)
-#define DCMI_CR_BSM_1                        ((uint32_t)0x00020000U)
-#define DCMI_CR_OEBS                         ((uint32_t)0x00040000U)
-#define DCMI_CR_LSM                          ((uint32_t)0x00080000U)
-#define DCMI_CR_OELS                         ((uint32_t)0x00100000U)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_OUTEN                        0x00002000U
+#define DCMI_CR_ENABLE                       0x00004000U
+#define DCMI_CR_BSM_0                        0x00010000U
+#define DCMI_CR_BSM_1                        0x00020000U
+#define DCMI_CR_OEBS                         0x00040000U
+#define DCMI_CR_LSM                          0x00080000U
+#define DCMI_CR_OELS                         0x00100000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001U)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002U)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004U)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001U)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002U)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004U)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008U)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010U)
+/********************  Bits definition for DCMI_RIS register  ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001U)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002U)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004U)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008U)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010U)
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 
 /********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   ((uint32_t)0x00000001U)
-#define DCMI_MIS_OVR_MIS                     ((uint32_t)0x00000002U)
-#define DCMI_MIS_ERR_MIS                     ((uint32_t)0x00000004U)
-#define DCMI_MIS_VSYNC_MIS                   ((uint32_t)0x00000008U)
-#define DCMI_MIS_LINE_MIS                    ((uint32_t)0x00000010U)
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
@@ -3111,40 +3120,40 @@ typedef struct
 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001U)
-#define DCMI_ICR_OVR_ISC                     ((uint32_t)0x00000002U)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004U)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008U)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010U)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
 
 /********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        ((uint32_t)0x000000FFU)
-#define DCMI_ESCR_LSC                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESCR_LEC                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESCR_FEC                        ((uint32_t)0xFF000000U)
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
 
 /********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        ((uint32_t)0x000000FFU)
-#define DCMI_ESUR_LSU                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESUR_LEU                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESUR_FEU                        ((uint32_t)0xFF000000U)
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
 
 /********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  ((uint32_t)0x00003FFFU)
-#define DCMI_CWSTRT_VST                      ((uint32_t)0x1FFF0000U)
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
 
 /********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   ((uint32_t)0x00003FFFU)
-#define DCMI_CWSIZE_VLINE                    ((uint32_t)0x3FFF0000U)
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
 
 /********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        ((uint32_t)0x000000FFU)
-#define DCMI_DR_BYTE1                        ((uint32_t)0x0000FF00U)
-#define DCMI_DR_BYTE2                        ((uint32_t)0x00FF0000U)
-#define DCMI_DR_BYTE3                        ((uint32_t)0xFF000000U)
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3152,161 +3161,161 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3315,154 +3324,154 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3470,108 +3479,108 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008U)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009U)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000AU)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000BU)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000CU)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000DU)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000EU)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000FU)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
 #define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010U)
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000U) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000U) 
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3579,709 +3588,709 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size             */
-#define  FMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000U)        /*!<Continous clock enable     */
-#define  FMC_BCR1_WFDIS                     ((uint32_t)0x00200000U)        /*!<Write FIFO Disable         */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
 
 /******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_PCR register  *******************/
-#define  FMC_PCR_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FMC_SR register  *******************/
-#define  FMC_SR_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /******************  Bit definition for FMC_PMEM register  ******************/
-#define  FMC_PMEM_MEMSET2                  ((uint32_t)0x000000FFU)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM_MEMSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMWAIT2                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM_MEMWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHOLD2                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM_MEMHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM_MEMHIZ2                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM_MEMHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM_MEMHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM_MEMHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM_MEMHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM_MEMHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM_MEMHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM_MEMHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM_MEMHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT register  ******************/
-#define  FMC_PATT_ATTSET2                  ((uint32_t)0x000000FFU)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT_ATTSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTWAIT2                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT_ATTWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHOLD2                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT_ATTHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT_ATTHIZ2                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT_ATTHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT_ATTHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT_ATTHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT_ATTHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT_ATTHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT_ATTHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT_ATTHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT_ATTHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_ECCR register  ******************/
-#define  FMC_ECCR_ECC2                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FMC_ECCR_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000U)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000U)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007U)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
                                             
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008U)        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
 
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010U)        /*!<Command target 1 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
 
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0U)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100U)        /*!<Bit 3 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
 
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00U)        /*!<MRD[12:0] bits (Mode register definition) */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
 
 /******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001U)        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
 
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFEU)        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
 
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000U)        /*!<RES interupt enable */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
 
 /******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001U)        /*!<Refresh error flag */
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
 
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006U)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004U)        /*!<Bit 1 */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
 
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018U)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020U)        /*!<Busy status */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4289,235 +4298,235 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -4537,22 +4546,22 @@ typedef struct
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -4572,57 +4581,57 @@ typedef struct
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -4630,97 +4639,97 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4728,103 +4737,101 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  *******************/
-#define  FMPI2C_CR1_PE                        ((uint32_t)0x00000001U)        /*!< Peripheral enable                   */
-#define  FMPI2C_CR1_TXIE                      ((uint32_t)0x00000002U)        /*!< TX interrupt enable                 */
-#define  FMPI2C_CR1_RXIE                      ((uint32_t)0x00000004U)        /*!< RX interrupt enable                 */
-#define  FMPI2C_CR1_ADDRIE                    ((uint32_t)0x00000008U)        /*!< Address match interrupt enable      */
-#define  FMPI2C_CR1_NACKIE                    ((uint32_t)0x00000010U)        /*!< NACK received interrupt enable      */
-#define  FMPI2C_CR1_STOPIE                    ((uint32_t)0x00000020U)        /*!< STOP detection interrupt enable     */
-#define  FMPI2C_CR1_TCIE                      ((uint32_t)0x00000040U)        /*!< Transfer complete interrupt enable  */
-#define  FMPI2C_CR1_ERRIE                     ((uint32_t)0x00000080U)        /*!< Errors interrupt enable             */
-#define  FMPI2C_CR1_DFN                       ((uint32_t)0x00000F00U)        /*!< Digital noise filter                */
-#define  FMPI2C_CR1_ANFOFF                    ((uint32_t)0x00001000U)        /*!< Analog noise filter OFF             */
-#define  FMPI2C_CR1_SWRST                     ((uint32_t)0x00002000U)        /*!< Software reset                      */
-#define  FMPI2C_CR1_TXDMAEN                   ((uint32_t)0x00004000U)        /*!< DMA transmission requests enable    */
-#define  FMPI2C_CR1_RXDMAEN                   ((uint32_t)0x00008000U)        /*!< DMA reception requests enable       */
-#define  FMPI2C_CR1_SBC                       ((uint32_t)0x00010000U)        /*!< Slave byte control                  */
-#define  FMPI2C_CR1_NOSTRETCH                 ((uint32_t)0x00020000U)        /*!< Clock stretching disable            */
-#define  FMPI2C_CR1_WUPEN                     ((uint32_t)0x00040000U)        /*!< Wakeup from STOP enable             */
-#define  FMPI2C_CR1_GCEN                      ((uint32_t)0x00080000U)        /*!< General call enable                 */
-#define  FMPI2C_CR1_SMBHEN                    ((uint32_t)0x00100000U)        /*!< SMBus host address enable           */
-#define  FMPI2C_CR1_SMBDEN                    ((uint32_t)0x00200000U)        /*!< SMBus device default address enable */
-#define  FMPI2C_CR1_ALERTEN                   ((uint32_t)0x00400000U)        /*!< SMBus alert enable                  */
-#define  FMPI2C_CR1_PECEN                     ((uint32_t)0x00800000U)        /*!< PEC enable                          */
+#define  FMPI2C_CR1_PE                        0x00000001U        /*!< Peripheral enable                   */
+#define  FMPI2C_CR1_TXIE                      0x00000002U        /*!< TX interrupt enable                 */
+#define  FMPI2C_CR1_RXIE                      0x00000004U        /*!< RX interrupt enable                 */
+#define  FMPI2C_CR1_ADDRIE                    0x00000008U        /*!< Address match interrupt enable      */
+#define  FMPI2C_CR1_NACKIE                    0x00000010U        /*!< NACK received interrupt enable      */
+#define  FMPI2C_CR1_STOPIE                    0x00000020U        /*!< STOP detection interrupt enable     */
+#define  FMPI2C_CR1_TCIE                      0x00000040U        /*!< Transfer complete interrupt enable  */
+#define  FMPI2C_CR1_ERRIE                     0x00000080U        /*!< Errors interrupt enable             */
+#define  FMPI2C_CR1_DFN                       0x00000F00U        /*!< Digital noise filter                */
+#define  FMPI2C_CR1_ANFOFF                    0x00001000U        /*!< Analog noise filter OFF             */
+#define  FMPI2C_CR1_TXDMAEN                   0x00004000U        /*!< DMA transmission requests enable    */
+#define  FMPI2C_CR1_RXDMAEN                   0x00008000U        /*!< DMA reception requests enable       */
+#define  FMPI2C_CR1_SBC                       0x00010000U        /*!< Slave byte control                  */
+#define  FMPI2C_CR1_NOSTRETCH                 0x00020000U        /*!< Clock stretching disable            */
+#define  FMPI2C_CR1_GCEN                      0x00080000U        /*!< General call enable                 */
+#define  FMPI2C_CR1_SMBHEN                    0x00100000U        /*!< SMBus host address enable           */
+#define  FMPI2C_CR1_SMBDEN                    0x00200000U        /*!< SMBus device default address enable */
+#define  FMPI2C_CR1_ALERTEN                   0x00400000U        /*!< SMBus alert enable                  */
+#define  FMPI2C_CR1_PECEN                     0x00800000U        /*!< PEC enable                          */
 
 /******************  Bit definition for I2C_CR2 register  ********************/
-#define  FMPI2C_CR2_SADD                      ((uint32_t)0x000003FFU)        /*!< Slave address (master mode)                             */
-#define  FMPI2C_CR2_RD_WRN                    ((uint32_t)0x00000400U)        /*!< Transfer direction (master mode)                        */
-#define  FMPI2C_CR2_ADD10                     ((uint32_t)0x00000800U)        /*!< 10-bit addressing mode (master mode)                    */
-#define  FMPI2C_CR2_HEAD10R                   ((uint32_t)0x00001000U)        /*!< 10-bit address header only read direction (master mode) */
-#define  FMPI2C_CR2_START                     ((uint32_t)0x00002000U)        /*!< START generation                                        */
-#define  FMPI2C_CR2_STOP                      ((uint32_t)0x00004000U)        /*!< STOP generation (master mode)                           */
-#define  FMPI2C_CR2_NACK                      ((uint32_t)0x00008000U)        /*!< NACK generation (slave mode)                            */
-#define  FMPI2C_CR2_NBYTES                    ((uint32_t)0x00FF0000U)        /*!< Number of bytes                                         */
-#define  FMPI2C_CR2_RELOAD                    ((uint32_t)0x01000000U)        /*!< NBYTES reload mode                                      */
-#define  FMPI2C_CR2_AUTOEND                   ((uint32_t)0x02000000U)        /*!< Automatic end mode (master mode)                        */
-#define  FMPI2C_CR2_PECBYTE                   ((uint32_t)0x04000000U)        /*!< Packet error checking byte                              */
+#define  FMPI2C_CR2_SADD                      0x000003FFU        /*!< Slave address (master mode)                             */
+#define  FMPI2C_CR2_RD_WRN                    0x00000400U        /*!< Transfer direction (master mode)                        */
+#define  FMPI2C_CR2_ADD10                     0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
+#define  FMPI2C_CR2_HEAD10R                   0x00001000U        /*!< 10-bit address header only read direction (master mode) */
+#define  FMPI2C_CR2_START                     0x00002000U        /*!< START generation                                        */
+#define  FMPI2C_CR2_STOP                      0x00004000U        /*!< STOP generation (master mode)                           */
+#define  FMPI2C_CR2_NACK                      0x00008000U        /*!< NACK generation (slave mode)                            */
+#define  FMPI2C_CR2_NBYTES                    0x00FF0000U        /*!< Number of bytes                                         */
+#define  FMPI2C_CR2_RELOAD                    0x01000000U        /*!< NBYTES reload mode                                      */
+#define  FMPI2C_CR2_AUTOEND                   0x02000000U        /*!< Automatic end mode (master mode)                        */
+#define  FMPI2C_CR2_PECBYTE                   0x04000000U        /*!< Packet error checking byte                              */
 
 /*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  FMPI2C_OAR1_OA1                      ((uint32_t)0x000003FFU)        /*!< Interface own address 1   */
-#define  FMPI2C_OAR1_OA1MODE                  ((uint32_t)0x00000400U)        /*!< Own address 1 10-bit mode */
-#define  FMPI2C_OAR1_OA1EN                    ((uint32_t)0x00008000U)        /*!< Own address 1 enable      */
+#define  FMPI2C_OAR1_OA1                      0x000003FFU        /*!< Interface own address 1   */
+#define  FMPI2C_OAR1_OA1MODE                  0x00000400U        /*!< Own address 1 10-bit mode */
+#define  FMPI2C_OAR1_OA1EN                    0x00008000U        /*!< Own address 1 enable      */
 
 /*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  FMPI2C_OAR2_OA2                      ((uint32_t)0x000000FEU)        /*!< Interface own address 2 */
-#define  FMPI2C_OAR2_OA2MSK                   ((uint32_t)0x00000700U)        /*!< Own address 2 masks     */
-#define  FMPI2C_OAR2_OA2EN                    ((uint32_t)0x00008000U)        /*!< Own address 2 enable    */
+#define  FMPI2C_OAR2_OA2                      0x000000FEU        /*!< Interface own address 2 */
+#define  FMPI2C_OAR2_OA2MSK                   0x00000700U        /*!< Own address 2 masks     */
+#define  FMPI2C_OAR2_OA2EN                    0x00008000U        /*!< Own address 2 enable    */
 
 /*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  FMPI2C_TIMINGR_SCLL                  ((uint32_t)0x000000FFU)        /*!< SCL low period (master mode)  */
-#define  FMPI2C_TIMINGR_SCLH                  ((uint32_t)0x0000FF00U)        /*!< SCL high period (master mode) */
-#define  FMPI2C_TIMINGR_SDADEL                ((uint32_t)0x000F0000U)        /*!< Data hold time                */
-#define  FMPI2C_TIMINGR_SCLDEL                ((uint32_t)0x00F00000U)        /*!< Data setup time               */
-#define  FMPI2C_TIMINGR_PRESC                 ((uint32_t)0xF0000000U)        /*!< Timings prescaler             */
+#define  FMPI2C_TIMINGR_SCLL                  0x000000FFU        /*!< SCL low period (master mode)  */
+#define  FMPI2C_TIMINGR_SCLH                  0x0000FF00U        /*!< SCL high period (master mode) */
+#define  FMPI2C_TIMINGR_SDADEL                0x000F0000U        /*!< Data hold time                */
+#define  FMPI2C_TIMINGR_SCLDEL                0x00F00000U        /*!< Data setup time               */
+#define  FMPI2C_TIMINGR_PRESC                 0xF0000000U        /*!< Timings prescaler             */
 
 /******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  FMPI2C_TIMEOUTR_TIMEOUTA             ((uint32_t)0x00000FFFU)        /*!< Bus timeout A                 */
-#define  FMPI2C_TIMEOUTR_TIDLE                ((uint32_t)0x00001000U)        /*!< Idle clock timeout detection  */
-#define  FMPI2C_TIMEOUTR_TIMOUTEN             ((uint32_t)0x00008000U)        /*!< Clock timeout enable          */
-#define  FMPI2C_TIMEOUTR_TIMEOUTB             ((uint32_t)0x0FFF0000U)        /*!< Bus timeout B                 */
-#define  FMPI2C_TIMEOUTR_TEXTEN               ((uint32_t)0x80000000U)        /*!< Extended clock timeout enable */
+#define  FMPI2C_TIMEOUTR_TIMEOUTA             0x00000FFFU        /*!< Bus timeout A                 */
+#define  FMPI2C_TIMEOUTR_TIDLE                0x00001000U        /*!< Idle clock timeout detection  */
+#define  FMPI2C_TIMEOUTR_TIMOUTEN             0x00008000U        /*!< Clock timeout enable          */
+#define  FMPI2C_TIMEOUTR_TIMEOUTB             0x0FFF0000U        /*!< Bus timeout B                 */
+#define  FMPI2C_TIMEOUTR_TEXTEN               0x80000000U        /*!< Extended clock timeout enable */
 
 /******************  Bit definition for I2C_ISR register  *********************/
-#define  FMPI2C_ISR_TXE                       ((uint32_t)0x00000001U)        /*!< Transmit data register empty     */
-#define  FMPI2C_ISR_TXIS                      ((uint32_t)0x00000002U)        /*!< Transmit interrupt status        */
-#define  FMPI2C_ISR_RXNE                      ((uint32_t)0x00000004U)        /*!< Receive data register not empty  */
-#define  FMPI2C_ISR_ADDR                      ((uint32_t)0x00000008U)        /*!< Address matched (slave mode)     */
-#define  FMPI2C_ISR_NACKF                     ((uint32_t)0x00000010U)        /*!< NACK received flag               */
-#define  FMPI2C_ISR_STOPF                     ((uint32_t)0x00000020U)        /*!< STOP detection flag              */
-#define  FMPI2C_ISR_TC                        ((uint32_t)0x00000040U)        /*!< Transfer complete (master mode)  */
-#define  FMPI2C_ISR_TCR                       ((uint32_t)0x00000080U)        /*!< Transfer complete reload         */
-#define  FMPI2C_ISR_BERR                      ((uint32_t)0x00000100U)        /*!< Bus error                        */
-#define  FMPI2C_ISR_ARLO                      ((uint32_t)0x00000200U)        /*!< Arbitration lost                 */
-#define  FMPI2C_ISR_OVR                       ((uint32_t)0x00000400U)        /*!< Overrun/Underrun                 */
-#define  FMPI2C_ISR_PECERR                    ((uint32_t)0x00000800U)        /*!< PEC error in reception           */
-#define  FMPI2C_ISR_TIMEOUT                   ((uint32_t)0x00001000U)        /*!< Timeout or Tlow detection flag   */
-#define  FMPI2C_ISR_ALERT                     ((uint32_t)0x00002000U)        /*!< SMBus alert                      */
-#define  FMPI2C_ISR_BUSY                      ((uint32_t)0x00008000U)        /*!< Bus busy                         */
-#define  FMPI2C_ISR_DIR                       ((uint32_t)0x00010000U)        /*!< Transfer direction (slave mode)  */
-#define  FMPI2C_ISR_ADDCODE                   ((uint32_t)0x00FE0000U)        /*!< Address match code (slave mode)  */
+#define  FMPI2C_ISR_TXE                       0x00000001U        /*!< Transmit data register empty     */
+#define  FMPI2C_ISR_TXIS                      0x00000002U        /*!< Transmit interrupt status        */
+#define  FMPI2C_ISR_RXNE                      0x00000004U        /*!< Receive data register not empty  */
+#define  FMPI2C_ISR_ADDR                      0x00000008U        /*!< Address matched (slave mode)     */
+#define  FMPI2C_ISR_NACKF                     0x00000010U        /*!< NACK received flag               */
+#define  FMPI2C_ISR_STOPF                     0x00000020U        /*!< STOP detection flag              */
+#define  FMPI2C_ISR_TC                        0x00000040U        /*!< Transfer complete (master mode)  */
+#define  FMPI2C_ISR_TCR                       0x00000080U        /*!< Transfer complete reload         */
+#define  FMPI2C_ISR_BERR                      0x00000100U        /*!< Bus error                        */
+#define  FMPI2C_ISR_ARLO                      0x00000200U        /*!< Arbitration lost                 */
+#define  FMPI2C_ISR_OVR                       0x00000400U        /*!< Overrun/Underrun                 */
+#define  FMPI2C_ISR_PECERR                    0x00000800U        /*!< PEC error in reception           */
+#define  FMPI2C_ISR_TIMEOUT                   0x00001000U        /*!< Timeout or Tlow detection flag   */
+#define  FMPI2C_ISR_ALERT                     0x00002000U        /*!< SMBus alert                      */
+#define  FMPI2C_ISR_BUSY                      0x00008000U        /*!< Bus busy                         */
+#define  FMPI2C_ISR_DIR                       0x00010000U        /*!< Transfer direction (slave mode)  */
+#define  FMPI2C_ISR_ADDCODE                   0x00FE0000U        /*!< Address match code (slave mode)  */
 
 /******************  Bit definition for I2C_ICR register  *********************/
-#define  FMPI2C_ICR_ADDRCF                    ((uint32_t)0x00000008U)        /*!< Address matched clear flag  */
-#define  FMPI2C_ICR_NACKCF                    ((uint32_t)0x00000010U)        /*!< NACK clear flag             */
-#define  FMPI2C_ICR_STOPCF                    ((uint32_t)0x00000020U)        /*!< STOP detection clear flag   */
-#define  FMPI2C_ICR_BERRCF                    ((uint32_t)0x00000100U)        /*!< Bus error clear flag        */
-#define  FMPI2C_ICR_ARLOCF                    ((uint32_t)0x00000200U)        /*!< Arbitration lost clear flag */
-#define  FMPI2C_ICR_OVRCF                     ((uint32_t)0x00000400U)        /*!< Overrun/Underrun clear flag */
-#define  FMPI2C_ICR_PECCF                     ((uint32_t)0x00000800U)        /*!< PAC error clear flag        */
-#define  FMPI2C_ICR_TIMOUTCF                  ((uint32_t)0x00001000U)        /*!< Timeout clear flag          */
-#define  FMPI2C_ICR_ALERTCF                   ((uint32_t)0x00002000U)        /*!< Alert clear flag            */
+#define  FMPI2C_ICR_ADDRCF                    0x00000008U        /*!< Address matched clear flag  */
+#define  FMPI2C_ICR_NACKCF                    0x00000010U        /*!< NACK clear flag             */
+#define  FMPI2C_ICR_STOPCF                    0x00000020U        /*!< STOP detection clear flag   */
+#define  FMPI2C_ICR_BERRCF                    0x00000100U        /*!< Bus error clear flag        */
+#define  FMPI2C_ICR_ARLOCF                    0x00000200U        /*!< Arbitration lost clear flag */
+#define  FMPI2C_ICR_OVRCF                     0x00000400U        /*!< Overrun/Underrun clear flag */
+#define  FMPI2C_ICR_PECCF                     0x00000800U        /*!< PAC error clear flag        */
+#define  FMPI2C_ICR_TIMOUTCF                  0x00001000U        /*!< Timeout clear flag          */
+#define  FMPI2C_ICR_ALERTCF                   0x00002000U        /*!< Alert clear flag            */
 
 /******************  Bit definition for I2C_PECR register  *********************/
-#define  FMPI2C_PECR_PEC                      ((uint32_t)0x000000FFU)        /*!< PEC register */
+#define  FMPI2C_PECR_PEC                      0x000000FFU        /*!< PEC register */
 
 /******************  Bit definition for I2C_RXDR register  *********************/
-#define  FMPI2C_RXDR_RXDATA                   ((uint32_t)0x000000FFU)        /*!< 8-bit receive data */
+#define  FMPI2C_RXDR_RXDATA                   0x000000FFU        /*!< 8-bit receive data */
 
 /******************  Bit definition for I2C_TXDR register  *********************/
-#define  FMPI2C_TXDR_TXDATA                   ((uint32_t)0x000000FFU)        /*!< 8-bit transmit data */
+#define  FMPI2C_TXDR_TXDATA                   0x000000FFU        /*!< 8-bit transmit data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4832,20 +4839,20 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -4854,41 +4861,41 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000U)     /*!< Over Drive enable                     */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000U)     /*!< Over Drive switch enabled             */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000U)     /*!< Under Drive enable in stop mode       */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000U)     /*!< Bit 0                                 */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000U)     /*!< Bit 1                                 */
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000U)     /*!< Flash Memory Sleep System Run         */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000U)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                     */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled             */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode       */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                                 */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                                 */
+#define  PWR_CR_FMSSR                        0x00100000U     /*!< Flash Memory Sleep System Run         */
+#define  PWR_CR_FISSR                        0x00200000U     /*!< Flash Interface Stop while System Run */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
@@ -4896,17 +4903,17 @@ typedef struct
 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000080U)     /*!< Enable WKUP pin 2                                */
-#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100U)     /*!< Enable WKUP pin 1                                */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000U)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000U)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000U)     /*!< Under Drive ready                                */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP2                       0x00000080U     /*!< Enable WKUP pin 2                                */
+#define  PWR_CSR_EWUP1                       0x00000100U     /*!< Enable WKUP pin 1                                */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -4917,133 +4924,133 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*****************  Bit definition for QUADSPI_CR register  *******************/
-#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001U)            /*!< Enable                             */
-#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002U)            /*!< Abort request                      */
-#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004U)            /*!< DMA Enable                         */
-#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008U)            /*!< Timeout Counter Enable             */
-#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000010U)            /*!< SSHIFT Sample Shift                */
-#define  QUADSPI_CR_DFM                          ((uint32_t)0x00000040U)            /*!< Dual Flash Mode                    */
-#define  QUADSPI_CR_FSEL                         ((uint32_t)0x00000080U)            /*!< Flash Select                       */
-#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00001F00U)            /*!< FTHRES[3:0] FIFO Level             */
-#define  QUADSPI_CR_FTHRES_0                     ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CR_FTHRES_1                     ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CR_FTHRES_2                     ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_CR_FTHRES_3                     ((uint32_t)0x00000800U)            /*!< Bit 3 */
-#define  QUADSPI_CR_FTHRES_4                     ((uint32_t)0x00001000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000U)            /*!< Transfer Error Interrupt Enable    */
-#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000U)            /*!< Transfer Complete Interrupt Enable */
-#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000U)            /*!< FIFO Threshold Interrupt Enable    */
-#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000U)            /*!< Status Match Interrupt Enable      */
-#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000U)            /*!< TimeOut Interrupt Enable           */
-#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000U)            /*!< Polling Match Mode                 */
-#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000U)            /*!< PRESCALER[7:0] Clock prescaler     */
-#define  QUADSPI_CR_PRESCALER_0                  ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CR_PRESCALER_1                  ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CR_PRESCALER_2                  ((uint32_t)0x04000000U)            /*!< Bit 2 */
-#define  QUADSPI_CR_PRESCALER_3                  ((uint32_t)0x08000000U)            /*!< Bit 3 */
-#define  QUADSPI_CR_PRESCALER_4                  ((uint32_t)0x10000000U)            /*!< Bit 4 */
-#define  QUADSPI_CR_PRESCALER_5                  ((uint32_t)0x20000000U)            /*!< Bit 5 */
-#define  QUADSPI_CR_PRESCALER_6                  ((uint32_t)0x40000000U)            /*!< Bit 6 */
-#define  QUADSPI_CR_PRESCALER_7                  ((uint32_t)0x80000000U)            /*!< Bit 7 */
+#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                             */
+#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                      */
+#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                         */
+#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable             */
+#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< SSHIFT Sample Shift                */
+#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                    */
+#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                       */
+#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[3:0] FIFO Level             */
+#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
+#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
+#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
 
 /*****************  Bit definition for QUADSPI_DCR register  ******************/
-#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001U)            /*!< Mode 0 / Mode 3                 */
-#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700U)            /*!< CSHT[2:0]: ChipSelect High Time */
-#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000U)            /*!< FSIZE[4:0]: Flash Size          */
-#define  QUADSPI_DCR_FSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_DCR_FSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_DCR_FSIZE_2                     ((uint32_t)0x00040000U)            /*!< Bit 2 */
-#define  QUADSPI_DCR_FSIZE_3                     ((uint32_t)0x00080000U)            /*!< Bit 3 */
-#define  QUADSPI_DCR_FSIZE_4                     ((uint32_t)0x00100000U)            /*!< Bit 4 */
+#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
 
 /******************  Bit definition for QUADSPI_SR register  *******************/
-#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001U)             /*!< Transfer Error Flag    */
-#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002U)             /*!< Transfer Complete Flag */
-#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008U)             /*!< Status Match Flag      */
-#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010U)             /*!< Timeout Flag           */
-#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020U)             /*!< Busy                   */
-#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00003F00U)             /*!< FIFO Threshlod Flag    */
-#define  QUADSPI_SR_FLEVEL_0                     ((uint32_t)0x00000100U)             /*!< Bit 0 */
-#define  QUADSPI_SR_FLEVEL_1                     ((uint32_t)0x00000200U)             /*!< Bit 1 */
-#define  QUADSPI_SR_FLEVEL_2                     ((uint32_t)0x00000400U)             /*!< Bit 2 */
-#define  QUADSPI_SR_FLEVEL_3                     ((uint32_t)0x00000800U)             /*!< Bit 3 */
-#define  QUADSPI_SR_FLEVEL_4                     ((uint32_t)0x00001000U)             /*!< Bit 4 */
-#define  QUADSPI_SR_FLEVEL_5                     ((uint32_t)0x00002000U)             /*!< Bit 5 */
+#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       0x00003F00U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
+#define  QUADSPI_SR_FLEVEL_5                     0x00002000U             /*!< Bit 5 */
 
 /******************  Bit definition for QUADSPI_FCR register  ******************/
-#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001U)             /*!< Clear Transfer Error Flag    */
-#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002U)             /*!< Clear Transfer Complete Flag */
-#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008U)             /*!< Clear Status Match Flag      */
-#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010U)             /*!< Clear Timeout Flag           */
+#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
 
 /******************  Bit definition for QUADSPI_DLR register  ******************/
-#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFFU)               /*!< DL[31:0]: Data Length */
+#define  QUADSPI_DLR_DL                        0xFFFFFFFFU               /*!< DL[31:0]: Data Length */
 
 /******************  Bit definition for QUADSPI_CCR register  ******************/
-#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FFU)            /*!< INSTRUCTION[7:0]: Instruction */
-#define  QUADSPI_CCR_INSTRUCTION_0                ((uint32_t)0x00000001U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_INSTRUCTION_1                ((uint32_t)0x00000002U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_INSTRUCTION_2                ((uint32_t)0x00000004U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_INSTRUCTION_3                ((uint32_t)0x00000008U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_INSTRUCTION_4                ((uint32_t)0x00000010U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_INSTRUCTION_5                ((uint32_t)0x00000020U)            /*!< Bit 5 */
-#define  QUADSPI_CCR_INSTRUCTION_6                ((uint32_t)0x00000040U)            /*!< Bit 6 */
-#define  QUADSPI_CCR_INSTRUCTION_7                ((uint32_t)0x00000080U)            /*!< Bit 7 */
-#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300U)            /*!< IMODE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00U)            /*!< ADMODE[1:0]: Address Mode         */
-#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000U)            /*!< ADSIZE[1:0]: Address Size         */
-#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000U)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
-#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000U)            /*!< ABSIZE[1:0]: Instruction Mode     */
-#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000U)            /*!< DCYC[4:0]: Dummy Cycles           */
-#define  QUADSPI_CCR_DCYC_0                       ((uint32_t)0x00040000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DCYC_1                       ((uint32_t)0x00080000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_DCYC_2                       ((uint32_t)0x00100000U)            /*!< Bit 2 */
-#define  QUADSPI_CCR_DCYC_3                       ((uint32_t)0x00200000U)            /*!< Bit 3 */
-#define  QUADSPI_CCR_DCYC_4                       ((uint32_t)0x00400000U)            /*!< Bit 4 */
-#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000U)            /*!< DMODE[1:0]: Data Mode                */
-#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000U)            /*!< FMODE[1:0]: Functional Mode           */
-#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000U)            /*!< Bit 0 */
-#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000U)            /*!< Bit 1 */
-#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000U)            /*!< SIOO: Send Instruction Only Once Mode */
-#define  QUADSPI_CCR_DHHC                         ((uint32_t)0x40000000U)            /*!< DHHC: Delay Half Hclk Cycle           */
-#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000U)            /*!< DDRM: Double Data Rate Mode           */ 
+#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction */
+#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode                */
+#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode           */
+#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
 /******************  Bit definition for QUADSPI_AR register  *******************/
-#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFFU)            /*!< ADDRESS[31:0]: Address                */
+#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address                */
 
 /******************  Bit definition for QUADSPI_ABR register  ******************/
-#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFFU)            /*!< ALTERNATE[31:0]: Alternate Bytes      */
+#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes      */
 
 /******************  Bit definition for QUADSPI_DR register  *******************/
-#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFFU)            /*!< DATA[31:0]: Data                      */
+#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data                      */
 
 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
-#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFFU)            /*!< MASK[31:0]: Status Mask               */
+#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask               */
 
 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
-#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFFU)            /*!< MATCH[31:0]: Status Match             */
+#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match             */
 
 /******************  Bit definition for QUADSPI_PIR register  *****************/
-#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFFU)            /*!< INTERVAL[15:0]: Polling Interval      */
+#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval      */
 
 /******************  Bit definition for QUADSPI_LPTR register  *****************/
-#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFFU)            /*!< TIMEOUT[15:0]: Timeout period         */
+#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period         */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5051,543 +5058,543 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000U)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
-#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x70000000U)
-#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x10000000U)
-#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x20000000U)
-#define  RCC_PLLCFGR_PLLR_2                  ((uint32_t)0x40000000U)
+#define  RCC_PLLCFGR_PLLR                    0x70000000U
+#define  RCC_PLLCFGR_PLLR_0                  0x10000000U
+#define  RCC_PLLCFGR_PLLR_1                  0x20000000U
+#define  RCC_PLLCFGR_PLLR_2                  0x40000000U
 
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock      */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock      */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL/PLLP selected as system clock */
-#define  RCC_CFGR_SW_PLLR                    ((uint32_t)0x00000003U)        /*!< PLL/PLLR selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock      */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock      */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL/PLLP selected as system clock */
+#define  RCC_CFGR_SW_PLLR                    0x00000003U        /*!< PLL/PLLR selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL/PLLP used as system clock       */
-#define  RCC_CFGR_SWS_PLLR                   ((uint32_t)0x0000000CU)        /*!< PLL/PLLR used as system clock       */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL/PLLP used as system clock       */
+#define  RCC_CFGR_SWS_PLLR                   0x0000000CU        /*!< PLL/PLLR used as system clock       */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040U)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000U)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000U)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB3RSTR_QSPIRST               ((uint32_t)0x00000002U)
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
+#define  RCC_AHB3RSTR_QSPIRST               0x00000002U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040U)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080U)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_SPDIFRXRST             ((uint32_t)0x00010000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_FMPI2C1RST             ((uint32_t)0x01000000U)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000U)
-#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x08000000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_FMPI2C1RST             0x01000000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_CECRST                 0x08000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000U)
-#define  RCC_APB2RSTR_SAI2RST                ((uint32_t)0x00800000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_SAI2RST                0x00800000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
 
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000U)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000U)
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB3ENR_QSPIEN                 ((uint32_t)0x00000002U)
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040U)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080U)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_SPDIFRXEN               ((uint32_t)0x00010000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_FMPI2C1EN               ((uint32_t)0x01000000U)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000U)
-#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x08000000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_FMPI2C1EN               0x01000000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_CECEN                   0x08000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200U)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB2ENR_SAI2EN                  ((uint32_t)0x00800000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_SAI2EN                  0x00800000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
 
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
 
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000U)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000U)
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB3LPENR_QSPILPEN             ((uint32_t)0x00000002U)
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
+#define  RCC_AHB3LPENR_QSPILPEN             0x00000002U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010U)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020U)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040U)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080U)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_SPDIFRXLPEN           ((uint32_t)0x00010000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000U)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000U)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_FMPI2C1LPEN           ((uint32_t)0x01000000U)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000U)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB1LPENR_CECLPEN               ((uint32_t)0x08000000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_FMPI2C1LPEN           0x01000000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_CECLPEN               0x08000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200U)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB2LPENR_SAI2LPEN              ((uint32_t)0x00800000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEMOD                     0x00000008U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLI2SCFGR_PLLI2SM              0x0000003FU
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            0x00000001U
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            0x00000002U
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            0x00000004U
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            0x00000008U
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            0x00000010U
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            0x00000020U
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SP              ((uint32_t)0x00030000U)
-#define  RCC_PLLI2SCFGR_PLLI2SP_0            ((uint32_t)0x00010000U)
-#define  RCC_PLLI2SCFGR_PLLI2SP_1            ((uint32_t)0x00020000U)
+#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 
 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIM              ((uint32_t)0x0000003FU)
-#define  RCC_PLLSAICFGR_PLLSAIM_0            ((uint32_t)0x00000001U)
-#define  RCC_PLLSAICFGR_PLLSAIM_1            ((uint32_t)0x00000002U)
-#define  RCC_PLLSAICFGR_PLLSAIM_2            ((uint32_t)0x00000004U)
-#define  RCC_PLLSAICFGR_PLLSAIM_3            ((uint32_t)0x00000008U)
-#define  RCC_PLLSAICFGR_PLLSAIM_4            ((uint32_t)0x00000010U)
-#define  RCC_PLLSAICFGR_PLLSAIM_5            ((uint32_t)0x00000020U)
+#define  RCC_PLLSAICFGR_PLLSAIM              0x0000003FU
+#define  RCC_PLLSAICFGR_PLLSAIM_0            0x00000001U
+#define  RCC_PLLSAICFGR_PLLSAIM_1            0x00000002U
+#define  RCC_PLLSAICFGR_PLLSAIM_2            0x00000004U
+#define  RCC_PLLSAICFGR_PLLSAIM_3            0x00000008U
+#define  RCC_PLLSAICFGR_PLLSAIM_4            0x00000010U
+#define  RCC_PLLSAICFGR_PLLSAIM_5            0x00000020U
 
-#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
 
-#define  RCC_PLLSAICFGR_PLLSAIP              ((uint32_t)0x00030000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_0            ((uint32_t)0x00010000U)
-#define  RCC_PLLSAICFGR_PLLSAIP_1            ((uint32_t)0x00020000U)
+#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
+#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
+#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
 
-#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001FU)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00U)
-#define  RCC_DCKCFGR_SAI1SRC                 ((uint32_t)0x00300000U)
-#define  RCC_DCKCFGR_SAI1SRC_0               ((uint32_t)0x00100000U)
-#define  RCC_DCKCFGR_SAI1SRC_1               ((uint32_t)0x00200000U)
-#define  RCC_DCKCFGR_SAI2SRC                 ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR_SAI2SRC_0               ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR_SAI2SRC_1               ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000U)
-#define  RCC_DCKCFGR_I2S1SRC                 ((uint32_t)0x06000000U)
-#define  RCC_DCKCFGR_I2S1SRC_0               ((uint32_t)0x02000000U)
-#define  RCC_DCKCFGR_I2S1SRC_1               ((uint32_t)0x04000000U)
-#define  RCC_DCKCFGR_I2S2SRC                 ((uint32_t)0x18000000U)
-#define  RCC_DCKCFGR_I2S2SRC_0               ((uint32_t)0x08000000U)
-#define  RCC_DCKCFGR_I2S2SRC_1               ((uint32_t)0x10000000U)
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_SAI1SRC                 0x00300000U
+#define  RCC_DCKCFGR_SAI1SRC_0               0x00100000U
+#define  RCC_DCKCFGR_SAI1SRC_1               0x00200000U
+#define  RCC_DCKCFGR_SAI2SRC                 0x00C00000U
+#define  RCC_DCKCFGR_SAI2SRC_0               0x00400000U
+#define  RCC_DCKCFGR_SAI2SRC_1               0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
+#define  RCC_DCKCFGR_I2S1SRC                 0x06000000U
+#define  RCC_DCKCFGR_I2S1SRC_0               0x02000000U
+#define  RCC_DCKCFGR_I2S1SRC_1               0x04000000U
+#define  RCC_DCKCFGR_I2S2SRC                 0x18000000U
+#define  RCC_DCKCFGR_I2S2SRC_0               0x08000000U
+#define  RCC_DCKCFGR_I2S2SRC_1               0x10000000U
 
 /********************  Bit definition for RCC_CKGATENR register  ***************/
-#define  RCC_CKGATENR_AHB2APB1_CKEN          ((uint32_t)0x00000001U)
-#define  RCC_CKGATENR_AHB2APB2_CKEN          ((uint32_t)0x00000002U)
-#define  RCC_CKGATENR_CM4DBG_CKEN            ((uint32_t)0x00000004U)
-#define  RCC_CKGATENR_SPARE_CKEN             ((uint32_t)0x00000008U)
-#define  RCC_CKGATENR_SRAM_CKEN              ((uint32_t)0x00000010U)
-#define  RCC_CKGATENR_FLITF_CKEN             ((uint32_t)0x00000020U)
-#define  RCC_CKGATENR_RCC_CKEN               ((uint32_t)0x00000040U)
+#define  RCC_CKGATENR_AHB2APB1_CKEN          0x00000001U
+#define  RCC_CKGATENR_AHB2APB2_CKEN          0x00000002U
+#define  RCC_CKGATENR_CM4DBG_CKEN            0x00000004U
+#define  RCC_CKGATENR_SPARE_CKEN             0x00000008U
+#define  RCC_CKGATENR_SRAM_CKEN              0x00000010U
+#define  RCC_CKGATENR_FLITF_CKEN             0x00000020U
+#define  RCC_CKGATENR_RCC_CKEN               0x00000040U
 
 /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
-#define  RCC_DCKCFGR2_FMPI2C1SEL             ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_0           ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR2_FMPI2C1SEL_1           ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR2_CECSEL                 ((uint32_t)0x04000000U)
-#define  RCC_DCKCFGR2_CK48MSEL               ((uint32_t)0x08000000U)
-#define  RCC_DCKCFGR2_SDIOSEL                ((uint32_t)0x10000000U)
-#define  RCC_DCKCFGR2_SPDIFRXSEL             ((uint32_t)0x20000000U)
+#define  RCC_DCKCFGR2_FMPI2C1SEL             0x00C00000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_0           0x00400000U
+#define  RCC_DCKCFGR2_FMPI2C1SEL_1           0x00800000U
+#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
+#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
+#define  RCC_DCKCFGR2_SDIOSEL                0x10000000U
+#define  RCC_DCKCFGR2_SPDIFRXSEL             0x20000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5595,379 +5602,379 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -5975,150 +5982,152 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003U)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
 
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030U)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
 
 /*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003U)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
 
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000CU)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
 
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0U)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080U)        /*!<Bit 2 */
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
 
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100U)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200U)        /*!<ClocK STRobing edge      */
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
 
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00U)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
 
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000U)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000U)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000U)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000U)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000U)        /*!<No Divider Configuration   */
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
 
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000U)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000U)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000U)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000U)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000U)        /*!<Bit 3  */
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
 
 /*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007U)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
 
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008U)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010U)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020U)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040U)        /*!<Muate value                      */
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
 
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80U)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100U)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200U)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400U)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800U)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000U)        /*!<Bit 5 */
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000U)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
 
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000U)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000U)        /*!<Bit 1 */
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
 
 /******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FFU)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
 
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00U)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000U)        /*!<Bit 6 */
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
 
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000U)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000U)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000U)        /*!<Frame Synchronization OFFset      */
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
 
 /******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001FU)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010U)        /*!<Bit 4 */
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
 
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0U)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
 
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00U)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
 
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000U)        /*!<SLOTEN[15:0] (Slot Enable)  */
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
 
 /*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001U)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002U)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004U)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008U)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010U)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020U)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040U)        /*!<Late frame synchronization detection interrupt enable          */
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
 
 /********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001U)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002U)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004U)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008U)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010U)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020U)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040U)         /*!<Late frame synchronization detection           */
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
 
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000U)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000U)         /*!<Bit 2 */
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
 
 /******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001U)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002U)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004U)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008U)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010U)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020U)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040U)        /*!<Clear Late frame synchronization detection           */
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
 
 /******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFFU)        
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
 
 /******************************************************************************/
 /*                                                                            */
@@ -6126,75 +6135,75 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SPDIFRX_CR register  *******************/
-#define  SPDIFRX_CR_SPDIFEN                  ((uint32_t)0x00000003U)        /*!<Peripheral Block Enable                      */
-#define  SPDIFRX_CR_RXDMAEN                  ((uint32_t)0x00000004U)        /*!<Receiver DMA Enable for data flow            */
-#define  SPDIFRX_CR_RXSTEO                   ((uint32_t)0x00000008U)        /*!<Stereo Mode                                  */
-#define  SPDIFRX_CR_DRFMT                    ((uint32_t)0x00000030U)        /*!<RX Data format                               */
-#define  SPDIFRX_CR_PMSK                     ((uint32_t)0x00000040U)        /*!<Mask Parity error bit                        */
-#define  SPDIFRX_CR_VMSK                     ((uint32_t)0x00000080U)        /*!<Mask of Validity bit                         */
-#define  SPDIFRX_CR_CUMSK                    ((uint32_t)0x00000100U)        /*!<Mask of channel status and user bits         */
-#define  SPDIFRX_CR_PTMSK                    ((uint32_t)0x00000200U)        /*!<Mask of Preamble Type bits                   */
-#define  SPDIFRX_CR_CBDMAEN                  ((uint32_t)0x00000400U)        /*!<Control Buffer DMA ENable for control flow   */
-#define  SPDIFRX_CR_CHSEL                    ((uint32_t)0x00000800U)        /*!<Channel Selection                            */
-#define  SPDIFRX_CR_NBTR                     ((uint32_t)0x00003000U)        /*!<Maximum allowed re-tries during synchronization phase */
-#define  SPDIFRX_CR_WFA                      ((uint32_t)0x00004000U)        /*!<Wait For Activity     */
-#define  SPDIFRX_CR_INSEL                    ((uint32_t)0x00070000U)        /*!<SPDIFRX input selection */
+#define  SPDIFRX_CR_SPDIFEN                  0x00000003U        /*!<Peripheral Block Enable                      */
+#define  SPDIFRX_CR_RXDMAEN                  0x00000004U        /*!<Receiver DMA Enable for data flow            */
+#define  SPDIFRX_CR_RXSTEO                   0x00000008U        /*!<Stereo Mode                                  */
+#define  SPDIFRX_CR_DRFMT                    0x00000030U        /*!<RX Data format                               */
+#define  SPDIFRX_CR_PMSK                     0x00000040U        /*!<Mask Parity error bit                        */
+#define  SPDIFRX_CR_VMSK                     0x00000080U        /*!<Mask of Validity bit                         */
+#define  SPDIFRX_CR_CUMSK                    0x00000100U        /*!<Mask of channel status and user bits         */
+#define  SPDIFRX_CR_PTMSK                    0x00000200U        /*!<Mask of Preamble Type bits                   */
+#define  SPDIFRX_CR_CBDMAEN                  0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
+#define  SPDIFRX_CR_CHSEL                    0x00000800U        /*!<Channel Selection                            */
+#define  SPDIFRX_CR_NBTR                     0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
+#define  SPDIFRX_CR_WFA                      0x00004000U        /*!<Wait For Activity     */
+#define  SPDIFRX_CR_INSEL                    0x00070000U        /*!<SPDIFRX input selection */
 
 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
-#define  SPDIFRX_IMR_RXNEIE                   ((uint32_t)0x00000001U)        /*!<RXNE interrupt enable                              */
-#define  SPDIFRX_IMR_CSRNEIE                  ((uint32_t)0x00000002U)        /*!<Control Buffer Ready Interrupt Enable              */
-#define  SPDIFRX_IMR_PERRIE                   ((uint32_t)0x00000004U)        /*!<Parity error interrupt enable                      */
-#define  SPDIFRX_IMR_OVRIE                    ((uint32_t)0x00000008U)        /*!<Overrun error Interrupt Enable                     */
-#define  SPDIFRX_IMR_SBLKIE                   ((uint32_t)0x00000010U)        /*!<Synchronization Block Detected Interrupt Enable    */
-#define  SPDIFRX_IMR_SYNCDIE                  ((uint32_t)0x00000020U)        /*!<Synchronization Done                               */
-#define  SPDIFRX_IMR_IFEIE                    ((uint32_t)0x00000040U)        /*!<Serial Interface Error Interrupt Enable            */
+#define  SPDIFRX_IMR_RXNEIE                   0x00000001U        /*!<RXNE interrupt enable                              */
+#define  SPDIFRX_IMR_CSRNEIE                  0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
+#define  SPDIFRX_IMR_PERRIE                   0x00000004U        /*!<Parity error interrupt enable                      */
+#define  SPDIFRX_IMR_OVRIE                    0x00000008U        /*!<Overrun error Interrupt Enable                     */
+#define  SPDIFRX_IMR_SBLKIE                   0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
+#define  SPDIFRX_IMR_SYNCDIE                  0x00000020U        /*!<Synchronization Done                               */
+#define  SPDIFRX_IMR_IFEIE                    0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
 
 /*******************  Bit definition for SPDIFRX_SR register  *******************/
-#define  SPDIFRX_SR_RXNE                   ((uint32_t)0x00000001U)       /*!<Read data register not empty                          */
-#define  SPDIFRX_SR_CSRNE                  ((uint32_t)0x00000002U)       /*!<The Control Buffer register is not empty              */
-#define  SPDIFRX_SR_PERR                   ((uint32_t)0x00000004U)       /*!<Parity error                                          */
-#define  SPDIFRX_SR_OVR                    ((uint32_t)0x00000008U)       /*!<Overrun error                                         */
-#define  SPDIFRX_SR_SBD                    ((uint32_t)0x00000010U)       /*!<Synchronization Block Detected                        */
-#define  SPDIFRX_SR_SYNCD                  ((uint32_t)0x00000020U)       /*!<Synchronization Done                                  */
-#define  SPDIFRX_SR_FERR                   ((uint32_t)0x00000040U)       /*!<Framing error                                         */
-#define  SPDIFRX_SR_SERR                   ((uint32_t)0x00000080U)       /*!<Synchronization error                                 */
-#define  SPDIFRX_SR_TERR                   ((uint32_t)0x00000100U)       /*!<Time-out error                                        */
-#define  SPDIFRX_SR_WIDTH5                 ((uint32_t)0x7FFF0000U)       /*!<Duration of 5 symbols counted with SPDIFRX_clk          */
+#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
+#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
+#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
+#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
+#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
+#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
+#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
+#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
+#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
+#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with SPDIFRX_clk          */
 
 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
-#define  SPDIFRX_IFCR_PERRCF               ((uint32_t)0x00000004U)       /*!<Clears the Parity error flag                         */
-#define  SPDIFRX_IFCR_OVRCF                ((uint32_t)0x00000008U)       /*!<Clears the Overrun error flag                        */
-#define  SPDIFRX_IFCR_SBDCF                ((uint32_t)0x00000010U)       /*!<Clears the Synchronization Block Detected flag       */
-#define  SPDIFRX_IFCR_SYNCDCF              ((uint32_t)0x00000020U)       /*!<Clears the Synchronization Done flag                 */
+#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
+#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
+#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
+#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
-#define  SPDIFRX_DR0_DR                    ((uint32_t)0x00FFFFFFU)        /*!<Data value            */
-#define  SPDIFRX_DR0_PE                    ((uint32_t)0x01000000U)        /*!<Parity Error bit      */
-#define  SPDIFRX_DR0_V                     ((uint32_t)0x02000000U)        /*!<Validity bit          */
-#define  SPDIFRX_DR0_U                     ((uint32_t)0x04000000U)        /*!<User bit              */
-#define  SPDIFRX_DR0_C                     ((uint32_t)0x08000000U)        /*!<Channel Status bit    */
-#define  SPDIFRX_DR0_PT                    ((uint32_t)0x30000000U)        /*!<Preamble Type         */
+#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
+#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
+#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
+#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
+#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
-#define  SPDIFRX_DR1_DR                    ((uint32_t)0xFFFFFF00U)        /*!<Data value            */
-#define  SPDIFRX_DR1_PT                    ((uint32_t)0x00000030U)        /*!<Preamble Type         */
-#define  SPDIFRX_DR1_C                     ((uint32_t)0x00000008U)        /*!<Channel Status bit    */
-#define  SPDIFRX_DR1_U                     ((uint32_t)0x00000004U)        /*!<User bit              */
-#define  SPDIFRX_DR1_V                     ((uint32_t)0x00000002U)        /*!<Validity bit          */
-#define  SPDIFRX_DR1_PE                    ((uint32_t)0x00000001U)        /*!<Parity Error bit      */
+#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
+#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
+#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
+#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
+#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
 
 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
-#define  SPDIFRX_DR1_DRNL1                 ((uint32_t)0xFFFF0000U)        /*!<Data value Channel B      */
-#define  SPDIFRX_DR1_DRNL2                 ((uint32_t)0x0000FFFFU)        /*!<Data value Channel A      */
+#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
+#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
 
 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
-#define  SPDIFRX_CSR_USR                     ((uint32_t)0x0000FFFFU)        /*!<User data information           */
-#define  SPDIFRX_CSR_CS                      ((uint32_t)0x00FF0000U)        /*!<Channel A status information    */
-#define  SPDIFRX_CSR_SOB                     ((uint32_t)0x01000000U)        /*!<Start Of Block                  */
+#define  SPDIFRX_CSR_USR                     0x0000FFFFU        /*!<User data information           */
+#define  SPDIFRX_CSR_CS                      0x00FF0000U        /*!<Channel A status information    */
+#define  SPDIFRX_CSR_SOB                     0x01000000U        /*!<Start Of Block                  */
 
 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
-#define  SPDIFRX_DIR_THI                 ((uint32_t)0x000013FFU)        /*!<Threshold LOW      */
-#define  SPDIFRX_DIR_TLO                 ((uint32_t)0x1FFF0000U)        /*!<Threshold HIGH     */
+#define  SPDIFRX_DIR_THI                 0x000013FFU        /*!<Threshold LOW      */
+#define  SPDIFRX_DIR_TLO                 0x1FFF0000U        /*!<Threshold HIGH     */
 
 
 /******************************************************************************/
@@ -6203,148 +6212,148 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6352,85 +6361,85 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
-#define  SPI_I2SCFGR_ASTRTEN                 ((uint32_t)0x00001000U)            /*!<Asynchronous start enable */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U            /*!<Asynchronous start enable */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6438,290 +6447,290 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
-#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100U) /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  ((uint32_t)0x00000C00U) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008U) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009U) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000AU) /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080U) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090U) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0U) /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
 
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600U) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800U) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900U) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00U) /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
 
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000U) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000U) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000U) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000U) /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006U) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008U) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009U) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000AU) /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060U) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080U) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090U) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0U) /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600U) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800U) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900U) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00U) /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
 
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000U) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000U) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000U) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000U) /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006U) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008U) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009U) /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060U) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080U) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090U) /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
 
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600U) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800U) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900U) /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
 
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000U) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000U) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000U) /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006U) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008U) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009U) /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
 
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060U) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008U) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009U) /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
 
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600U) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800U) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900U) /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
 
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000U) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000U) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000U) /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************  Bit definition for SYSCFG_CFGR register  ****************/  
-#define SYSCFG_CFGR_FMPI2C1_SCL         ((uint32_t)0x00000001U) /*!<FM+ drive capability for FMPI2C1_SCL pin */
-#define SYSCFG_CFGR_FMPI2C1_SDA         ((uint32_t)0x00000002U) /*!<FM+ drive capability for FMPI2C1_SDA pin */
+#define SYSCFG_CFGR_FMPI2C1_SCL         0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA         0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6729,298 +6738,298 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -7029,82 +7038,82 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7112,35 +7121,54 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -7149,46 +7177,46 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 
 /******************************************************************************/
@@ -7197,678 +7225,678 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)         /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)         /*!< Session request */
-#define USB_OTG_GOTGCTL_VBVALOEN                ((uint32_t)0x00000004U)         /*!< VBUS valid override enable */
-#define USB_OTG_GOTGCTL_VBVALOVAL               ((uint32_t)0x00000008U)         /*!< VBUS valid override value */
-#define USB_OTG_GOTGCTL_AVALOEN                 ((uint32_t)0x00000010U)         /*!< A-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_AVALOVAL                ((uint32_t)0x00000020U)         /*!< A-peripheral session valid override value */
-#define USB_OTG_GOTGCTL_BVALOEN                 ((uint32_t)0x00000040U)         /*!< B-peripheral session valid override enable */
-#define USB_OTG_GOTGCTL_BVALOVAL                ((uint32_t)0x00000080U)         /*!< B-peripheral session valid override value  */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)         /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)         /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)         /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_EHEN                    ((uint32_t)0x00001000U)         /*!< Embedded host enable */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)         /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)         /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)         /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSESVLD                 ((uint32_t)0x00080000U)         /*!< B-session valid */
-#define USB_OTG_GOTGCTL_OTGVER                  ((uint32_t)0x00100000U)         /*!< OTG version  */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
 
 /********************  Bit definition for USB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition for USB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done                          */
-#define USB_OTG_GOTGINT_IDCHNG                  ((uint32_t)0x00100000U)            /*!< Change in ID pin input value           */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
 
 /********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status   */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status   */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
 
 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
 
 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM                ((uint32_t)0x00000020U)            /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
 
 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_RSTDET                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt                       */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_LPMINT                  ((uint32_t)0x08000000U)            /*!< LPM interrupt                                  */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt        */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_RSTDEM                  ((uint32_t)0x00800000U)            /*!< Reset detected interrupt mask                      */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_LPMINTM                 ((uint32_t)0x08000000U)            /*!< LPM interrupt Mask                                  */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask        */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth                */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)         /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)           /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)           /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U           /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                 ((uint32_t)0x00010000U)              /*!< Power down */
-#define USB_OTG_GCCFG_VBDEN                  ((uint32_t)0x00200000U)              /*!< USB VBUS Detection Enable */
+#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
 
 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM          ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM          ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
  
 /********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID               ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
-#define  USB_OTG_GLPMCFG_LPMEN               ((uint32_t)0x00000001U)            /*!< LPM support enable                                     */
-#define  USB_OTG_GLPMCFG_LPMACK              ((uint32_t)0x00000002U)            /*!< LPM Token acknowledge enable                           */
-#define  USB_OTG_GLPMCFG_BESL                ((uint32_t)0x0000003CU)            /*!< BESL value received with last ACKed LPM Token          */
-#define  USB_OTG_GLPMCFG_REMWAKE             ((uint32_t)0x00000040U)            /*!< bRemoteWake value received with last ACKed LPM Token   */
-#define  USB_OTG_GLPMCFG_L1SSEN              ((uint32_t)0x00000080U)            /*!< L1 shallow sleep enable                                */
-#define  USB_OTG_GLPMCFG_BESLTHRS            ((uint32_t)0x00000F00U)            /*!< BESL threshold                                         */
-#define  USB_OTG_GLPMCFG_L1DSEN              ((uint32_t)0x00001000U)            /*!< L1 deep sleep enable                                   */
-#define  USB_OTG_GLPMCFG_LPMRSP              ((uint32_t)0x00006000U)            /*!< LPM response                                           */
-#define  USB_OTG_GLPMCFG_SLPSTS              ((uint32_t)0x00008000U)            /*!< Port sleep status                                      */
-#define  USB_OTG_GLPMCFG_L1RSMOK             ((uint32_t)0x00010000U)            /*!< Sleep State Resume OK                                  */
-#define  USB_OTG_GLPMCFG_LPMCHIDX            ((uint32_t)0x001E0000U)            /*!< LPM Channel Index                                      */
-#define  USB_OTG_GLPMCFG_LPMRCNT             ((uint32_t)0x00E00000U)            /*!< LPM retry count                                        */
-#define  USB_OTG_GLPMCFG_SNDLPM              ((uint32_t)0x01000000U)            /*!< Send LPM transaction                                   */
-#define  USB_OTG_GLPMCFG_LPMRCNTSTS          ((uint32_t)0x0E000000U)            /*!< LPM retry count status                                 */
-#define  USB_OTG_GLPMCFG_ENBESL              ((uint32_t)0x10000000U)            /*!< Enable best effort service latency                     */
+#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
 
 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM           ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM            ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM             ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM         ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM         ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM          ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM             ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM            ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
 
 /********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset                 */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power                 */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask                       */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask                       */
 
 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth                    */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
 
 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status                       */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake                  */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable                  */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
 
 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space available */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR                 ((uint32_t)0x00000020U)            /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 
 /**
@@ -7943,10 +7971,12 @@ typedef struct
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
 
 /******************************* SAI Instances ********************************/
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
                                      ((PERIPH) == SAI1_Block_B) || \
                                      ((PERIPH) == SAI2_Block_A) || \
                                      ((PERIPH) == SAI2_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
 
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h
index deb16c377b..bb77f28a8a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c
index f77e8118a6..51ea3a8f13 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -111,9 +111,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -341,7 +342,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -506,7 +507,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -695,7 +696,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -772,18 +773,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h
index 36df869771..bb88f0d38f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h
index 0fd6592699..84a69380f5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h
@@ -2,19 +2,19 @@
   ******************************************************************************
   * @file    stm32f407xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F407xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
   *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
   *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -64,10 +64,10 @@
 /**
   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
   */
-#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
 #ifndef __FPU_PRESENT
 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
 #endif /* __FPU_PRESENT */
@@ -935,19 +935,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x080FFFFF) /*!< FLASH end address */
-#define CCMDATARAM_END        ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -956,122 +956,122 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
 #define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
 
 /*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
 
 /*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1187,360 +1187,365 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1549,1319 +1554,1319 @@ USB_OTG_HostChannelTypeDef;
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFF)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFF)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2869,15 +2874,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 
 /******************************************************************************/
@@ -2886,90 +2891,92 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFF)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2983,213 +2990,260 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
-#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 
-/********************  Bits definition for DCMI_MISR register  ****************/
-#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
-#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
-#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
-#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
-#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
-#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
 /*                             DMA Controller                                 */
 /*                                                                            */
 /******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 
 /******************************************************************************/
@@ -3198,154 +3252,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3353,97 +3407,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3451,828 +3505,828 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FSMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */
+#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FSMC_BCR2_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BCR2_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BCR2_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FSMC_BCR3_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BCR3_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BCR3_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CPSIZE                    ((uint32_t)0x00070000)        /*!<CRAM page size */
-#define  FSMC_BCR4_CPSIZE_0                  ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BCR4_CPSIZE_1                  ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BCR4_CPSIZE_2                  ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */
+#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */
+#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */
+#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */
+#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */
+#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */
+#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */
+#define  FSMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FSMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FSMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FSMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */
 
 /******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [7:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FSMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */
 
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */
 
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty */
+#define  FSMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FSMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      0x40U               /*!<FIFO empty */
 
 /*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty */
+#define  FSMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FSMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      0x40U               /*!<FIFO empty */
 
 /*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint32_t)0x01)               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        ((uint32_t)0x02)               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        ((uint32_t)0x04)               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       ((uint32_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       ((uint32_t)0x10)               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       ((uint32_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      ((uint32_t)0x40)               /*!<FIFO empty */
+#define  FSMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                 */
+#define  FSMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                       */
+#define  FSMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status                */
+#define  FSMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit   */
+#define  FSMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit         */
+#define  FSMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit  */
+#define  FSMC_SR4_FEMPT                      0x40U               /*!<FIFO empty */
 
 /******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
 
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
+#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4280,235 +4334,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -4528,22 +4582,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -4563,57 +4617,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -4621,97 +4675,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000F)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -4719,20 +4773,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -4741,42 +4795,42 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection               */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                        */
-#define  PWR_CR_VOS                          ((uint32_t)0x00004000)     /*!< VOS bit (Regulator voltage scaling output selection) */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection               */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                        */
+#define  PWR_CR_VOS                          0x00004000U     /*!< VOS bit (Regulator voltage scaling output selection) */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -4787,442 +4841,442 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
-#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
+#define  RCC_AHB3RSTR_FSMCRST                0x00000001U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
 
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
-#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB3ENR_FSMCEN                  0x00000001U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
-#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5230,15 +5284,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5246,379 +5300,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 
 
@@ -5628,157 +5682,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5786,84 +5840,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5871,245 +5925,245 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6117,298 +6171,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFF)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -6417,82 +6471,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FF)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000F)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6500,35 +6554,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -6537,46 +6610,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -6584,91 +6657,91 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
 
 /* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
   
 /* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
 
 /* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
 
 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
@@ -6682,334 +6755,334 @@ USB_OTG_HostChannelTypeDef;
    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
 
 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
 
 /* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
 
 /* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
 
 /* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
 
 /* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
 
 /* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
 
 /* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
 
 /* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
 
 /* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
 
 /******************************************************************************/
 /*                Ethernet MMC Registers bits definition                      */
 /******************************************************************************/
 
 /* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
 
 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
 
 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
 
 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
 
 /******************************************************************************/
 /*               Ethernet PTP Registers bits definition                       */
 /******************************************************************************/
 
 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
 
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
 
 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
 
 /* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
 
 /* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
 
 /* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
 
 /* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
+#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
 
 /******************************************************************************/
 /*                 Ethernet DMA Registers bits definition                     */
 /******************************************************************************/
 
 /* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
 
 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
 
 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
 
 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
 
 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
 
 /* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
   /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
 
 /* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
 
 /* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
 
 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7017,654 +7090,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFF)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFF)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001E)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFF)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFF)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFF)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFF)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000F)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFF)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFF)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFF)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFF)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFF)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFF)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFF)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FC)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFF)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFF)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFF)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007F)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFF)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFF)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FF)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 /**
   * @}
@@ -8022,15 +8095,15 @@ USB_OTG_HostChannelTypeDef;
 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
 
 /****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280 /* in Bytes */
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
 
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6    /* Including EP0 */
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096 /* in Bytes */
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
 
 /******************************************************************************/
 /*  For a painless codes migration between the STM32F4xx device product       */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h
index f2538e5c25..8306e2f669 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -76,7 +76,10 @@
   */
 #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
-    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   #define STM32F407xx         /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -91,7 +94,15 @@
   /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
   /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
   /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
-                                   and STM32F446ZE Devices */ 
+                                   and STM32F446ZE Devices */
+  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
+                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
+                                   and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -107,17 +118,17 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.4.1
+  * @brief CMSIS version number V2.5.0
   */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F4xx_CMSIS_DEVICE_VERSION        ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
-                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION))
-                                             
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION))
+
 /**
   * @}
   */
@@ -146,10 +157,28 @@
   #include "stm32f401xc.h"
 #elif defined(STM32F401xE)
   #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+  #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+  #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
   #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+  #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+  #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.c
index d518517633..448af3ffab 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -341,7 +341,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h
index 3fb34198c2..0b8a72d9ef 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h
index 00935791fc..57d11dad78 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f439xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F439xx Device Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -1123,21 +1123,21 @@ USB_OTG_HostChannelTypeDef;
 /** @addtogroup Peripheral_memory_map
   * @{
   */
-#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000U) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            ((uint32_t)0x20020000U) /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000U) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC registers base address                                                 */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000U) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         ((uint32_t)0x22400000U) /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000U) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x081FFFFFU) /*!< FLASH end address */
-#define CCMDATARAM_END        ((uint32_t)0x1000FFFFU) /*!< CCM data RAM end address */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -1262,24 +1262,24 @@ USB_OTG_HostChannelTypeDef;
 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000U)
+#define DBGMCU_BASE           0xE0042000U
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000U)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000U)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000U)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800U)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900U)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00U)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20U)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400U)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440U)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500U)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20U)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00U)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000U)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000U)
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
 
 /**
   * @}
@@ -1414,334 +1414,334 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001U)        /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002U)        /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004U)        /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008U)        /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010U)        /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020U)        /*!<Overrun flag */
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001FU)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020U)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040U)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080U)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100U)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200U)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400U)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800U)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000U)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000U)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000U)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000U)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000U)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000U)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
   
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001U)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002U)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100U)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200U)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400U)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800U)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000U)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000U)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000U)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000U)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000U)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000U)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000U)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007U)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038U)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0U)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00U)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000U)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000U)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000U)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000U)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000U)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007U)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038U)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0U)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00U)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000U)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000U)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000U)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000U)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000U)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000U)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000U)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000U)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000U)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFFU)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFFU)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001FU)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0U)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00U)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000U)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000U)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001FU)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0U)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00U)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000U)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000U)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000U)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001FU)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0U)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00U)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000U)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000U)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000U)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000U)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000U)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000U)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000U)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000U)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000U)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001FU)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0U)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00U)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000U)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000U)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000U)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000U)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000U)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000U)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFFU)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFFU)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000U)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001U)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002U)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004U)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008U)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010U)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020U)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100U)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200U)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400U)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800U)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000U)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_OVR2                        ((uint32_t)0x00002000U)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000U)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000U)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000U)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000U)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000U)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_OVR3                        ((uint32_t)0x00200000U)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
 
 /* Legacy defines */
 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
@@ -1749,30 +1749,30 @@ USB_OTG_HostChannelTypeDef;
 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001FU)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00U)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000U)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000U)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000U)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000U)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000U)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000U)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFFU)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000U)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1781,1319 +1781,1319 @@ USB_OTG_HostChannelTypeDef;
 /******************************************************************************/
 /*!<CAN control and status registers */
 /*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint32_t)0x00000001U)        /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint32_t)0x00000002U)        /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint32_t)0x00000004U)        /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint32_t)0x00000008U)        /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint32_t)0x00000010U)        /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint32_t)0x00000020U)        /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint32_t)0x00000040U)        /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint32_t)0x00000080U)        /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint32_t)0x00008000U)        /*!<bxCAN software master reset */
-#define  CAN_MCR_DBF                         ((uint32_t)0x00010000U)        /*!<bxCAN Debug freeze */
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
 /*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint32_t)0x0001U)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint32_t)0x0002U)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint32_t)0x0004U)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint32_t)0x0008U)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint32_t)0x0010U)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint32_t)0x0100U)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint32_t)0x0200U)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint32_t)0x0400U)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint32_t)0x0800U)            /*!<CAN Rx Signal */
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
 
 /*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001U)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002U)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004U)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008U)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080U)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100U)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200U)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400U)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800U)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000U)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000U)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000U)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000U)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000U)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000U)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000U)        /*!<Mailbox Code */
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
 
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000U)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000U)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000U)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000U)        /*!<Transmit Mailbox 2 Empty */
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
 
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000U)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000U)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000U)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000U)        /*!<Lowest Priority Flag for Mailbox 2 */
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
 
 /*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint32_t)0x03U)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint32_t)0x08U)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint32_t)0x10U)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint32_t)0x20U)               /*!<Release FIFO 0 Output Mailbox */
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
 
 /*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint32_t)0x03U)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint32_t)0x08U)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint32_t)0x10U)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint32_t)0x20U)               /*!<Release FIFO 1 Output Mailbox */
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
 
 /********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010U)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020U)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040U)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000U)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000U)        /*!<Sleep Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100U)        /*!<Error warning interrupt enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200U)        /*!<Error passive interrupt enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400U)        /*!<Bus-off interrupt enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800U)        /*!<Last error code interrupt enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000U)        /*!<Error interrupt enable */
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
 
 
 /********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001U)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002U)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004U)        /*!<Bus-Off Flag */
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
 
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070U)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040U)        /*!<Bit 2 */
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
 
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000U)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000U)        /*!<Receive Error Counter */
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
 
 /*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FFU)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000U)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS1_0                       ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS1_1                       ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS1_2                       ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  CAN_BTR_TS1_3                       ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000U)        /*!<Time Segment 2 */
-#define  CAN_BTR_TS2_0                       ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  CAN_BTR_TS2_1                       ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  CAN_BTR_TS2_2                       ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000U)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_SJW_0                       ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  CAN_BTR_SJW_1                       ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000U)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000U)        /*!<Silent Mode */
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
 
 
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001U)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100U)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002U)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004U)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8U)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000U)        /*!<Standard Identifier or Extended Identifier */
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
 
 /*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000FU)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00U)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000U)        /*!<Message Time Stamp */
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
 
 /*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FFU)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00U)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000U)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000U)        /*!<Data byte 3 */
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
 
 /*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FFU)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00U)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000U)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000U)        /*!<Data byte 7 */
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
 
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint32_t)0x01U)               /*!<Filter Init Mode */
-#define  CAN_FMR_CAN2SB                      ((uint32_t)0x00003F00U)        /*!<CAN2 start bank */
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
 
 /*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint32_t)0x00000001U)        /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint32_t)0x00000002U)        /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint32_t)0x00000004U)        /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint32_t)0x00000008U)        /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint32_t)0x00000010U)        /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint32_t)0x00000020U)        /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint32_t)0x00000040U)        /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint32_t)0x00000080U)        /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint32_t)0x00000100U)        /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint32_t)0x00000200U)        /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint32_t)0x00000400U)        /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint32_t)0x00000800U)        /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint32_t)0x00001000U)        /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint32_t)0x00002000U)        /*!<Filter Init Mode bit 13 */
-#define  CAN_FM1R_FBM14                      ((uint32_t)0x00004000U)        /*!<Filter Init Mode bit 14 */
-#define  CAN_FM1R_FBM15                      ((uint32_t)0x00008000U)        /*!<Filter Init Mode bit 15 */
-#define  CAN_FM1R_FBM16                      ((uint32_t)0x00010000U)        /*!<Filter Init Mode bit 16 */
-#define  CAN_FM1R_FBM17                      ((uint32_t)0x00020000U)        /*!<Filter Init Mode bit 17 */
-#define  CAN_FM1R_FBM18                      ((uint32_t)0x00040000U)        /*!<Filter Init Mode bit 18 */
-#define  CAN_FM1R_FBM19                      ((uint32_t)0x00080000U)        /*!<Filter Init Mode bit 19 */
-#define  CAN_FM1R_FBM20                      ((uint32_t)0x00100000U)        /*!<Filter Init Mode bit 20 */
-#define  CAN_FM1R_FBM21                      ((uint32_t)0x00200000U)        /*!<Filter Init Mode bit 21 */
-#define  CAN_FM1R_FBM22                      ((uint32_t)0x00400000U)        /*!<Filter Init Mode bit 22 */
-#define  CAN_FM1R_FBM23                      ((uint32_t)0x00800000U)        /*!<Filter Init Mode bit 23 */
-#define  CAN_FM1R_FBM24                      ((uint32_t)0x01000000U)        /*!<Filter Init Mode bit 24 */
-#define  CAN_FM1R_FBM25                      ((uint32_t)0x02000000U)        /*!<Filter Init Mode bit 25 */
-#define  CAN_FM1R_FBM26                      ((uint32_t)0x04000000U)        /*!<Filter Init Mode bit 26 */
-#define  CAN_FM1R_FBM27                      ((uint32_t)0x08000000U)        /*!<Filter Init Mode bit 27 */
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
 
 /*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint32_t)0x00000001U)        /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint32_t)0x00000002U)        /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint32_t)0x00000004U)        /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint32_t)0x00000008U)        /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint32_t)0x00000010U)        /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint32_t)0x00000020U)        /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint32_t)0x00000040U)        /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint32_t)0x00000080U)        /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint32_t)0x00000100U)        /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint32_t)0x00000200U)        /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint32_t)0x00000400U)        /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint32_t)0x00000800U)        /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint32_t)0x00001000U)        /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint32_t)0x00002000U)        /*!<Filter Scale Configuration bit 13 */
-#define  CAN_FS1R_FSC14                      ((uint32_t)0x00004000U)        /*!<Filter Scale Configuration bit 14 */
-#define  CAN_FS1R_FSC15                      ((uint32_t)0x00008000U)        /*!<Filter Scale Configuration bit 15 */
-#define  CAN_FS1R_FSC16                      ((uint32_t)0x00010000U)        /*!<Filter Scale Configuration bit 16 */
-#define  CAN_FS1R_FSC17                      ((uint32_t)0x00020000U)        /*!<Filter Scale Configuration bit 17 */
-#define  CAN_FS1R_FSC18                      ((uint32_t)0x00040000U)        /*!<Filter Scale Configuration bit 18 */
-#define  CAN_FS1R_FSC19                      ((uint32_t)0x00080000U)        /*!<Filter Scale Configuration bit 19 */
-#define  CAN_FS1R_FSC20                      ((uint32_t)0x00100000U)        /*!<Filter Scale Configuration bit 20 */
-#define  CAN_FS1R_FSC21                      ((uint32_t)0x00200000U)        /*!<Filter Scale Configuration bit 21 */
-#define  CAN_FS1R_FSC22                      ((uint32_t)0x00400000U)        /*!<Filter Scale Configuration bit 22 */
-#define  CAN_FS1R_FSC23                      ((uint32_t)0x00800000U)        /*!<Filter Scale Configuration bit 23 */
-#define  CAN_FS1R_FSC24                      ((uint32_t)0x01000000U)        /*!<Filter Scale Configuration bit 24 */
-#define  CAN_FS1R_FSC25                      ((uint32_t)0x02000000U)        /*!<Filter Scale Configuration bit 25 */
-#define  CAN_FS1R_FSC26                      ((uint32_t)0x04000000U)        /*!<Filter Scale Configuration bit 26 */
-#define  CAN_FS1R_FSC27                      ((uint32_t)0x08000000U)        /*!<Filter Scale Configuration bit 27 */
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
 
 /******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                       ((uint32_t)0x00000001U)        /*!<Filter FIFO Assignment bit 0 */
-#define  CAN_FFA1R_FFA1                       ((uint32_t)0x00000002U)        /*!<Filter FIFO Assignment bit 1 */
-#define  CAN_FFA1R_FFA2                       ((uint32_t)0x00000004U)        /*!<Filter FIFO Assignment bit 2 */
-#define  CAN_FFA1R_FFA3                       ((uint32_t)0x00000008U)        /*!<Filter FIFO Assignment bit 3 */
-#define  CAN_FFA1R_FFA4                       ((uint32_t)0x00000010U)        /*!<Filter FIFO Assignment bit 4 */
-#define  CAN_FFA1R_FFA5                       ((uint32_t)0x00000020U)        /*!<Filter FIFO Assignment bit 5 */
-#define  CAN_FFA1R_FFA6                       ((uint32_t)0x00000040U)        /*!<Filter FIFO Assignment bit 6 */
-#define  CAN_FFA1R_FFA7                       ((uint32_t)0x00000080U)        /*!<Filter FIFO Assignment bit 7 */
-#define  CAN_FFA1R_FFA8                       ((uint32_t)0x00000100U)        /*!<Filter FIFO Assignment bit 8 */
-#define  CAN_FFA1R_FFA9                       ((uint32_t)0x00000200U)        /*!<Filter FIFO Assignment bit 9 */
-#define  CAN_FFA1R_FFA10                      ((uint32_t)0x00000400U)        /*!<Filter FIFO Assignment bit 10 */
-#define  CAN_FFA1R_FFA11                      ((uint32_t)0x00000800U)        /*!<Filter FIFO Assignment bit 11 */
-#define  CAN_FFA1R_FFA12                      ((uint32_t)0x00001000U)        /*!<Filter FIFO Assignment bit 12 */
-#define  CAN_FFA1R_FFA13                      ((uint32_t)0x00002000U)        /*!<Filter FIFO Assignment bit 13 */
-#define  CAN_FFA1R_FFA14                      ((uint32_t)0x00004000U)        /*!<Filter FIFO Assignment bit 14 */
-#define  CAN_FFA1R_FFA15                      ((uint32_t)0x00008000U)        /*!<Filter FIFO Assignment bit 15 */
-#define  CAN_FFA1R_FFA16                      ((uint32_t)0x00010000U)        /*!<Filter FIFO Assignment bit 16 */
-#define  CAN_FFA1R_FFA17                      ((uint32_t)0x00020000U)        /*!<Filter FIFO Assignment bit 17 */
-#define  CAN_FFA1R_FFA18                      ((uint32_t)0x00040000U)        /*!<Filter FIFO Assignment bit 18 */
-#define  CAN_FFA1R_FFA19                      ((uint32_t)0x00080000U)        /*!<Filter FIFO Assignment bit 19 */
-#define  CAN_FFA1R_FFA20                      ((uint32_t)0x00100000U)        /*!<Filter FIFO Assignment bit 20 */
-#define  CAN_FFA1R_FFA21                      ((uint32_t)0x00200000U)        /*!<Filter FIFO Assignment bit 21 */
-#define  CAN_FFA1R_FFA22                      ((uint32_t)0x00400000U)        /*!<Filter FIFO Assignment bit 22 */
-#define  CAN_FFA1R_FFA23                      ((uint32_t)0x00800000U)        /*!<Filter FIFO Assignment bit 23 */
-#define  CAN_FFA1R_FFA24                      ((uint32_t)0x01000000U)        /*!<Filter FIFO Assignment bit 24 */
-#define  CAN_FFA1R_FFA25                      ((uint32_t)0x02000000U)        /*!<Filter FIFO Assignment bit 25 */
-#define  CAN_FFA1R_FFA26                      ((uint32_t)0x04000000U)        /*!<Filter FIFO Assignment bit 26 */
-#define  CAN_FFA1R_FFA27                      ((uint32_t)0x08000000U)        /*!<Filter FIFO Assignment bit 27 */
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
 
 /*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                        ((uint32_t)0x0FFFFFFFU)        /*!<Filter Active */
-#define  CAN_FA1R_FACT0                       ((uint32_t)0x00000001U)        /*!<Filter Active bit 0 */
-#define  CAN_FA1R_FACT1                       ((uint32_t)0x00000002U)        /*!<Filter Active bit 1 */
-#define  CAN_FA1R_FACT2                       ((uint32_t)0x00000004U)        /*!<Filter Active bit 2 */
-#define  CAN_FA1R_FACT3                       ((uint32_t)0x00000008U)        /*!<Filter Active bit 3 */
-#define  CAN_FA1R_FACT4                       ((uint32_t)0x00000010U)        /*!<Filter Active bit 4 */
-#define  CAN_FA1R_FACT5                       ((uint32_t)0x00000020U)        /*!<Filter Active bit 5 */
-#define  CAN_FA1R_FACT6                       ((uint32_t)0x00000040U)        /*!<Filter Active bit 6 */
-#define  CAN_FA1R_FACT7                       ((uint32_t)0x00000080U)        /*!<Filter Active bit 7 */
-#define  CAN_FA1R_FACT8                       ((uint32_t)0x00000100U)        /*!<Filter Active bit 8 */
-#define  CAN_FA1R_FACT9                       ((uint32_t)0x00000200U)        /*!<Filter Active bit 9 */
-#define  CAN_FA1R_FACT10                      ((uint32_t)0x00000400U)        /*!<Filter Active bit 10 */
-#define  CAN_FA1R_FACT11                      ((uint32_t)0x00000800U)        /*!<Filter Active bit 11 */
-#define  CAN_FA1R_FACT12                      ((uint32_t)0x00001000U)        /*!<Filter Active bit 12 */
-#define  CAN_FA1R_FACT13                      ((uint32_t)0x00002000U)        /*!<Filter Active bit 13 */
-#define  CAN_FA1R_FACT14                      ((uint32_t)0x00004000U)        /*!<Filter Active bit 14 */
-#define  CAN_FA1R_FACT15                      ((uint32_t)0x00008000U)        /*!<Filter Active bit 15 */
-#define  CAN_FA1R_FACT16                      ((uint32_t)0x00010000U)        /*!<Filter Active bit 16 */
-#define  CAN_FA1R_FACT17                      ((uint32_t)0x00020000U)        /*!<Filter Active bit 17 */
-#define  CAN_FA1R_FACT18                      ((uint32_t)0x00040000U)        /*!<Filter Active bit 18 */
-#define  CAN_FA1R_FACT19                      ((uint32_t)0x00080000U)        /*!<Filter Active bit 19 */
-#define  CAN_FA1R_FACT20                      ((uint32_t)0x00100000U)        /*!<Filter Active bit 20 */
-#define  CAN_FA1R_FACT21                      ((uint32_t)0x00200000U)        /*!<Filter Active bit 21 */
-#define  CAN_FA1R_FACT22                      ((uint32_t)0x00400000U)        /*!<Filter Active bit 22 */
-#define  CAN_FA1R_FACT23                      ((uint32_t)0x00800000U)        /*!<Filter Active bit 23 */
-#define  CAN_FA1R_FACT24                      ((uint32_t)0x01000000U)        /*!<Filter Active bit 24 */
-#define  CAN_FA1R_FACT25                      ((uint32_t)0x02000000U)        /*!<Filter Active bit 25 */
-#define  CAN_FA1R_FACT26                      ((uint32_t)0x04000000U)        /*!<Filter Active bit 26 */
-#define  CAN_FA1R_FACT27                      ((uint32_t)0x08000000U)        /*!<Filter Active bit 27 */
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
 
 /*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001U)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002U)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004U)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008U)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010U)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020U)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040U)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080U)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100U)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200U)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400U)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800U)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000U)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000U)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000U)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000U)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000U)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000U)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000U)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000U)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000U)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000U)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000U)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000U)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000U)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000U)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000U)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000U)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000U)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000U)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000U)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000U)        /*!<Filter bit 31 */
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3101,15 +3101,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFFU)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01U)        /*!< RESET bit */
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3117,53 +3117,53 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004U)
+#define CRYP_CR_ALGODIR                      0x00000004U
 
-#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038U)
-#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008U)
-#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010U)
-#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020U)
-#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000U)
-#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008U)
-#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010U)
-#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018U)
-#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020U)
-#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028U)
-#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030U)
-#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038U)
+#define CRYP_CR_ALGOMODE                     0x00080038U
+#define CRYP_CR_ALGOMODE_0                   0x00000008U
+#define CRYP_CR_ALGOMODE_1                   0x00000010U
+#define CRYP_CR_ALGOMODE_2                   0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
 
-#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0U)
-#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040U)
-#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080U)
-#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300U)
-#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100U)
-#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200U)
-#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000U)
-#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000U)
+#define CRYP_CR_DATATYPE                     0x000000C0U
+#define CRYP_CR_DATATYPE_0                   0x00000040U
+#define CRYP_CR_DATATYPE_1                   0x00000080U
+#define CRYP_CR_KEYSIZE                      0x00000300U
+#define CRYP_CR_KEYSIZE_0                    0x00000100U
+#define CRYP_CR_KEYSIZE_1                    0x00000200U
+#define CRYP_CR_FFLUSH                       0x00004000U
+#define CRYP_CR_CRYPEN                       0x00008000U
 
-#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000U)
-#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000U)
-#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000U)
-#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000U) 
+#define CRYP_CR_GCM_CCMPH                    0x00030000U
+#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
+#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
+#define CRYP_CR_ALGOMODE_3                   0x00080000U 
 
 /****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         ((uint32_t)0x00000001U)
-#define CRYP_SR_IFNF                         ((uint32_t)0x00000002U)
-#define CRYP_SR_OFNE                         ((uint32_t)0x00000004U)
-#define CRYP_SR_OFFU                         ((uint32_t)0x00000008U)
-#define CRYP_SR_BUSY                         ((uint32_t)0x00000010U)
+#define CRYP_SR_IFEM                         0x00000001U
+#define CRYP_SR_IFNF                         0x00000002U
+#define CRYP_SR_OFNE                         0x00000004U
+#define CRYP_SR_OFFU                         0x00000008U
+#define CRYP_SR_BUSY                         0x00000010U
 /****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001U)
-#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002U)
+#define CRYP_DMACR_DIEN                      0x00000001U
+#define CRYP_DMACR_DOEN                      0x00000002U
 /*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001U)
-#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002U)
+#define CRYP_IMSCR_INIM                      0x00000001U
+#define CRYP_IMSCR_OUTIM                     0x00000002U
 /****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001U)
-#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002U)
+#define CRYP_RISR_OUTRIS                     0x00000001U
+#define CRYP_RISR_INRIS                      0x00000002U
 /****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001U)
-#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002U)
+#define CRYP_MISR_INMIS                      0x00000001U
+#define CRYP_MISR_OUTMIS                     0x00000002U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3171,92 +3171,92 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001U)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002U)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004U)        /*!<DAC channel1 Trigger enable */
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
 
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038U)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0U)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00U)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000U)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun interrupt enable*/
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000U)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000U)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000U)        /*!<DAC channel2 Trigger enable */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
 
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000U)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000U)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000U)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000U)        /*!<Bit 2 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
 
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000U)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000U)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000U)        /*!<Bit 1 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
 
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000U)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
 
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000U)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun interrupt enable*/
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
 
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x01U)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x02U)               /*!<DAC channel2 software trigger */
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
 
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0xFFU)               /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x0FFFU)            /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0xFFF0U)            /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0xFFU)               /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFFU)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000U)        /*!<DAC channel2 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
 
 /*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0U)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000U)        /*!<DAC channel2 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
 
 /******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x00FFU)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0xFF00U)            /*!<DAC channel2 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
 
 /*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel1 data output */
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
 
 /*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x0FFFU)            /*!<DAC channel2 data output */
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
 
 /********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000U)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000U)        /*!<DAC channel2 DMA underrun flag */
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3270,46 +3270,55 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001U)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002U)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004U)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008U)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010U)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020U)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040U)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080U)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800U)
-#define DCMI_CR_CRE                          ((uint32_t)0x00001000U)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000U)
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
 
 /********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001U)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002U)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004U)
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
 
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001U)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002U)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004U)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008U)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010U)
+/********************  Bits definition for DCMI_RIS register  ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
 
 /********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001U)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002U)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004U)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008U)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010U)
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
 
 /********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS                   ((uint32_t)0x00000001U)
-#define DCMI_MIS_OVR_MIS                     ((uint32_t)0x00000002U)
-#define DCMI_MIS_ERR_MIS                     ((uint32_t)0x00000004U)
-#define DCMI_MIS_VSYNC_MIS                   ((uint32_t)0x00000008U)
-#define DCMI_MIS_LINE_MIS                    ((uint32_t)0x00000010U)
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
@@ -3319,40 +3328,40 @@ USB_OTG_HostChannelTypeDef;
 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
 
 /********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001U)
-#define DCMI_ICR_OVR_ISC                     ((uint32_t)0x00000002U)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004U)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008U)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010U)
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
 
 /* Legacy defines */
 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
 
 /********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC                        ((uint32_t)0x000000FFU)
-#define DCMI_ESCR_LSC                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESCR_LEC                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESCR_FEC                        ((uint32_t)0xFF000000U)
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
 
 /********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU                        ((uint32_t)0x000000FFU)
-#define DCMI_ESUR_LSU                        ((uint32_t)0x0000FF00U)
-#define DCMI_ESUR_LEU                        ((uint32_t)0x00FF0000U)
-#define DCMI_ESUR_FEU                        ((uint32_t)0xFF000000U)
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
 
 /********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT                  ((uint32_t)0x00003FFFU)
-#define DCMI_CWSTRT_VST                      ((uint32_t)0x1FFF0000U)
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
 
 /********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT                   ((uint32_t)0x00003FFFU)
-#define DCMI_CWSIZE_VLINE                    ((uint32_t)0x3FFF0000U)
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
 
 /********************  Bits definition for DCMI_DR register  ******************/
-#define DCMI_DR_BYTE0                        ((uint32_t)0x000000FFU)
-#define DCMI_DR_BYTE1                        ((uint32_t)0x0000FF00U)
-#define DCMI_DR_BYTE2                        ((uint32_t)0x00FF0000U)
-#define DCMI_DR_BYTE3                        ((uint32_t)0xFF000000U)
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3360,162 +3369,161 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000U)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000U)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000U)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000U)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000U)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000U)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000U)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000U)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000U)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000U)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000U)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000U)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000U)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000U)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000U)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000U)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000U)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000U)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000U)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800U)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800U)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000U)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400U)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200U)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100U)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0U)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040U)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080U)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020U)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010U)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008U)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004U)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002U)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001U)
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
 
 /* Legacy defines */
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000U)
+#define DMA_SxCR_ACK                         0x00100000U
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFFU)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001U)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002U)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004U)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008U)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010U)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020U)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040U)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080U)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100U)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200U)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400U)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800U)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000U)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000U)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000U)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000U)
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
 
 /********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080U)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038U)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008U)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010U)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020U)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004U)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003U)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001U)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002U)
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
 
 /********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000U)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000U)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000U)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000U)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000U)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000U)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000U)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000U)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000U)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000U)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800U)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400U)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200U)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100U)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040U)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020U)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010U)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008U)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004U)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001U)
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
 
 /********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000U)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000U)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000U)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000U)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000U)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000U)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000U)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000U)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000U)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000U)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800U)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400U)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200U)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100U)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040U)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020U)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010U)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008U)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004U)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001U)
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
 
 /********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000U)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000U)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000U)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000U)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000U)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000U)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000U)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000U)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000U)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000U)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800U)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400U)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200U)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100U)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040U)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020U)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010U)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008U)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004U)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001U)
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000U)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000U)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000U)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000U)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000U)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000U)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000U)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000U)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000U)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000U)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800U)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400U)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200U)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100U)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040U)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020U)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010U)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008U)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004U)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001U)
-
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3525,34 +3533,36 @@ USB_OTG_HostChannelTypeDef;
 
 /********************  Bit definition for DMA2D_CR register  ******************/
 
-#define DMA2D_CR_START                     ((uint32_t)0x00000001U)               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002U)               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004U)               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100U)               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200U)               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400U)               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800U)               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000U)               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000U)               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      ((uint32_t)0x00030000U)               /*!< DMA2D Mode */
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
 
 /********************  Bit definition for DMA2D_ISR register  *****************/
 
-#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001U)               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002U)               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004U)               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008U)               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010U)               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020U)               /*!< Configuration Error Interrupt Flag */
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
 
 /********************  Bit definition for DMA2D_IFCR register  ****************/
 
-#define DMA2D_IFCR_CTEIF                   ((uint32_t)0x00000001U)               /*!< Clears Transfer Error Interrupt Flag         */
-#define DMA2D_IFCR_CTCIF                   ((uint32_t)0x00000002U)               /*!< Clears Transfer Complete Interrupt Flag      */
-#define DMA2D_IFCR_CTWIF                   ((uint32_t)0x00000004U)               /*!< Clears Transfer Watermark Interrupt Flag     */
-#define DMA2D_IFCR_CAECIF                  ((uint32_t)0x00000008U)               /*!< Clears CLUT Access Error Interrupt Flag      */
-#define DMA2D_IFCR_CCTCIF                  ((uint32_t)0x00000010U)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFCR_CCEIF                   ((uint32_t)0x00000020U)               /*!< Clears Configuration Error Interrupt Flag    */
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
 
 /* Legacy defines */
 #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
@@ -3564,109 +3574,124 @@ USB_OTG_HostChannelTypeDef;
 
 /********************  Bit definition for DMA2D_FGMAR register  ***************/
 
-#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_FGOR register  ****************/
 
-#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_BGMAR register  ***************/
 
-#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGOR register  ****************/
 
-#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
 
-#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000FU)               /*!< Color mode */
-#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010U)               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020U)               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00U)               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000U)               /*!< Alpha mode */
-#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000U)               /*!< Alpha value */
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
 
 /********************  Bit definition for DMA2D_FGCOLR register  **************/
 
-#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FFU)               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00U)               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000U)               /*!< Red Value */   
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
 
 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
 
-#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000FU)               /*!< Color mode */
-#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010U)               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020U)               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00U)               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000U)               /*!< Alpha Mode */
-#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000U)               /*!< Alpha value */
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
 
 /********************  Bit definition for DMA2D_BGCOLR register  **************/
 
-#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FFU)               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00U)               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000U)               /*!< Red Value */
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
 
 /********************  Bit definition for DMA2D_FGCMAR register  **************/
 
-#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_BGCMAR register  **************/
 
-#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OPFCCR register  **************/
 
-#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007U)               /*!< Color mode */
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
 
 /********************  Bit definition for DMA2D_OCOLR register  ***************/
 
 /*!<Mode_ARGB8888/RGB888 */
 
-#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FFU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
 
 /*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800U)               /*!< Red Value */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
 
 /*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
 
 /*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000FU)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0U)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00U)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000U)               /*!< Alpha Channel Value */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
 
 /********************  Bit definition for DMA2D_OMAR register  ****************/
 
-#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFFU)               /*!< Memory Address */
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
 
 /********************  Bit definition for DMA2D_OOR register  *****************/
 
-#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFFU)               /*!< Line Offset */
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
 
 /********************  Bit definition for DMA2D_NLR register  *****************/
 
-#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFFU)               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000U)               /*!< Pixel per Lines */
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
 
 /********************  Bit definition for DMA2D_LWR register  *****************/
 
-#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFFU)               /*!< Line Watermark */
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
 
 /********************  Bit definition for DMA2D_AMTCR register  ***************/
 
-#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001U)               /*!< Enable */
-#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00U)               /*!< Dead Time */
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
 
 
 /********************  Bit definition for DMA2D_FGCLUT register  **************/
@@ -3674,161 +3699,160 @@ USB_OTG_HostChannelTypeDef;
 /********************  Bit definition for DMA2D_BGCLUT register  **************/
 
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                    External Interrupt/Event Controller                     */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001U)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002U)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004U)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008U)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010U)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020U)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040U)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080U)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100U)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200U)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400U)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800U)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000U)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000U)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000U)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000U)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000U)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000U)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000U)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000U)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000U)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000U)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000U)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001U)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002U)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004U)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008U)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010U)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020U)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040U)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080U)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100U)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200U)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400U)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800U)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000U)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000U)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000U)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000U)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000U)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000U)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000U)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000U)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000U)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000U)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000U)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001U)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002U)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004U)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008U)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010U)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020U)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040U)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080U)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100U)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200U)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400U)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800U)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000U)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000U)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000U)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000U)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000U)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000U)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000U)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000U)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000U)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000U)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000U)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001U)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002U)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004U)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008U)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010U)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020U)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040U)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080U)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100U)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200U)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400U)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800U)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000U)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000U)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000U)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000U)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000U)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000U)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000U)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000U)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000U)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000U)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000U)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001U)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002U)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004U)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008U)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010U)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020U)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040U)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080U)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100U)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200U)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400U)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800U)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000U)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000U)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000U)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000U)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000U)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000U)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000U)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000U)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000U)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000U)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000U)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3836,108 +3860,108 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000FU)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000U)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001U)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002U)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003U)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004U)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005U)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006U)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007U)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008U)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009U)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000AU)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000BU)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000CU)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000DU)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000EU)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000FU)
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100U)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200U)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400U)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800U)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000U)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00U)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03U)
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001U)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002U)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010U)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020U)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040U)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080U)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000U)
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001U)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002U)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004U)
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
 #define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8U)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008U)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010U)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020U)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040U)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080U)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300U)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100U)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200U)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000U)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000U)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000U)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000U)
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001U)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002U)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004U)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008U)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000CU)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010U)
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020U)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040U)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080U)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00U)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100U)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200U)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400U)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800U)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000U)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000U)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000U)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000U)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000U)
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000U) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000U) 
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
                                              
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000U)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000U)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000U)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000U)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000U)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000U)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000U)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000U)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000U)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000U)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000U)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000U)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000U)
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -3945,1006 +3969,1006 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FMC_BCR1_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR1_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR1_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000U)        /*!<Continous clock enable     */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
 
 /******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FMC_BCR2_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR2_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR2_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FMC_BCR3_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR3_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR3_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001U)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002U)        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
 
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000CU)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
 
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030U)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040U)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100U)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200U)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400U)        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800U)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000U)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000U)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000U)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000U)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CPSIZE                    ((uint32_t)0x00070000U)        /*!<CRAM page size */
-#define  FMC_BCR4_CPSIZE_0                  ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BCR4_CPSIZE_1                  ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BCR4_CPSIZE_2                  ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000U)        /*!<Write burst enable         */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
 
 /******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000U)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000U)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000U)        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000U)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
 
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000FU)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0U)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00U)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000U)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define  FMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000U)        /*!<Bit 3 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
 
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000U)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000U)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000U)        /*!<Bit 1 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002U)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004U)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008U)        /*!<Memory type                               */
+#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
 
-#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030U)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
 
-#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040U)        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
 
-#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00U)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200U)        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400U)        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800U)        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000U)        /*!<Bit 3 */
+#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
 
-#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000U)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000U)        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000U)        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000U)        /*!<Bit 3 */
+#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
 
-#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000U)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000U)        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000U)        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000U)        /*!<Bit 2 */
+#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
 
 /*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        ((uint32_t)0x01U)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        ((uint32_t)0x02U)               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        ((uint32_t)0x04U)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       ((uint32_t)0x08U)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       ((uint32_t)0x10U)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       ((uint32_t)0x20U)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      ((uint32_t)0x40U)               /*!<FIFO empty                                  */
+#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
 
 /******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FFU)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FFU)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FFU)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00U)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000U)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000U)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FFU)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FFU)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FFU)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00U)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000U)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000U)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FFU)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
+#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
+#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
+#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00U)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000U)        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000U)        /*!<Bit 7 */
+#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000U)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000U)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000U)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000U)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000U)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000U)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000U)        /*!<Bit 7 */
+#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
 
-#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000U)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000U)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000U)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000U)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000U)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000U)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000U)        /*!<Bit 7 */
+#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
 
 /******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFFU)        /*!<ECC result */
+#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
 
 /******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000U)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003U)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000CU)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030U)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040U)        /*!<Number of internal bank */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
 
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180U)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100U)        /*!<Bit 1 */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200U)        /*!<Write protection */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
 
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00U)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
 
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000U)        /*!<Read burst */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
 
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000U)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000U)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000U)        /*!<Bit 1 */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
 
 /******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000FU)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
                                             
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0U)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00U)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
 
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000U)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000U)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000U)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
 
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000U)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000U)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000U)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000U)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
 
 /******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007U)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
                                             
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008U)        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
 
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010U)        /*!<Command target 1 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
 
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0U)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080U)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100U)        /*!<Bit 3 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
 
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00U)        /*!<MRD[12:0] bits (Mode register definition) */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
 
 /******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001U)        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
 
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFEU)        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
 
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000U)        /*!<RES interupt enable */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
 
 /******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001U)        /*!<Refresh error flag */
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
 
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006U)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004U)        /*!<Bit 1 */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
 
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018U)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008U)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010U)        /*!<Bit 1 */
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020U)        /*!<Busy status */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
 
 
 
@@ -4954,235 +4978,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003U)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001U)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000CU)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004U)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030U)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010U)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0U)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040U)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300U)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100U)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00U)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400U)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000U)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000U)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000U)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000U)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000U)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000U)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000U)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000U)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000U)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000U)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000U)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000U)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000U)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000U)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000U)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000U)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000U)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000U)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000U)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000U)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000U)
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001U)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002U)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004U)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008U)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010U)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020U)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040U)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080U)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100U)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200U)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400U)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800U)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000U)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000U)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000U)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000U)
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003U)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001U)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000CU)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004U)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030U)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010U)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0U)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040U)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300U)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100U)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00U)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400U)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000U)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000U)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000U)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000U)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000U)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000U)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000U)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000U)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000U)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000U)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000U)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000U)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000U)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000U)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000U)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000U)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000U)
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003U)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001U)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000CU)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004U)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030U)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010U)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0U)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040U)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300U)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100U)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00U)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400U)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000U)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000U)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000U)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000U)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000U)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000U)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000U)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000U)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000U)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000U)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000U)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000U)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000U)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000U)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000U)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000U)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000U)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000U)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000U)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000U)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000U)
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001U)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002U)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004U)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008U)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010U)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020U)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040U)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080U)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100U)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200U)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400U)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800U)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000U)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000U)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000U)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000U)
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -5202,22 +5226,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001U)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002U)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004U)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008U)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010U)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020U)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040U)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080U)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100U)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200U)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400U)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800U)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000U)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000U)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000U)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000U)
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -5237,57 +5261,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001U)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002U)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004U)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008U)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010U)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020U)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040U)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080U)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100U)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200U)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400U)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800U)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000U)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000U)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000U)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000U)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000U)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000U)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000U)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000U)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000U)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000U)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000U)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000U)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000U)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000U)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000U)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000U)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000U)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000U)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000U)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000U)
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001U)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002U)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004U)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008U)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010U)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020U)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040U)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080U)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100U)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200U)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400U)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800U)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000U)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000U)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000U)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000U)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000U)
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5295,32 +5319,32 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         ((uint32_t)0x00000004U)
-#define HASH_CR_DMAE                         ((uint32_t)0x00000008U)
-#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030U)
-#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010U)
-#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020U)
-#define HASH_CR_MODE                         ((uint32_t)0x00000040U)
-#define HASH_CR_ALGO                         ((uint32_t)0x00040080U)
-#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080U)
-#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000U)
-#define HASH_CR_NBW                          ((uint32_t)0x00000F00U)
-#define HASH_CR_NBW_0                        ((uint32_t)0x00000100U)
-#define HASH_CR_NBW_1                        ((uint32_t)0x00000200U)
-#define HASH_CR_NBW_2                        ((uint32_t)0x00000400U)
-#define HASH_CR_NBW_3                        ((uint32_t)0x00000800U)
-#define HASH_CR_DINNE                        ((uint32_t)0x00001000U)
-#define HASH_CR_MDMAT                        ((uint32_t)0x00002000U)
-#define HASH_CR_LKEY                         ((uint32_t)0x00010000U)
+#define HASH_CR_INIT                         0x00000004U
+#define HASH_CR_DMAE                         0x00000008U
+#define HASH_CR_DATATYPE                     0x00000030U
+#define HASH_CR_DATATYPE_0                   0x00000010U
+#define HASH_CR_DATATYPE_1                   0x00000020U
+#define HASH_CR_MODE                         0x00000040U
+#define HASH_CR_ALGO                         0x00040080U
+#define HASH_CR_ALGO_0                       0x00000080U
+#define HASH_CR_ALGO_1                       0x00040000U
+#define HASH_CR_NBW                          0x00000F00U
+#define HASH_CR_NBW_0                        0x00000100U
+#define HASH_CR_NBW_1                        0x00000200U
+#define HASH_CR_NBW_2                        0x00000400U
+#define HASH_CR_NBW_3                        0x00000800U
+#define HASH_CR_DINNE                        0x00001000U
+#define HASH_CR_MDMAT                        0x00002000U
+#define HASH_CR_LKEY                         0x00010000U
 
 /******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBLW                        ((uint32_t)0x0000001FU)
-#define HASH_STR_NBLW_0                      ((uint32_t)0x00000001U)
-#define HASH_STR_NBLW_1                      ((uint32_t)0x00000002U)
-#define HASH_STR_NBLW_2                      ((uint32_t)0x00000004U)
-#define HASH_STR_NBLW_3                      ((uint32_t)0x00000008U)
-#define HASH_STR_NBLW_4                      ((uint32_t)0x00000010U)
-#define HASH_STR_DCAL                        ((uint32_t)0x00000100U)
+#define HASH_STR_NBLW                        0x0000001FU
+#define HASH_STR_NBLW_0                      0x00000001U
+#define HASH_STR_NBLW_1                      0x00000002U
+#define HASH_STR_NBLW_2                      0x00000004U
+#define HASH_STR_NBLW_3                      0x00000008U
+#define HASH_STR_NBLW_4                      0x00000010U
+#define HASH_STR_DCAL                        0x00000100U
 /* Aliases for HASH_STR register */
 #define HASH_STR_NBW                         HASH_STR_NBLW
 #define HASH_STR_NBW_0                       HASH_STR_NBLW_0
@@ -5330,17 +5354,17 @@ USB_OTG_HostChannelTypeDef;
 #define HASH_STR_NBW_4                       HASH_STR_NBLW_4
 
 /******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIE                       ((uint32_t)0x00000001U)
-#define HASH_IMR_DCIE                        ((uint32_t)0x00000002U)
+#define HASH_IMR_DINIE                       0x00000001U
+#define HASH_IMR_DCIE                        0x00000002U
 /* Aliases for HASH_IMR register */
 #define HASH_IMR_DINIM                       HASH_IMR_DINIE
 #define HASH_IMR_DCIM                        HASH_IMR_DCIE
 
 /******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        ((uint32_t)0x00000001U)
-#define HASH_SR_DCIS                         ((uint32_t)0x00000002U)
-#define HASH_SR_DMAS                         ((uint32_t)0x00000004U)
-#define HASH_SR_BUSY                         ((uint32_t)0x00000008U)
+#define HASH_SR_DINIS                        0x00000001U
+#define HASH_SR_DCIS                         0x00000002U
+#define HASH_SR_DMAS                         0x00000004U
+#define HASH_SR_BUSY                         0x00000008U
 
 /******************************************************************************/
 /*                                                                            */
@@ -5348,97 +5372,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001U)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002U)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008U)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010U)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020U)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040U)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080U)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100U)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200U)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400U)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800U)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000U)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000U)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000U)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003FU)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020U)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100U)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200U)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400U)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800U)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000U)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FEU)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300U)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001U)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002U)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004U)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008U)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010U)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020U)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040U)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080U)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100U)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200U)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000U)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001U)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FEU)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FFU)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001U)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002U)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004U)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008U)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010U)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040U)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080U)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100U)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200U)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400U)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800U)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000U)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000U)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000U)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001U)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002U)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004U)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010U)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020U)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040U)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080U)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00U)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFFU)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000U)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000U)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003FU)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000FU)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010U)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -5446,20 +5470,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFFU)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07U)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04U)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFFU)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01U)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02U)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -5470,148 +5494,148 @@ USB_OTG_HostChannelTypeDef;
 
 /********************  Bit definition for LTDC_SSCR register  *****************/
 
-#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FFU)              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000U)              /*!< Horizontal Synchronization Width */
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
 
 /********************  Bit definition for LTDC_BPCR register  *****************/
 
-#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FFU)              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000U)              /*!< Accumulated Horizontal Back Porch */
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
 
 /********************  Bit definition for LTDC_AWCR register  *****************/
 
-#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FFU)              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000U)              /*!< Accumulated Active Width */
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
 
 /********************  Bit definition for LTDC_TWCR register  *****************/
 
-#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FFU)              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000U)              /*!< Total Width */
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
 
 /********************  Bit definition for LTDC_GCR register  ******************/
 
-#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001U)              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        ((uint32_t)0x00000070U)              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        ((uint32_t)0x00000700U)              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        ((uint32_t)0x00007000U)              /*!< Dither Red Width */
-#define LTDC_GCR_DEN                        ((uint32_t)0x00010000U)              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000U)              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000U)              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000U)              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000U)              /*!< Horizontal Synchronization Polarity */
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
 
 /* Legacy defines */
 #define LTDC_GCR_DTEN                       LTDC_GCR_DEN
 
 /********************  Bit definition for LTDC_SRCR register  *****************/
 
-#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001U)               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002U)               /*!< Vertical Blanking Reload */
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
 
 /********************  Bit definition for LTDC_BCCR register  *****************/
 
-#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FFU)              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00U)              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000U)              /*!< Background Red value */
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
 
 /********************  Bit definition for LTDC_IER register  ******************/
 
-#define LTDC_IER_LIE                        ((uint32_t)0x00000001U)              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       ((uint32_t)0x00000002U)              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004U)              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       ((uint32_t)0x00000008U)              /*!< Register Reload interrupt enable */
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
 
 /********************  Bit definition for LTDC_ISR register  ******************/
 
-#define LTDC_ISR_LIF                        ((uint32_t)0x00000001U)              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002U)              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004U)              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008U)              /*!< Register Reload interrupt Flag */
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_ICR register  ******************/
 
-#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001U)              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002U)              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004U)              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008U)              /*!< Clears Register Reload interrupt Flag */
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
 
 /********************  Bit definition for LTDC_LIPCR register  ****************/
 
-#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FFU)              /*!< Line Interrupt Position */
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
 
 /********************  Bit definition for LTDC_CPSR register  *****************/
 
-#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFFU)              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000U)              /*!< Current X Position */
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
 
 /********************  Bit definition for LTDC_CDSR register  *****************/
 
-#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001U)              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002U)              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004U)              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008U)              /*!< Horizontal Synchronization Status */
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
 
 /********************  Bit definition for LTDC_LxCR register  *****************/
 
-#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001U)              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002U)              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010U)              /*!< Color Lockup Table Enable */
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
 
 /********************  Bit definition for LTDC_LxWHPCR register  **************/
 
-#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFFU)              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000U)              /*!< Window Horizontal Stop Position */
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
 
 /********************  Bit definition for LTDC_LxWVPCR register  **************/
 
-#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFFU)              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000U)              /*!< Window Vertical Stop Position */
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
 
 /********************  Bit definition for LTDC_LxCKCR register  ***************/
 
-#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FFU)              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00U)              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000U)              /*!< Color Key Red value */
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
 
 /********************  Bit definition for LTDC_LxPFCR register  ***************/
 
-#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007U)              /*!< Pixel Format */
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
 
 /********************  Bit definition for LTDC_LxCACR register  ***************/
 
-#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FFU)              /*!< Constant Alpha */
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
 
 /********************  Bit definition for LTDC_LxDCCR register  ***************/
 
-#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FFU)              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00U)              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000U)              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000U)              /*!< Default Color Alpha */
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
                                 
 /********************  Bit definition for LTDC_LxBFCR register  ***************/
 
-#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007U)              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700U)              /*!< Blending Factor 1 */
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
 
 /********************  Bit definition for LTDC_LxCFBAR register  **************/
 
-#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFFU)              /*!< Color Frame Buffer Start Address */
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
 
 /********************  Bit definition for LTDC_LxCFBLR register  **************/
 
-#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFFU)              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000U)              /*!< Color Frame Buffer Pitch in bytes */
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
 
 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
 
-#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FFU)              /*!< Frame Buffer Line Number */
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
 
 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
 
-#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FFU)              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00U)              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000U)              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000U)              /*!< CLUT address */
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
 
 
 /******************************************************************************/
@@ -5620,39 +5644,39 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001U)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002U)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004U)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008U)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010U)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0U)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020U)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040U)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080U)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000U)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020U)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040U)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060U)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080U)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0U)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0U)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0U)     /*!< PVD level 7 */
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100U)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200U)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400U)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800U)     /*!< Main regulator Low Voltage Scaling in Stop mode            */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000U)     /*!< Refer to AN4073 on how to use this bit */ 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000U)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000U)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000U)     /*!< Bit 1 */
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000U)     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000U)     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000U)     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000U)     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000U)     /*!< Bit 1                               */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
 
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
@@ -5660,16 +5684,16 @@ USB_OTG_HostChannelTypeDef;
 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001U)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002U)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004U)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008U)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100U)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200U)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000U)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000U)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000U)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000U)     /*!< Under Drive ready                                */
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -5680,523 +5704,523 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001U)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002U)
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8U)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008U)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010U)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020U)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040U)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080U)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00U)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100U)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200U)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400U)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800U)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000U)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000U)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000U)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000U)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000U)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000U)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000U)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000U)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000U)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000U)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000U)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000U)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000U)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000U)
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003FU)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001U)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002U)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004U)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008U)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010U)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020U)
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0U)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040U)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080U)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100U)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200U)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400U)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800U)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000U)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000U)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000U)
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000U)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000U)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000U)
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000U)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000U)
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000U)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000U)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000U)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000U)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000U)
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003U)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001U)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002U)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000U)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001U)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002U)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000CU)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004U)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008U)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000U)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004U)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008U)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0U)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010U)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020U)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040U)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080U)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000U)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080U)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090U)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0U)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0U)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0U)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0U)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0U)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0U)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00U)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000U)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000U)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000U)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000U)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000U)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000U)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000U)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000U)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000U)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000U)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000U)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000U)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000U)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000U)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000U)
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000U)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000U)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000U)
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000U)
+#define  RCC_CFGR_I2SSRC                     0x00800000U
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000U)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000U)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000U)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000U)
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000U)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000U)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000U)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000U)
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000U)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000U)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000U)
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001U)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002U)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004U)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008U)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010U)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020U)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040U)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080U)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100U)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200U)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400U)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800U)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000U)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000U)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000U)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000U)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000U)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000U)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000U)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000U)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000U)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000U)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000U)
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001U)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002U)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004U)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008U)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010U)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020U)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040U)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080U)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100U)
-#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200U)
-#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400U)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000U)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000U)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000U)
-#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000U)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000U)
-#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x20000000U)
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001U)
-#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010U)
-#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020U)
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
+#define  RCC_AHB2RSTR_HASHRST                0x00000020U
  /* maintained for legacy purpose */
  #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040U)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080U)
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001U)
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001U)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002U)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004U)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008U)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010U)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020U)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040U)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080U)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100U)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800U)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000U)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000U)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000U)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000U)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000U)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000U)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000U)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000U)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000U)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000U)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000U)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000U)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000U)
-#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000U)
-#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000U)
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001U)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002U)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010U)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020U)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100U)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800U)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000U)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000U)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000U)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000U)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000U)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000U)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000U)
-#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000U)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000U)
-#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000U)
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001U)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002U)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004U)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008U)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010U)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020U)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040U)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080U)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100U)
-#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200U)
-#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400U)
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
 
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000U)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000U)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000U)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000U)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000U)
-#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000U)
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
 
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000U)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000U)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000U)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000U)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000U)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000U)
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001U)
-#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010U)
-#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020U)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040U)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080U)
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
+#define  RCC_AHB2ENR_HASHEN                  0x00000020U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001U)
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004U)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008U)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010U)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020U)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040U)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080U)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100U)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000U)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000U)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000U)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000U)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000U)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000U)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000U)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000U)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000U)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000U)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000U)
-#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000U)
-#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000U)
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001U)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002U)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010U)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020U)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100U)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200U)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400U)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800U)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000U)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000U)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000U)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000U)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000U)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000U)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000U)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000U)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000U)
-#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000U)
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001U)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002U)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004U)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008U)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010U)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020U)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040U)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080U)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100U)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200U)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400U)
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
 
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000U)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000U)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000U)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000U)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000U)
-#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000U)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000U)
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
 
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000U)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000U)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000U)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000U)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000U)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000U)
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001U)
-#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010U)
-#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020U)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040U)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080U)
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
+#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001U)
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004U)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008U)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010U)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020U)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040U)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080U)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100U)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000U)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000U)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000U)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000U)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000U)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000U)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000U)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000U)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000U)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000U)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000U)
-#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000U)
-#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000U)
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001U)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002U)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010U)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020U)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100U)
-#define  RCC_APB2LPENR_ADC2LPEN              ((uint32_t)0x00000200U)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400U)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800U)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000U)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000U)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000U)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000U)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000U)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000U)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000U)
-#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000U)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000U)
-#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000U)
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001U)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002U)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004U)
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300U)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100U)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200U)
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000U)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000U)
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001U)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002U)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000U)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000U)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000U)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000U)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000U)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000U)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000U)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000U)
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFFU)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000U)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000U)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000U)
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
 
 
 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0U)
-#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040U)
-#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080U)
-#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100U)
-#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200U)
-#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400U)
-#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800U)
-#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000U)
-#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000U)
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
 
-#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000U)
-#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000U)
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
 
-#define  RCC_PLLSAICFGR_PLLSAIR              ((uint32_t)0x70000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_0            ((uint32_t)0x10000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_1            ((uint32_t)0x20000000U)
-#define  RCC_PLLSAICFGR_PLLSAIR_2            ((uint32_t)0x40000000U)
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
 
 /********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001FU)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00U)
-#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000U)
-#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000U)
-#define  RCC_DCKCFGR_SAI1ASRC_0              ((uint32_t)0x00100000U)
-#define  RCC_DCKCFGR_SAI1ASRC_1              ((uint32_t)0x00200000U)
-#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000U)
-#define  RCC_DCKCFGR_SAI1BSRC_0              ((uint32_t)0x00400000U)
-#define  RCC_DCKCFGR_SAI1BSRC_1              ((uint32_t)0x00800000U)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000U)
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
+#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
+#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
+#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
+#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
+#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
+#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
 
 
 /******************************************************************************/
@@ -6205,15 +6229,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004U)
-#define RNG_CR_IE                            ((uint32_t)0x00000008U)
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
 
 /********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001U)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002U)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004U)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020U)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040U)
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
 
 /******************************************************************************/
 /*                                                                            */
@@ -6221,379 +6245,379 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000U)
-#define RTC_TR_HT                            ((uint32_t)0x00300000U)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000U)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000U)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000U)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000U)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000U)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000U)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000U)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000U)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000U)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000U)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000U)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00U)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100U)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200U)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400U)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800U)
-#define RTC_TR_ST                            ((uint32_t)0x00000070U)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010U)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020U)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040U)
-#define RTC_TR_SU                            ((uint32_t)0x0000000FU)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001U)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002U)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004U)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008U)
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000U)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000U)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000U)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000U)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000U)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000U)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000U)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000U)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000U)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000U)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000U)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000U)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000U)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000U)
-#define RTC_DR_MT                            ((uint32_t)0x00001000U)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00U)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100U)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200U)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400U)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800U)
-#define RTC_DR_DT                            ((uint32_t)0x00000030U)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010U)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020U)
-#define RTC_DR_DU                            ((uint32_t)0x0000000FU)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001U)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002U)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004U)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008U)
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000U)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000U)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000U)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000U)
-#define RTC_CR_POL                           ((uint32_t)0x00100000U)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000U)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000U)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000U)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000U)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000U)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000U)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000U)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000U)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800U)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400U)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200U)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100U)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080U)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040U)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020U)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010U)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008U)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007U)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001U)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002U)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004U)
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000U)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000U)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000U)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000U)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800U)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400U)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200U)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100U)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080U)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040U)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020U)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010U)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008U)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004U)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002U)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001U)
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000U)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFFU)
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFFU)
+#define RTC_WUTR_WUT                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080U)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001FU)
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000U)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000U)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000U)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000U)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000U)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000U)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000U)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000U)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000U)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000U)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000U)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000U)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000U)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000U)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000U)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000U)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000U)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000U)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000U)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000U)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000U)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000U)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000U)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000U)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000U)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00U)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100U)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200U)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400U)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800U)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080U)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070U)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010U)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020U)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040U)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000FU)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001U)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002U)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004U)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008U)
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FFU)
+#define RTC_WPR_KEY                          0x000000FFU
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFFU)
+#define RTC_SSR_SS                           0x0000FFFFU
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFFU)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000U)
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000U)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000U)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000U)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000U)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000U)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000U)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000U)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000U)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000U)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000U)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000U)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000U)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000U)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00U)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100U)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200U)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400U)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800U)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070U)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010U)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020U)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040U)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000FU)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000U)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000U)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000U)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000U)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000U)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00U)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100U)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200U)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400U)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800U)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030U)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010U)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020U)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000FU)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001U)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002U)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004U)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008U)
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFFU)
+#define RTC_TSSSR_SS                         0x0000FFFFU
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000U)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000U)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000U)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FFU)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001U)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002U)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004U)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008U)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010U)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020U)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040U)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080U)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100U)
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000U)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000U)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000U)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000U)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000U)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000U)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000U)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800U)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800U)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000U)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700U)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100U)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200U)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400U)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080U)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010U)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008U)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004U)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002U)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001U)
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000U)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000U)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000U)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000U)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000U)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFFU)
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP0R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP1R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP2R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP3R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP4R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP5R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP6R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP7R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP8R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP9R                            0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP10R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP11R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP12R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP13R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP14R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP15R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP16R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP17R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP18R                           0xFFFFFFFFU
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFFU)
+#define RTC_BKP19R                           0xFFFFFFFFU
 
 /******************************************************************************/
 /*                                                                            */
@@ -6601,150 +6625,152 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003U)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
 
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030U)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010U)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020U)        /*!<Bit 1 */
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
 
 /*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003U)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
 
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000CU)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004U)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008U)        /*!<Bit 1 */
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
 
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0U)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020U)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040U)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080U)        /*!<Bit 2 */
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
 
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100U)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200U)        /*!<ClocK STRobing edge      */
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
 
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00U)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400U)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800U)        /*!<Bit 1 */
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
 
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000U)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000U)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000U)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000U)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000U)        /*!<No Divider Configuration   */
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
 
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00F00000U)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00100000U)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00200000U)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00400000U)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00800000U)        /*!<Bit 3  */
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
 
 /*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000007U)        /*!<FTH[2:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xCR2_FTH_2                   ((uint32_t)0x00000004U)        /*!<Bit 2 */
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
 
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008U)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010U)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020U)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040U)        /*!<Muate value                      */
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
 
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80U)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080U)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100U)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200U)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400U)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800U)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000U)        /*!<Bit 5 */
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
 
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00002000U)        /*!< Complement Bit             */
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
 
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000U)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000U)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000U)        /*!<Bit 1 */
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
 
 /******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FFU)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040U)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080U)        /*!<Bit 7 */
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
 
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00U)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800U)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000U)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000U)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000U)        /*!<Bit 6 */
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
 
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000U)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000U)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000U)        /*!<Frame Synchronization OFFset      */
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
 
 /******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001FU)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008U)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010U)        /*!<Bit 4 */
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
 
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0U)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080U)        /*!<Bit 1 */
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
 
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00U)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100U)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200U)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400U)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800U)        /*!<Bit 3 */
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
 
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000U)        /*!<SLOTEN[15:0] (Slot Enable)  */
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
 
 /*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001U)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002U)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004U)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008U)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010U)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020U)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040U)        /*!<Late frame synchronization detection interrupt enable          */
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
 
 /********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001U)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002U)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004U)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008U)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010U)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020U)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040U)         /*!<Late frame synchronization detection           */
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
 
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000U)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000U)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000U)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00040000U)         /*!<Bit 2 */
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
 
 /******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001U)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002U)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004U)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008U)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010U)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020U)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040U)        /*!<Clear Late frame synchronization detection           */
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
 
 /******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFFU)        
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
 
 
 /******************************************************************************/
@@ -6753,157 +6779,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03U)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02U)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FFU)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100U)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200U)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400U)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800U)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800U)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000U)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000U)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000U)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFFU)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003FU)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0U)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040U)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080U)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100U)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200U)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400U)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800U)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000U)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000U)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000U)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3FU)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFFU)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFFU)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFFU)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001U)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002U)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004U)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008U)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0U)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100U)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200U)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400U)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800U)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFFU)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001U)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002U)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004U)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008U)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010U)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020U)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040U)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080U)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100U)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200U)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400U)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800U)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000U)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000U)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000U)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000U)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000U)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000U)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000U)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000U)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000U)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000U)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000U)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001U)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002U)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004U)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008U)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010U)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020U)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040U)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080U)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100U)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200U)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400U)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000U)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000U)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001U)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002U)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004U)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008U)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010U)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020U)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040U)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080U)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100U)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200U)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400U)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800U)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000U)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000U)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000U)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000U)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000U)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000U)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000U)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000U)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000U)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000U)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000U)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000U)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFFU)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFFU)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6911,84 +6937,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001U)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002U)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004U)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038U)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008U)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010U)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020U)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040U)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080U)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100U)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200U)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400U)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800U)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000U)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000U)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000U)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000U)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001U)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002U)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004U)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010U)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020U)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040U)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080U)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001U)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002U)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004U)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008U)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010U)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020U)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040U)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080U)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100U)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFFU)            /*!<Data Register           */
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFFU)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFFU)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001U)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006U)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008U)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030U)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080U)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300U)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100U)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200U)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400U)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800U)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FFU)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100U)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200U)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -6996,290 +7022,290 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001U)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002U)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004U)
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
 
-#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100U) /*!< User Flash Bank mode    */
-#define SYSCFG_SWP_FMC                  ((uint32_t)0x00000C00U) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000U) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000U) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
 
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000U) /*!<Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000FU) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0U) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00U) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000U) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
 /** 
   * @brief   EXTI0 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000U) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001U) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002U) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003U) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004U) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x0005U) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x0006U) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007U) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x0008U) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x0009U) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x000AU) /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
 
 /** 
   * @brief   EXTI1 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000U) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010U) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020U) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030U) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040U) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x0050U) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x0060U) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070U) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x0080U) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x0090U) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x00A0U) /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
 
 
 /** 
   * @brief   EXTI2 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000U) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100U) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200U) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300U) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400U) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x0500U) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x0600U) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700U) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x0800U) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x0900U) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x0A00U) /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
 
 
 /** 
   * @brief   EXTI3 configuration  
   */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000U) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000U) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000U) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000U) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000U) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x5000U) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x6000U) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000U) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x8000U) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x9000U) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0xA000U) /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000FU) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0U) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00U) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000U) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
 /** 
   * @brief   EXTI4 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000U) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001U) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002U) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003U) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004U) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x0005U) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x0006U) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007U) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x0008U) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x0009U) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x000AU) /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
 
 /** 
   * @brief   EXTI5 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000U) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010U) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020U) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030U) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040U) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x0050U) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x0060U) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070U) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x0080U) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x0090U) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x00A0U) /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
 
 /** 
   * @brief   EXTI6 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000U) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100U) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200U) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300U) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400U) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x0500U) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x0600U) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700U) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x0800U) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x0900U) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x0A00U) /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
 
 
 /** 
   * @brief   EXTI7 configuration  
   */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000U) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000U) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000U) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000U) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000U) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x5000U) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x6000U) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000U) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x8000U) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x9000U) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0xA000U) /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000FU) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0U) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00U) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000U) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
            
 /** 
   * @brief   EXTI8 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000U) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001U) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002U) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003U) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004U) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x0005U) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x0006U) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007U) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x0008U) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x0009U) /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
 
 /** 
   * @brief   EXTI9 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000U) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010U) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020U) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030U) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040U) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x0050U) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x0060U) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070U) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x0080U) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x0090U) /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
 
 
 /** 
   * @brief   EXTI10 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000U) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100U) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200U) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300U) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400U) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x0500U) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x0600U) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700U) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x0800U) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x0900U) /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
 
 
 /** 
   * @brief   EXTI11 configuration  
   */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000U) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000U) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000U) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000U) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000U) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x5000U) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x6000U) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000U) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x8000U) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x9000U) /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000FU) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0U) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00U) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000U) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
 /** 
   * @brief   EXTI12 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000U) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001U) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002U) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003U) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004U) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x0005U) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x0006U) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007U) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x0008U) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x0009U) /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
 
 
 /** 
   * @brief   EXTI13 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000U) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010U) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020U) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030U) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040U) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x0050U) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x0060U) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070U) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x0008U) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x0009U) /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
 
 
 /** 
   * @brief   EXTI14 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000U) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100U) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200U) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300U) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400U) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x0500U) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x0600U) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700U) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x0800U) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x0900U) /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
 
 
 /** 
   * @brief   EXTI15 configuration  
   */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000U) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000U) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000U) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000U) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000U) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x5000U) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x6000U) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000U) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x8000U) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x9000U) /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001U) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100U) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7287,298 +7313,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001U)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002U)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004U)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008U)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010U)            /*!<Direction             */
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060U)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020U)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040U)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080U)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300U)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001U)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004U)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008U)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070U)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080U)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100U)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200U)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400U)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800U)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000U)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000U)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000U)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007U)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070U)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080U)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00U)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800U)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000U)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000U)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000U)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001U)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020U)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040U)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080U)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100U)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200U)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000U)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000U)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000U)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001U)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002U)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004U)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008U)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010U)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020U)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040U)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080U)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200U)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400U)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000U)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01U)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02U)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04U)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08U)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10U)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20U)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40U)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80U)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003U)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004U)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008U)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070U)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080U)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300U)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400U)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800U)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000U)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000U)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000CU)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0U)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00U)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000U)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003U)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004U)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008U)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070U)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080U)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300U)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400U)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800U)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000U)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000U)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000CU)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0U)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00U)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000U)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000U)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000U)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001U)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002U)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004U)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008U)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010U)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020U)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040U)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080U)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100U)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200U)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400U)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800U)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000U)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000U)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000U)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFU)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFFU)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFU)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFFU)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFFU)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FFU)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300U)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200U)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400U)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800U)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000U)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000U)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000U)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000U)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001FU)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010U)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00U)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100U)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200U)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400U)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800U)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000U)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFFU)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0U)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040U)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080U)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00U)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400U)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800U)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -7587,82 +7613,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001U)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002U)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004U)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008U)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010U)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020U)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040U)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080U)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100U)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200U)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FFU)            /*!<Data value */
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000FU)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0U)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001U)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002U)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004U)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008U)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010U)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020U)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040U)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100U)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200U)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400U)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800U)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000U)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000U)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000U)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000FU)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020U)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040U)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100U)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200U)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400U)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800U)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000U)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000U)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000U)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000U)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001U)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002U)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004U)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008U)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010U)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020U)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040U)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080U)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100U)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200U)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400U)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800U)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FFU)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040U)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080U)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00U)            /*!<Guard time value */
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -7670,35 +7696,54 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7FU)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01U)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02U)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04U)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08U)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10U)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20U)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40U)               /*!<Bit 6 */
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80U)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007FU)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001U)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002U)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004U)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008U)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010U)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020U)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040U)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180U)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080U)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100U)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200U)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01U)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -7707,46 +7752,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFFU)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000U)
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001U)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002U)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004U)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020U)
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0U)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040U)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080U)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001U)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002U)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004U)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008U)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010U)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020U)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040U)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080U)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100U)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400U)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800U)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000U)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000U)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000U)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001U)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002U)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000U)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000U)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
 
 /******************************************************************************/
 /*                                                                            */
@@ -7754,91 +7799,91 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000U)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000U)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000U)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000U)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000U)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000U)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000U)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000U)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000U)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000U)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000U)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000U)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000U)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000U)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000U)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800U)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400U)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200U)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080U)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060U)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000U)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020U)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040U)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060U)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010U)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008U)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004U)  /* Receiver enable */
+  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
 
 /* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000U)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400U)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200U)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100U)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0U)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040U)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080U)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0U)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020U)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010U)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008U)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004U)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002U)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001U)  /* Promiscuous mode */
+#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFFU)  /* Hash table high */
+#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFFU)  /* Hash table low */
+#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800U)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0U)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001CU)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000U)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004U)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008U)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000CU)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010U)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002U)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001U)  /* MII busy */ 
+#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
   
 /* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFFU)  /* MII data: read/write data from/to PHY */
+#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000U)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080U)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030U)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000U)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010U)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020U)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030U)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008U)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004U)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002U)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001U)  /* Flow control busy/backpressure activate */
+#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
 
 /* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000U)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFFU)  /* VLAN tag identifier (for receive frames) */
+#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
 
 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFFU)  /* Wake-up frame filter register data */
+#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
@@ -7852,334 +7897,334 @@ USB_OTG_HostChannelTypeDef;
    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
 
 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000U)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200U)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040U)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020U)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004U)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002U)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001U)  /* Power Down */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
 
 /* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200U)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040U)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020U)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010U)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008U)  /* PMT status */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
 
 /* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200U)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008U)  /* PMT interrupt mask */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
 
 /* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFFU)  /* MAC address0 high */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
 
 /* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFFU)  /* MAC address0 low */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
 
 /* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFFU)  /* MAC address1 high */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFFU)  /* MAC address1 low */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
 
 /* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFFU)  /* MAC address1 high */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
 
 /* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFFU)  /* MAC address2 low */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
 
 /* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000U)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000U)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000U)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000U)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000U)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000U)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000U)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000U)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000U)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFFU)  /* MAC address3 high */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
 
 /* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFFU)  /* MAC address3 low */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
 
 /******************************************************************************/
 /*                Ethernet MMC Registers bits definition                      */
 /******************************************************************************/
 
 /* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020U)  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010U)  /* MMC counter preset */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008U)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004U)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002U)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001U)  /* Counters Reset */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000U)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040U)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020U)  /* Set when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000U)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000U)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000U)  /* Set when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000U)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040U)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020U)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000U)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000U)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000U)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFFU)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFFU)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFFU)  /* Number of good frames transmitted. */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
 
 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFFU)  /* Number of frames received with CRC error. */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
 
 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFFU)  /* Number of frames received with alignment (dribble) error */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
 
 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFFU)  /* Number of good unicast frames received. */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
 
 /******************************************************************************/
 /*               Ethernet PTP Registers bits definition                       */
 /******************************************************************************/
 
 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000U)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000U)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000U)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000U)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000U)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800U)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400U)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200U)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100U)  /* Time stamp snapshot for all received frames enable */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
 
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020U)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010U)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008U)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004U)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002U)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001U)  /* Time stamp enable */
+#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
 
 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FFU)  /* System time Sub-second increment value */
+#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
 
 /* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFFU)  /* System Time second */
+#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000U)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFFU)  /* System Time sub-seconds */
+#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFFU)  /* Time stamp update seconds */
+#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000U)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFFU)  /* Time stamp update sub-seconds */
+#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
 
 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFFU)  /* Time stamp addend */
+#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
 
 /* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFFU)  /* Target time stamp high */
+#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
 
 /* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFFU)  /* Target time stamp low */
+#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
 
 /* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020U)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010U)  /* Time stamp seconds overflow */
+#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
 
 /******************************************************************************/
 /*                 Ethernet DMA Registers bits definition                     */
 /******************************************************************************/
 
 /* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000U)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000U)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000U)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000U)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000U)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000U)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000U)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000U)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00U)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000U)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080U)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007CU)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002U)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001U)  /* Software reset */
+#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
 
 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFFU)  /* Transmit poll demand */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
 
 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFFU)  /* Receive poll demand  */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
 
 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFFU)  /* Start of receive list */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
 
 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFFU)  /* Start of transmit list */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
 
 /* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000U)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000U)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000U)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000U)  /* Error bits status */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
   /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000U)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000U)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000U)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000U)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000U)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000U)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000U)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000U)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000U)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000U)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000U)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000U)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000U)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000U)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000U)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000U)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000U)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000U)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000U)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000U)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000U)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400U)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200U)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100U)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080U)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040U)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020U)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010U)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008U)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004U)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002U)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001U)  /* Transmit status */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
 
 /* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000U)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000U)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000U)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000U)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000U)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000U)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000U)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000U)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000U)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000U)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000U)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000U)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000U)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000U)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000U)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080U)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040U)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018U)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000U)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008U)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010U)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018U)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004U)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002U)  /* Start/stop receive */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
 
 /* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000U)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000U)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000U)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000U)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400U)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200U)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100U)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080U)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040U)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020U)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010U)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008U)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004U)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002U)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001U)  /* Transmit interrupt enable */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
 
 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000U)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000U)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000U)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFFU)  /* Number of frames missed by the controller */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFFU)  /* Host transmit descriptor address pointer */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFFU)  /* Host receive descriptor address pointer */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFFU)  /* Host transmit buffer address pointer */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
 
 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFFU)  /* Host receive buffer address pointer */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
 
 /******************************************************************************/
 /*                                                                            */
@@ -8187,654 +8232,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001U)            /*!< Session request success  */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002U)            /*!< Session request          */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100U)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200U)            /*!< HNP request              */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400U)            /*!< Host set HNP enable      */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800U)            /*!< Device HNP enabled       */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000U)            /*!< Connector ID status      */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000U)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000U)            /*!< A-session valid          */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000U)            /*!< B-session valid          */
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003U)            /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004U)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003U)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004U)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0U)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080U)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100U)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200U)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400U)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800U)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000U)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000U)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001U)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002U)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010U)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004U)            /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100U)            /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200U)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000U)            /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000U)            /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000U)            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001U)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002U)            /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004U)            /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008U)            /*!< Global OUT NAK status   */
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070U)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010U)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020U)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040U)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080U)            /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100U)            /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200U)            /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400U)            /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800U)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFFU)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFFU)            /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000U)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001U)            /*!< Suspend status   */
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006U)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008U)            /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00U)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001U)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001EU)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004U)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008U)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010U)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020U)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080U)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100U)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007U)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040U)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100U)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200U)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00U)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000U)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000U)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000U)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000U)            /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000U)            /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000U)            /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000U)            /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000U)            /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000U)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000U)            /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000U)            /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000U)            /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000U)            /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000U)            /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000U)            /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001U)            /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002U)            /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004U)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010U)            /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020U)            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0U)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040U)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080U)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100U)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200U)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400U)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000U)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000U)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFFU)            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000U)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000U)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000U)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000U)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFFU)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008U)            /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100U)            /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200U)            /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001U)            /*!< Current mode of operation           */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt             */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt                       */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008U)            /*!< Start of frame                      */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010U)            /*!< RxFIFO nonempty                     */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty            */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040U)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective            */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400U)            /*!< Early suspend                            */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800U)            /*!< USB suspend                              */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset                                */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000U)            /*!< Enumeration done                         */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt          */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000U)            /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000U)            /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000U)            /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000U)            /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt        */
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002U)            /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004U)            /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008U)            /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010U)            /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020U)            /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040U)            /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080U)            /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400U)            /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800U)            /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000U)            /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000U)            /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000U)            /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000U)            /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000U)            /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000U)            /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000U)            /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000U)            /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000U)            /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000U)            /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000U)            /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000U)            /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000U)            /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000U)            /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000U)            /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000U)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000U)            /*!< Resume/remote wakeup detected interrupt mask        */
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFFU)            /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000U)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFFU)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000FU)            /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000U)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFFU)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000U)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000FU)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0U)            /*!< Byte count */
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000U)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000U)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000U)            /*!<Bit 1 */
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000U)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000U)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000FU)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008U)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000U)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000U)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000U)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000U)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000U)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD            ((uint32_t)0x0000FFFFU)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT         ((uint32_t)0x0000FFFFU)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000U)            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFFU)            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000U)            /*!< Endpoint 0 TxFIFO depth                */
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFFU)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFFU)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000U)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000U)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000U)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000U)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000U)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000U)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000U)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000U)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000U)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000U)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000U)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001U)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002U)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FCU)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000U)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000U)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000U)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000U)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000U)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000U)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000U)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000U)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000U)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000U)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000U)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFFU)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002U)            /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000U)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000U)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000U)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000U)            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000U)            /*!< Enable the VBUS sensing device                               */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000U)            /*!< SOF output enable                                            */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000U)            /*!< VBUS sensing disable option                                  */
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002U)            /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000U)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFFU)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001U)            /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002U)            /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004U)            /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008U)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010U)            /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020U)            /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040U)            /*!< Port resume   */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080U)            /*!< Port suspend  */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100U)            /*!< Port reset    */
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00U)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000U)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000U)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000U)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000U)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000U)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000U)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000U)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000U)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008U)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020U)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100U)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200U)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000U)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000U)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000U)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFFU)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000U)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000U)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000U)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000U)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000U)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FFU)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800U)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000U)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000U)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000U)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000U)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000U)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000U)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000U)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000U)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000U)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000U)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000U)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000U)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000U)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000U)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000U)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007FU)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80U)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200U)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400U)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800U)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000U)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000U)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000U)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000U)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000U)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000U)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000U)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002U)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008U)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010U)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040U)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080U)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100U)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200U)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400U)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008U)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010U)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040U)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080U)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100U)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200U)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800U)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000U)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000U)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001U)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002U)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004U)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008U)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010U)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020U)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040U)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080U)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100U)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200U)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400U)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000U)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000U)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000U)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000U)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFFU)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFFU)            /*!< IN endpoint TxFIFO space available */
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFFU)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000U)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FFU)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000U)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000U)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000U)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000U)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000U)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000U)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000U)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000U)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000U)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000U)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000U)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000U)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001U)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002U)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008U)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010U)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040U)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000U)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFFU)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000U)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000U)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000U)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000U)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001U)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002U)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010U)            /*!<Bit 1 */
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
 
 
 /**
@@ -8926,8 +8971,10 @@ USB_OTG_HostChannelTypeDef;
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
 
 /******************************* SAI Instances ********************************/
-#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
                                      ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
 
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h
index 307d559a17..37f27d4560 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
   *            
   *          The file is the unique include file that the application programmer
@@ -78,7 +78,8 @@
     !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
     !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
     !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx)
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
   /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
   /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
   /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
@@ -101,6 +102,10 @@
                                    STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
   /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
                                    and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
 #endif
    
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -116,11 +121,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS version number V2.4.3
+  * @brief CMSIS version number V2.5.0
   */
 #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -160,7 +165,7 @@
 #elif defined(STM32F410Cx)
   #include "stm32f410cx.h"
 #elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"  
+  #include "stm32f410rx.h"
 #elif defined(STM32F411xE)
   #include "stm32f411xe.h"
 #elif defined(STM32F446xx)
@@ -169,6 +174,14 @@
   #include "stm32f469xx.h"
 #elif defined(STM32F479xx)
   #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
 #else
  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c
index 3f9ffe3159..4a221718de 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V2.4.3
-  * @date    22-January-2016
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from 
@@ -111,9 +111,10 @@
 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 /* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -340,7 +341,7 @@ void SystemInit_ExtMemCtl(void)
   __IO uint32_t tmp = 0x00;
 
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
   RCC->AHB1ENR |= 0x000001F8;
@@ -505,7 +506,7 @@ void SystemInit_ExtMemCtl(void)
  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #if defined (DATA_IN_ExtSDRAM)
   register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
+  register __IO uint32_t index;
 
 #if defined(STM32F446xx)
   /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
@@ -694,7 +695,7 @@ void SystemInit_ExtMemCtl(void)
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
 
 #if defined(DATA_IN_ExtSRAM)
 /*-- GPIOs Configuration -----------------------------------------------------*/
@@ -771,18 +772,19 @@ void SystemInit_ExtMemCtl(void)
   FMC_Bank1->BTCR[3]  = 0x00110212;
   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 #endif /* STM32F469xx || STM32F479xx */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
   /* Delay after an RCC peripheral clock enabling */
   tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001011;
   FSMC_Bank1->BTCR[3]  = 0x00000201;
   FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #endif /* DATA_IN_ExtSRAM */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
   (void)(tmp); 
 }
 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h
index 3fb34198c2..0b8a72d9ef 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f4xx.h
   * @author  MCD Application Team
-  * @version V2.4.2
-  * @date    13-November-2015
+  * @version V2.5.0
+  * @date    22-April-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
   ******************************************************************************  
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h
index b5e5392a3d..97dd4498ab 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version $VERSION$
-  * @date    $DATE$
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
@@ -129,7 +129,6 @@
 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
   * @{
   */
-  
 #define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
 #define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
 #define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
@@ -144,6 +143,62 @@
 #define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
 #define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
 #endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+ 
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
 /**
   * @}
   */
@@ -384,6 +439,7 @@
  #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
 #endif /* STM32F0 || STM32F3 || STM32F1 */
 
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
 /**
   * @}
   */
@@ -424,7 +480,7 @@
 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
 #define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
 #define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
 #define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
@@ -556,6 +612,9 @@
   * @{
   */
 #define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+#if defined(STM32F7) 
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
 /**
   * @}
   */
@@ -872,9 +931,12 @@
 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
 #define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
 #define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
 #define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
 #define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
 #define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
 #define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
 #define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
@@ -886,6 +948,49 @@
 /**
   * @}
   */
+  
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */  
+  
+#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888  
+#define CM_RGB565               DMA2D_INPUT_RGB565  
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8      
+#define CM_AL44                 DMA2D_INPUT_AL44    
+#define CM_AL88                 DMA2D_INPUT_AL88    
+#define CM_L4                   DMA2D_INPUT_L4      
+#define CM_A8                   DMA2D_INPUT_A8      
+#define CM_A4                   DMA2D_INPUT_A4      
+/**
+  * @}
+  */    
+#endif  /* STM32L4xx ||  STM32F7*/
 
 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
   * @{
@@ -943,7 +1048,10 @@
 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
 /**
@@ -1447,10 +1555,28 @@
 
 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
 
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
 /**
   * @}
   */
 
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -2494,7 +2620,7 @@
 #endif
 
 #if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
 #define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
 #endif
 
@@ -2611,6 +2737,31 @@
 
 #define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
 #define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+
 /**
   * @}
   */
@@ -2899,6 +3050,8 @@
 #define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
 #define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c
index 5bc08b5289..98fde7ec8a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -68,11 +68,11 @@
   * @{
   */
 /**
-  * @brief STM32F4xx HAL Driver version number V1.4.4
+  * @brief STM32F4xx HAL Driver version number V1.5.0
   */
 #define __STM32F4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2   (0x04) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
                                         |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@@ -263,7 +263,7 @@ __weak void HAL_MspDeInit(void)
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
   /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U);
+  HAL_SYSTICK_Config(SystemCoreClock/1000U);
 
   /*Configure the SysTick IRQ priority */
   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h
index 162e0dfbcb..7c3c84bf8d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c
index 7b2e047ac9..6a9e013d88 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
@@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
     
     /* Check if Multimode enabled */
     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@@ -789,7 +789,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
     
     /* Enable end of conversion interrupt for regular group */
     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
@@ -1087,7 +1087,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
 
     /* Enable ADC overrun interrupt */
     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
@@ -1228,6 +1228,12 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Error ADC callback.
+  * @note   In case of error due to overrun when using ADC with DMA transfer 
+  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h
index 081a1f031a..53e005a111 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file containing functions prototypes of ADC HAL library.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c
index 43ba31f2d4..4d1e47d026 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h
index 8f9c9b939f..e83cf1ef99 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_adc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of ADC HAL module.
   ******************************************************************************
   * @attention
@@ -231,15 +231,16 @@ typedef struct
   */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-    defined(STM32F410Rx)
+    defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+    defined(STM32F412Cx)
 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cxs */
 
 #if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
-#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */      
+#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
 /**
   * @}
   */ 
@@ -253,7 +254,20 @@ typedef struct
 /** @defgroup ADC_Exported_Macros ADC Exported Macros
   * @{
   */
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+  * @brief Disable internal path of ADC channel Vbat
+  * @Note  Use case of this macro:
+  *        On devices STM32F42x and STM32F43x, ADC internal channels
+  *        Vbat and VrefInt share the same internal path, only
+  *        one of them can be enabled.This macro is to be used when ADC 
+  *        channels Vbat and VrefInt are selected, and must be called 
+  *        before starting conversion of ADC channel VrefInt in order 
+  *        to disable ADC channel Vbat.
+  * @retval None
+  */
+#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 /**
   * @}
   */ 
@@ -307,9 +321,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   */
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-    defined(STM32F410Rx) || defined(STM32F411xE)
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c
index 625ed11e7c..da7c8dd105 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_can.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Controller Area Network (CAN) peripheral:
   *           + Initialization and de-initialization functions 
@@ -115,7 +115,8 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
   
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -1420,7 +1421,8 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #endif /* HAL_CAN_MODULE_ENABLED */
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h
index 6ac61e7621..99d2bf4533 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-  	defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  	defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)   || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
 
@@ -755,7 +756,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
   */
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c
index 4c84f81421..3323d0e14c 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   CEC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the High Definition Multimedia Interface 
@@ -95,9 +95,6 @@
 /** @defgroup CEC_Private_Constants CEC Private Constants
   * @{
   */
-#define CEC_CFGR_FIELDS     (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
-                           | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
-                           | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
 /**
   * @}
   */
@@ -108,13 +105,12 @@
 /** @defgroup CEC_Private_Functions CEC Private Functions
   * @{
   */
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
 /**
   * @}
   */
   
 /* Exported functions ---------------------------------------------------------*/
+
 /** @defgroup CEC_Exported_Functions CEC Exported Functions
   * @{
   */
@@ -150,11 +146,9 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
-  uint32_t tmpreg = 0x0U;
-  
+{  
   /* Check the CEC handle allocation */
-  if(hcec == NULL)
+  if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
   {
     return HAL_ERROR;
   }
@@ -168,41 +162,50 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); 
-  assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); 
   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
-  assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));  
+  assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));  
 
-  
-  if(hcec->State == HAL_CEC_STATE_RESET)
-  {   
+  if(hcec->gState == HAL_CEC_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hcec->Lock = HAL_UNLOCKED;
     /* Init the low level hardware : GPIO, CLOCK */
     HAL_CEC_MspInit(hcec);
   }
-  
-  hcec->State = HAL_CEC_STATE_BUSY;
+  hcec->gState = HAL_CEC_STATE_BUSY;
   
   /* Disable the Peripheral */
   __HAL_CEC_DISABLE(hcec);
   
-  tmpreg = hcec->Init.SignalFreeTime;
-  tmpreg |= hcec->Init.Tolerance;
-  tmpreg |= hcec->Init.BRERxStop;
-  tmpreg |= hcec->Init.BREErrorBitGen;
-  tmpreg |= hcec->Init.LBPEErrorBitGen;
-  tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
-  tmpreg |= hcec->Init.SignalFreeTimeOption;
-  tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
-  tmpreg |= hcec->Init.ListenMode;
-  
   /* Write to CEC Control Register */
-  MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
-
-  /* Enable the Peripheral */
+  hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
+                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
+			 hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+                         hcec->Init.ListenMode;
+  
+  /* Enable the following CEC Transmission/Reception interrupts as
+   * well as the following CEC Transmission/Reception Errors interrupts 
+   * Rx Byte Received IT 
+   * End of Reception IT 
+   * Rx overrun
+   * Rx bit rising error
+   * Rx short bit period error
+   * Rx long bit period error
+   * Rx missing acknowledge
+   * Tx Byte Request IT 
+   * End of Transmission IT
+   * Tx Missing Acknowledge IT
+   * Tx-Error IT
+   * Tx-Buffer Underrun IT 
+   * Tx arbitration lost   */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+    
+  /* Enable the CEC Peripheral */
   __HAL_CEC_ENABLE(hcec);
   
-  hcec->State = HAL_CEC_STATE_READY;
+  hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+  hcec->gState = HAL_CEC_STATE_READY;
+  hcec->RxState = HAL_CEC_STATE_READY;
   
   return HAL_OK;
 }
@@ -223,15 +226,36 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
   /* Check the parameters */
   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
 
-  hcec->State = HAL_CEC_STATE_BUSY;
+  hcec->gState = HAL_CEC_STATE_BUSY;
   
   /* DeInit the low level hardware */
   HAL_CEC_MspDeInit(hcec);
   /* Disable the Peripheral */
   __HAL_CEC_DISABLE(hcec);
   
+  /* Clear Flags */
+  __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+  
+  /* Disable the following CEC Transmission/Reception interrupts as
+   * well as the following CEC Transmission/Reception Errors interrupts 
+   * Rx Byte Received IT 
+   * End of Reception IT 
+   * Rx overrun
+   * Rx bit rising error
+   * Rx short bit period error
+   * Rx long bit period error
+   * Rx missing acknowledge
+   * Tx Byte Request IT 
+   * End of Transmission IT
+   * Tx Missing Acknowledge IT
+   * Tx-Error IT
+   * Tx-Buffer Underrun IT 
+   * Tx arbitration lost   */
+  __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+  
   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-  hcec->State = HAL_CEC_STATE_RESET;
+  hcec->gState = HAL_CEC_STATE_RESET;
+  hcec->RxState = HAL_CEC_STATE_RESET;
   
   /* Process Unlock */
   __HAL_UNLOCK(hcec);
@@ -239,6 +263,53 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
   return HAL_OK;
 }
 
+/**
+  * @brief Initializes the Own Address of the CEC device
+  * @param hcec: CEC handle
+  * @param  CEC_OwnAddress: The CEC own address.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+  if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+  { 
+    /* Process Locked */
+    __HAL_LOCK(hcec); 
+    
+    hcec->gState = HAL_CEC_STATE_BUSY;
+  
+    /* Disable the Peripheral */
+    __HAL_CEC_DISABLE(hcec);
+    
+    if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+    {
+      hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
+    }
+    else
+    {
+      hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
+    }
+        
+    hcec->gState = HAL_CEC_STATE_READY;
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcec); 
+    
+    /* Enable the Peripheral */
+    __HAL_CEC_ENABLE(hcec);
+    
+    return  HAL_OK; 
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
 /**
   * @brief CEC MSP Init
   * @param hcec: CEC handle
@@ -281,13 +352,9 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
     This subsection provides a set of functions allowing to manage the CEC data transfers.
     
     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
-        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+        logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
     
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (+) No-Blocking mode: The communication is performed using Interrupts. 
+    (#) The communication is performed using Interrupts. 
            These API's return the HAL status.
            The end of the data processing will be indicated through the 
            dedicated CEC IRQ when using Interrupt mode.
@@ -295,275 +362,20 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
            will be executed respectivelly at the end of the transmit or Receive process
            The HAL_CEC_ErrorCallback()user callback will be executed when a communication 
            error is detected
-
-    (#) Blocking mode API's are :
-        (+) HAL_CEC_Transmit()
-        (+) HAL_CEC_Receive() 
         
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_CEC_Transmit_IT()
-        (+) HAL_CEC_Receive_IT()
-        (+) HAL_CEC_IRQHandler()
+    (#) API's with Interrupt are :
+         (+) HAL_CEC_Transmit_IT()
+         (+) HAL_CEC_IRQHandler()
 
-    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
-        (+) HAL_CEC_TxCpltCallback()
-        (+) HAL_CEC_RxCpltCallback()
-        (+) HAL_CEC_ErrorCallback()
+    (#) A set of User Callbacks are provided:
+         (+) HAL_CEC_TxCpltCallback()
+         (+) HAL_CEC_RxCpltCallback()
+         (+) HAL_CEC_ErrorCallback()
       
 @endverbatim
   * @{
   */
 
-/**
-  * @brief Send data in blocking mode 
-  * @param hcec: CEC handle
-  * @param DestinationAddress: destination logical address      
-  * @param pData: pointer to input byte data buffer
-  * @param Size: amount of data to be sent in bytes (without counting the header).
-  *              0 means only the header is sent (ping operation).
-  *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
-  * @param  Timeout: Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
-{
- uint8_t  temp = 0U;
-  uint32_t tempisr = 0U;
-  uint32_t tickstart = 0U;
-
-  if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) 
-  {
-    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-    if((pData == NULL ) && (Size > 0U)) 
-    {
-      hcec->State = HAL_CEC_STATE_ERROR;
-      return  HAL_ERROR;
-    }
-
-    assert_param(IS_CEC_ADDRESS(DestinationAddress));
-    assert_param(IS_CEC_MSGSIZE(Size));
-
-    /* Process Locked */
-    __HAL_LOCK(hcec);
-    
-    hcec->State = HAL_CEC_STATE_BUSY_TX;
-
-    hcec->TxXferCount = Size;
-
-    /* case no data to be sent, sender is only pinging the system */
-    if (Size == 0U)
-    {
-      /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
-      __HAL_CEC_LAST_BYTE_TX_SET(hcec);
-    }
-
-    /* send header block */
-    temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
-    hcec->Instance->TXDR = temp;
-    /* Set TX Start of Message  (TXSOM) bit */
-    __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
-    while (hcec->TxXferCount > 0U)
-    {
-      hcec->TxXferCount--;
-
-      tickstart = HAL_GetTick();
-      while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
-      {
-        if(Timeout != HAL_MAX_DELAY)
-        {
-          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
-          {
-            hcec->State = HAL_CEC_STATE_TIMEOUT;
-            /* Process Unlocked */
-            __HAL_UNLOCK(hcec);
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* check whether error occured while waiting for TXBR to be set:
-         * has Tx underrun occurred ?
-         * has Tx error occurred ?
-         * has Tx Missing Acknowledge error occurred ? 
-         * has Arbitration Loss error occurred ? */
-        tempisr = hcec->Instance->ISR;
-        if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0U)
-        {
-          /* copy ISR for error handling purposes */
-          hcec->ErrorCode = tempisr;
-         /* clear all error flags by default */
-         __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
-         hcec->State = HAL_CEC_STATE_ERROR;
-         __HAL_UNLOCK(hcec);
-         return  HAL_ERROR;
-        }
-      }
-      /* TXBR to clear BEFORE writing TXDR register */
-      __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
-      if (hcec->TxXferCount == 0U)
-      {
-        /* if last byte transmission, set TX End of Message (TXEOM) bit */
-        __HAL_CEC_LAST_BYTE_TX_SET(hcec);
-      }
-      hcec->Instance->TXDR = *pData++;
-
-      /* error check after TX byte write up */
-      tempisr = hcec->Instance->ISR;
-      if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0U)
-      {
-        /* copy ISR for error handling purposes */
-        hcec->ErrorCode = tempisr;
-        /* clear all error flags by default */
-        __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
-        hcec->State = HAL_CEC_STATE_ERROR;
-        __HAL_UNLOCK(hcec);
-        return  HAL_ERROR;
-      }
-    } /* end while (while (hcec->TxXferCount > 0)) */
-
-    /* if no error up to this point, check that transmission is  
-     * complete, that is wait until TXEOM is reset */
-    tickstart = HAL_GetTick();
-
-    while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((HAL_GetTick() - tickstart) > Timeout)
-        {
-          hcec->State = HAL_CEC_STATE_ERROR;
-          __HAL_UNLOCK(hcec);             
-          return HAL_TIMEOUT;
-        }
-      } 
-    }
-
-    /* Final error check once all bytes have been transmitted */
-    tempisr = hcec->Instance->ISR;
-    if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0U)
-    {
-      /* copy ISR for error handling purposes */
-      hcec->ErrorCode = tempisr;
-      /* clear all error flags by default */
-      __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
-      hcec->State = HAL_CEC_STATE_ERROR;
-      __HAL_UNLOCK(hcec);
-      return  HAL_ERROR;
-    }
-
-    hcec->State = HAL_CEC_STATE_READY;
-    __HAL_UNLOCK(hcec);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. 
-  * @param hcec: CEC handle
-  * @param pData: pointer to received data buffer.
-  * @param Timeout: Timeout duration.
-  *       Note that the received data size is not known beforehand, the latter is known
-  *       when the reception is complete and is stored in hcec->RxXferSize.  
-  *       hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
-  *       If only a header is received, hcec->RxXferSize = 0    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
-{
-  uint32_t temp;
-  uint32_t tickstart = 0U;
-
-  if (hcec->State == HAL_CEC_STATE_READY)
-  { 
-    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-    if (pData == NULL ) 
-    {
-      hcec->State = HAL_CEC_STATE_ERROR;
-      return  HAL_ERROR;
-    }
-
-    hcec->RxXferSize = 0U;
-    /* Process Locked */
-    __HAL_LOCK(hcec);
-
-    /* Rx loop until CEC_ISR_RXEND  is set */
-    while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
-    {
-      tickstart = HAL_GetTick();
-      /* Wait for next byte to be received */
-      while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
-      {
-        if(Timeout != HAL_MAX_DELAY)
-        {
-          if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
-          {
-            hcec->State = HAL_CEC_STATE_TIMEOUT;
-            __HAL_UNLOCK(hcec);
-            return HAL_TIMEOUT;
-          }
-        }
-        /* any error so far ? 
-         * has Rx Missing Acknowledge occurred ?
-         * has Rx Long Bit Period error occurred ?
-         * has Rx Short Bit Period error occurred ? 
-         * has Rx Bit Rising error occurred ?
-         * has Rx Overrun error occurred ? */
-        temp = (uint32_t) (hcec->Instance->ISR);
-        if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0U)
-        {
-          /* copy ISR for error handling purposes */
-          hcec->ErrorCode = temp;
-          /* clear all error flags by default */
-          __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
-          hcec->State = HAL_CEC_STATE_ERROR;
-          __HAL_UNLOCK(hcec);
-          return  HAL_ERROR;
-        }
-      } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
-
-      /* read received data */
-      *pData++ = hcec->Instance->RXDR;
-      temp = (uint32_t) (hcec->Instance->ISR);
-      /* end of message ? */
-      if ((temp &  CEC_ISR_RXEND) != 0U)
-      {
-         assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
-         __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
-          hcec->State = HAL_CEC_STATE_READY;
-         __HAL_UNLOCK(hcec);
-         return HAL_OK; 
-      }
-
-      /* clear Rx-Byte Received flag */
-      __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
-      /* increment payload byte counter */
-       hcec->RxXferSize++;
-    } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ 
-
-    /* if the instructions below are executed, it means RXEND was set when RXBR was 
-     * set for the first time:
-     * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
-     * loop has not been executed and this means a single byte has been sent */
-    *pData++ = hcec->Instance->RXDR;
-     /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
-     hcec->RxXferSize = 0U;
-     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
-
-    hcec->State = HAL_CEC_STATE_READY;
-    __HAL_UNLOCK(hcec);
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
 /**
   * @brief Send data in interrupt mode 
   * @param hcec: CEC handle 
@@ -574,121 +386,48 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3
   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
   * @retval HAL status
   */  
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
 {
-  uint8_t  temp = 0U; 
   /* if the IP isn't already busy and if there is no previous transmission
      already pending due to arbitration lost */
-  if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) 
-  &&   (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) 
-  {
-    if((pData == NULL) && (Size > 0U)) 
+  if (hcec->gState == HAL_CEC_STATE_READY) 
+  {    
+    if((pData == NULL ) && (Size > 0U)) 
     {
-      hcec->State = HAL_CEC_STATE_ERROR;
-      return  HAL_ERROR;
+      return  HAL_ERROR;                                    
     }
 
     assert_param(IS_CEC_ADDRESS(DestinationAddress)); 
+    assert_param(IS_CEC_ADDRESS(InitiatorAddress)); 
     assert_param(IS_CEC_MSGSIZE(Size));
 
     /* Process Locked */
     __HAL_LOCK(hcec);
     hcec->pTxBuffPtr = pData;
-    hcec->State = HAL_CEC_STATE_BUSY_TX;
+    hcec->gState = HAL_CEC_STATE_BUSY_TX;
     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
-    /* Disable Peripheral to write CEC_IER register */
-    __HAL_CEC_DISABLE(hcec);
-
-    /* Enable the following two CEC Transmission interrupts as
-     * well as the following CEC Transmission Errors interrupts: 
-     * Tx Byte Request IT 
-     * End of Transmission IT
-     * Tx Missing Acknowledge IT
-     * Tx-Error IT
-     * Tx-Buffer Underrun IT 
-     * Tx arbitration lost     */
-    __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
-    /* Enable the Peripheral */
-    __HAL_CEC_ENABLE(hcec);
-
+  
     /* initialize the number of bytes to send,
      * 0 means only one header is sent (ping operation) */
     hcec->TxXferCount = Size;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcec); 
-
+    
     /* in case of no payload (Size = 0), sender is only pinging the system;
-     * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+       Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
     if (Size == 0U)
     {
       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
     }
 
     /* send header block */
-    temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
-    hcec->Instance->TXDR = temp;
+    hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
     /* Set TX Start of Message  (TXSOM) bit */
     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
+	    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcec); 
+  
     return HAL_OK;
-  }
-    /* if the IP is already busy or if there is a previous transmission
-     already pending due to arbitration loss */
-  else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
-  {
-    __HAL_LOCK(hcec);
-    /* set state to BUSY TX, in case it wasn't set already (case
-     * of transmission new attempt after arbitration loss) */
-    if (hcec->State != HAL_CEC_STATE_BUSY_TX)
-    {
-      hcec->State = HAL_CEC_STATE_BUSY_TX;
-    }
 
-    /* if all data have been sent */
-    if(hcec->TxXferCount == 0U)
-    {
-      /* Disable Peripheral to write CEC_IER register */
-      __HAL_CEC_DISABLE(hcec);
-
-      /* Disable the CEC Transmission Interrupts */
-      __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
-      /* Disable the CEC Transmission Error Interrupts */
-      __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
-
-      /* Enable the Peripheral */
-      __HAL_CEC_ENABLE(hcec);
-
-      __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
-
-      hcec->State = HAL_CEC_STATE_READY;
-      /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
-      start again the Transmission under the Tx call back API */
-      __HAL_UNLOCK(hcec);
-      
-      HAL_CEC_TxCpltCallback(hcec);
-      
-      return HAL_OK;
-    }
-    else
-    {
-      if (hcec->TxXferCount == 1U)
-      {
-        /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
-        __HAL_CEC_LAST_BYTE_TX_SET(hcec);
-      }
-      /* clear Tx-Byte request flag */
-       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); 
-       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
-      hcec->TxXferCount--;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcec);
-
-      return HAL_OK;
-    }
   }
   else
   {
@@ -696,73 +435,27 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati
   }
 }
 
-/**
-  * @brief Receive data in interrupt mode. 
-  * @param hcec: CEC handle
-  * @param pData: pointer to received data buffer.
-  * Note that the received data size is not known beforehand, the latter is known
-  * when the reception is complete and is stored in hcec->RxXferSize.  
-  * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
-  * If only a header is received, hcec->RxXferSize = 0    
-  * @retval HAL status
-  */  
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
-{  
-  if(hcec->State == HAL_CEC_STATE_READY)
-  {
-    if(pData == NULL) 
-    {
-      hcec->State = HAL_CEC_STATE_ERROR;
-      return HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hcec);
-    hcec->RxXferSize = 0U;
-    hcec->pRxBuffPtr = pData;
-    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-    /* the IP is moving to a ready to receive state */
-    hcec->State = HAL_CEC_STATE_STANDBY_RX;
-
-    /* Disable Peripheral to write CEC_IER register */
-    __HAL_CEC_DISABLE(hcec);
-    
-    /* Enable the following CEC Reception Error Interrupts: 
-     * Rx overrun
-     * Rx bit rising error
-     * Rx short bit period error
-     * Rx long bit period error
-     * Rx missing acknowledge  */
-    __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcec);
-    
-    /* Enable the following two CEC Reception interrupts: 
-     * Rx Byte Received IT 
-     * End of Reception IT */
-    __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
-    
-    __HAL_CEC_ENABLE(hcec);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
 /**
   * @brief Get size of the received frame.
   * @param hcec: CEC handle
   * @retval Frame size
   */
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
 {
   return hcec->RxXferSize;
 }
-    
+
+/**
+  * @brief Change Rx Buffer.
+  * @param hcec: CEC handle
+  * @note  This function can be called only inside the HAL_CEC_RxCpltCallback() 
+  * @retval Frame size
+  */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+{
+  hcec->Init.RxBuffer = Rxbuffer; 
+}
+  
 /**
   * @brief This function handles CEC interrupt requests.
   * @param hcec: CEC handle
@@ -770,103 +463,102 @@ uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
   */
 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 {
+  
   /* save interrupts register for further error or interrupts handling purposes */
-  hcec->ErrorCode = hcec->Instance->ISR;
-  /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }
+  uint32_t reg = 0U;
+  reg = hcec->Instance->ISR;
+
   
-  /* CEC transmit error interrupt occured --------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }
-  
-  /* CEC TX underrun error interrupt occured --------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }
-  
-  /* CEC TX arbitration error interrupt occured --------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
+  /* ----------------------------Arbitration Lost Management----------------------------------*/     
+  /* CEC TX arbitration error interrupt occurred --------------------------------------*/
+  if((reg & CEC_FLAG_ARBLST) != RESET) 
   { 
+    hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
-    hcec->State = HAL_CEC_STATE_ERROR;
   }
   
-  /* CEC RX overrun error interrupt occured --------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
+  /* ----------------------------Rx Management----------------------------------*/ 
+  /* CEC RX byte received interrupt  ---------------------------------------------------*/
+  if((reg & CEC_FLAG_RXBR) != RESET) 
   { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
-    hcec->State = HAL_CEC_STATE_ERROR;
+    /* reception is starting */ 
+    hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+    hcec->RxXferSize++;
+    /* read received byte */
+    *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);  
+  }
+  
+  /* CEC RX end received interrupt  ---------------------------------------------------*/
+  if((reg & CEC_FLAG_RXEND) != RESET) 
+  { 
+    /* clear IT */
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+    
+    /* Rx process is completed, restore hcec->RxState to Ready */
+    hcec->RxState = HAL_CEC_STATE_READY; 
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+    hcec->Init.RxBuffer -= hcec->RxXferSize;
+    HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); 
+    hcec->RxXferSize = 0U; 
+  }
+  
+  /* ----------------------------Tx Management----------------------------------*/  
+  /* CEC TX byte request interrupt ------------------------------------------------*/
+  if((reg & CEC_FLAG_TXBR) != RESET) 
+  {
+    if (hcec->TxXferCount == 0U)
+    {
+      /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+      __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+    }
+    else
+    {	
+      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+      hcec->TxXferCount--;
+    }  
+    /* clear Tx-Byte request flag */
+    __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); 
   } 
   
-  /* CEC RX bit rising error interrupt occured -------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }
+  /* CEC TX end interrupt ------------------------------------------------*/
+  if((reg & CEC_FLAG_TXEND) != RESET) 
+  {	
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
+    
+    /* Tx process is ended, restore hcec->gState to Ready */     
+    hcec->gState = HAL_CEC_STATE_READY;
+    /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+    start again the Transmission under the Tx call back API */
+    __HAL_UNLOCK(hcec);
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+    HAL_CEC_TxCpltCallback(hcec);
+  } 
   
-  /* CEC RX short bit period error interrupt occured -------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }   
-  
-  /* CEC RX long bit period error interrupt occured --------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }   
-  
-  /* CEC RX missing acknowledge error interrupt occured ----------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
-  { 
-    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
-    hcec->State = HAL_CEC_STATE_ERROR;
-  }   
-
-  if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0U)
+  /* ----------------------------Rx/Tx Error Management----------------------------------*/   
+  if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
   {
+    hcec->ErrorCode = reg;
+    __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+
+    
+    if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+    {
+      hcec->Init.RxBuffer-=hcec->RxXferSize;	
+      hcec->RxXferSize = 0U; 
+      hcec->RxState = HAL_CEC_STATE_READY;
+    }
+    else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
+    {	
+      /* Set the CEC state ready to be able to start again the process */
+      hcec->gState = HAL_CEC_STATE_READY;
+    }	
+    
+    /* Error  Call Back */    
     HAL_CEC_ErrorCallback(hcec);
   }
-
-  /* CEC RX byte received interrupt  -----------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
-  { 
-    /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
-    CEC_Receive_IT(hcec);
-  }
-
-  /* CEC RX end received interrupt  ------------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
-  { 
-    /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
-    CEC_Receive_IT(hcec);
-  }
-
-  /* CEC TX byte request interrupt -------------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
-  {
-    /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
-    CEC_Transmit_IT(hcec);
-  } 
-
-  /* CEC TX end interrupt ----------------------------------------------------*/
-  if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
-  {
-   /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
-    CEC_Transmit_IT(hcec);
-  }
+  
 }
 
 /**
@@ -877,7 +569,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
 {
   /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcec);
+  UNUSED(hcec);  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_CEC_TxCpltCallback can be implemented in the user file
    */ 
@@ -886,14 +578,16 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 /**
   * @brief Rx Transfer completed callback
   * @param hcec: CEC handle
+  * @param RxFrameSize: Size of frame
   * @retval None
   */
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hcec);
+  UNUSED(RxFrameSize);
   /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CEC_TxCpltCallback can be implemented in the user file
+            the HAL_CEC_RxCpltCallback can be implemented in the user file
    */
 }
 
@@ -920,29 +614,35 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
 @verbatim   
  ===============================================================================
                       ##### Peripheral Control function #####
- ===============================================================================
+ ===============================================================================  
     [..]
     This subsection provides a set of functions allowing to control the CEC.
      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. 
+	 (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. 
 @endverbatim
   * @{
   */
 /**
   * @brief return the CEC state
-  * @param hcec: CEC handle
+  * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+  *              the configuration information for the specified CEC module.
   * @retval HAL state
   */
 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
 {
-  return hcec->State;
+  uint32_t temp1 = 0x00U, temp2 = 0x00U;
+  temp1 = hcec->gState;
+  temp2 = hcec->RxState;
+  
+  return (HAL_CEC_StateTypeDef)(temp1 | temp2);
 }
 
 /**
-* @brief  Return the CEC error code
-* @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
+  * @brief  Return the CEC error code
+  * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
   *              the configuration information for the specified CEC.
-* @retval CEC Error Code
-*/
+  * @retval CEC Error Code
+  */
 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
 {
   return hcec->ErrorCode;
@@ -951,154 +651,7 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
 /**
   * @}
   */
-  
-/**
-  * @brief Send data in interrupt mode 
-  * @param hcec: CEC handle. 
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_CEC_Transmit_IT()   
-  * @retval HAL status
-  */  
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
-{
-  /* if the IP is already busy or if there is a previous transmission
-     already pending due to arbitration loss */
-  if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
-        || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
-  {
-    __HAL_LOCK(hcec);
-    /* set state to BUSY TX, in case it wasn't set already (case
-     * of transmission new attempt after arbitration loss) */
-    if (hcec->State != HAL_CEC_STATE_BUSY_TX)
-    {
-      hcec->State = HAL_CEC_STATE_BUSY_TX;
-    }
 
-    /* if all data have been sent */
-    if(hcec->TxXferCount == 0U)
-    {
-      /* Disable Peripheral to write CEC_IER register */
-      __HAL_CEC_DISABLE(hcec);
-      
-      /* Disable the CEC Transmission Interrupts */
-      __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
-      /* Disable the CEC Transmission Error Interrupts */
-      __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
-
-      /* Enable the Peripheral */
-      __HAL_CEC_ENABLE(hcec);
-
-       __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
-
-      hcec->State = HAL_CEC_STATE_READY;
-      /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
-      start again the Transmission under the Tx call back API */
-      __HAL_UNLOCK(hcec);
-      
-      HAL_CEC_TxCpltCallback(hcec);
-      
-      return HAL_OK;
-    }
-    else
-    {
-      if (hcec->TxXferCount == 1U)
-      {
-        /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
-        __HAL_CEC_LAST_BYTE_TX_SET(hcec);
-      }
-      /* clear Tx-Byte request flag */
-       __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); 
-       hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
-      hcec->TxXferCount--;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcec);
-  
-      return HAL_OK;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;   
-  }
-}
-
-
-/**
-  * @brief Receive data in interrupt mode. 
-  * @param hcec: CEC handle.
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_CEC_Receive_IT()   
-  * @retval HAL status
-  */  
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
-{
-  uint32_t tempisr;
-  
-  /* Three different conditions are tested to carry out the RX IT processing:
-   * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and 
-   *   the reception of the first byte is starting
-   * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
-   *   and a new byte is being received
-   * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
-   *   but has been interrupted by a new message reception or discarded due to 
-   *   arbitration loss: the reception of the first or higher priority message 
-   *   (the arbitration winner) is starting */
-  if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) 
-  ||  (hcec->State == HAL_CEC_STATE_BUSY_RX)
-  ||  (hcec->State == HAL_CEC_STATE_BUSY_TX)) 
-  {
-    /* reception is starting */ 
-    hcec->State = HAL_CEC_STATE_BUSY_RX;
-    tempisr =  (uint32_t) (hcec->Instance->ISR);
-    if ((tempisr & CEC_FLAG_RXBR) != 0U)
-    {
-      /* Process Locked */
-      __HAL_LOCK(hcec);
-      /* read received byte */
-      *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
-      /* if last byte has been received */      
-      if ((tempisr & CEC_FLAG_RXEND) != 0U)
-      {
-        /* clear IT */
-        __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
-        /* RX interrupts are not disabled at this point.
-         * Indeed, to disable the IT, the IP must be disabled first
-         * which resets the TXSOM flag. In case of arbitration loss,
-         * this leads to a transmission abort.
-         * Therefore, RX interruptions disabling if so required,
-         * is done in HAL_CEC_RxCpltCallback */
- 
-        /* IP state is moved to READY.
-         * If the IP must remain in standby mode to listen
-         * any new message, it is up to HAL_CEC_RxCpltCallback
-         * to move it again to HAL_CEC_STATE_STANDBY_RX */  
-        hcec->State = HAL_CEC_STATE_READY; 
-        
-        /* Call the Process Unlocked before calling the Rx call back API */
-        __HAL_UNLOCK(hcec);
-        HAL_CEC_RxCpltCallback(hcec);
-        
-        return HAL_OK;
-      } 
-      __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);  
-
-      hcec->RxXferSize++;
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcec);
-      
-      return HAL_OK;
-    }
-    else
-    {
-      return HAL_BUSY; 
-    }
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h
index 02c3e914d2..6b8f0ee8de 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
@@ -108,8 +108,6 @@ typedef struct
   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
-
-  uint32_t OwnAddress;                   /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
   
   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
   
@@ -121,23 +119,66 @@ typedef struct
                                                 address (OAR) with positive acknowledge. Messages addressed to different destination 
                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
 
-  uint8_t  InitiatorAddress;             /* Initiator address (source logical address, sent in each header) */
+  uint16_t  OwnAddress;                 /*!< Own addresses configuration
+                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */
+  
+  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */
+  
 
 }CEC_InitTypeDef;
 
 /** 
-  * @brief HAL CEC State structures definition  
+  * @brief HAL CEC State structures definition 
+  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains CEC state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7 (not used)
+  *             x  : Should be set to 0
+  *          b6  Error information 
+  *             0  : No Error
+  *             1  : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized. HAL CEC Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.  
   */ 
 typedef enum
 {
-  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral Reset state                              */
-  HAL_CEC_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use            */
-  HAL_CEC_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                      */
-  HAL_CEC_STATE_BUSY_TX           = 0x03U,    /*!< Data Transmission process is ongoing                */
-  HAL_CEC_STATE_BUSY_RX           = 0x04U,    /*!< Data Reception process is ongoing                   */
-  HAL_CEC_STATE_STANDBY_RX        = 0x05U,    /*!< IP ready to receive, doesn't prevent IP to transmit */
-  HAL_CEC_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                                       */
-  HAL_CEC_STATE_ERROR             = 0x07U     /*!< State Error                                         */
+  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized 
+                                                   Value is allowed for gState and RxState             */
+  HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState             */
+  HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only                    */
+  HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only                   */
+  HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing 
+                                                   Value is allowed for gState only                    */
+  HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
 }HAL_CEC_StateTypeDef;
 
 /** 
@@ -145,25 +186,27 @@ typedef enum
   */  
 typedef struct
 {
-  CEC_TypeDef             *Instance;      /* CEC registers base address */
+  CEC_TypeDef             *Instance;      /*!< CEC registers base address */
   
-  CEC_InitTypeDef         Init;           /* CEC communication parameters */
+  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
   
-  uint8_t                 *pTxBuffPtr;    /* Pointer to CEC Tx transfer Buffer */
+  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
   
-  uint16_t                TxXferCount;    /* CEC Tx Transfer Counter */
+  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
   
-  uint8_t                 *pRxBuffPtr;    /* Pointer to CEC Rx transfer Buffer */
+  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
   
-  uint16_t                RxXferSize;     /* CEC Rx Transfer size, 0: header received only */
+  HAL_LockTypeDef         Lock;           /*!< Locking object */
+
+  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management 
+                                               and also related to Tx operations.
+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
   
-  uint32_t                ErrorCode;      /* For errors handling purposes, copy of ISR register 
-                                            in case error is reported */
+  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
   
-  HAL_LockTypeDef         Lock;           /* Locking object */
-  
-  HAL_CEC_StateTypeDef    State;          /* CEC communication state */
-    
+  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register 
+                                               in case error is reported */    
 }CEC_HandleTypeDef;
 /**
   * @}
@@ -177,16 +220,16 @@ typedef struct
 /** @defgroup CEC_Error_Code CEC Error Code
   * @{
   */ 
-#define HAL_CEC_ERROR_NONE    ((uint32_t)0x00000000)  /*!< no error                      */
-#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR           /*!< CEC Rx-Overrun                */
-#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE             /*!< CEC Rx Bit Rising Error       */
-#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE            /*!< CEC Rx Short Bit period Error */
-#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE            /*!< CEC Rx Long Bit period Error  */
-#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE          /*!< CEC Rx Missing Acknowledge    */
-#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST          /*!< CEC Arbitration Lost          */
-#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR           /*!< CEC Tx-Buffer Underrun        */
-#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR           /*!< CEC Tx-Error                  */
-#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE          /*!< CEC Tx Missing Acknowledge    */
+#define HAL_CEC_ERROR_NONE    ((uint32_t)0x00000000U)/*!< no error                      */
+#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */
+#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */
+#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */
+#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */
+#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */
+#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */
+#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */
+#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */
 /**
   * @}
   */
@@ -284,7 +327,30 @@ typedef struct
 /**
   * @}
   */
-  
+
+/** @defgroup CEC_OWN_ADDRESS   CEC Own Address    
+  * @{
+  */
+#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */
+#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */
+/**
+  * @}
+  */
+    
 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
   * @{
   */
@@ -359,15 +425,18 @@ typedef struct
   * @{
   */
 
-/** @brief  Reset CEC handle state
+/** @brief  Reset CEC handle gstate & RxState
   * @param  __HANDLE__: CEC handle.
   * @retval None
   */
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
+                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
+                                                     } while(0)
 
 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
   * @param  __HANDLE__: specifies the CEC Handle.
-  * @param  __FLAG__: specifies the interrupt to check.
+  * @param  __FLAG__: specifies the flag to check.
   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
   *            @arg CEC_FLAG_TXERR: Tx Error.
   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -377,7 +446,7 @@ typedef struct
   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
   *            @arg CEC_FLAG_LBPE: Rx Long period Error
   *            @arg CEC_FLAG_SBPE: Rx Short period Error
-  *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
   *            @arg CEC_FLAG_RXEND: End Of Reception.
   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.      
@@ -398,7 +467,7 @@ typedef struct
   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
   *            @arg CEC_FLAG_LBPE: Rx Long period Error
   *            @arg CEC_FLAG_SBPE: Rx Short period Error
-  *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
   *            @arg CEC_FLAG_RXEND: End Of Reception.
   *            @arg CEC_FLAG_RXBR: Rx-Byte Received. 
@@ -422,7 +491,7 @@ typedef struct
   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 
   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable 
   *            @arg CEC_IT_RXEND: End Of Reception IT Enable 
-  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                          
   * @retval none
   */
 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  
@@ -443,7 +512,7 @@ typedef struct
   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 
   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable 
   *            @arg CEC_IT_RXEND: End Of Reception IT Enable 
-  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                   
   * @retval none
   */   
 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  
@@ -518,7 +587,7 @@ typedef struct
   * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)                   
   * @retval none 
   */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__) << CEC_CFGR_OAR_LSB_POS)
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
 
 /**
   * @}
@@ -535,6 +604,7 @@ typedef struct
 /* Initialization and de-initialization functions  ****************************/
 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
 /**
@@ -545,14 +615,12 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
   * @{
   */
 /* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
 /**
   * @}
@@ -627,20 +695,6 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
 
-/** @brief Check CEC device Own Address Register (OAR) setting.
-  *        OAR address is written in a 15-bit field within CEC_CFGR register. 
-  * @param  __ADDRESS__: CEC own address.               
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFFU)  
-
-/** @brief Check CEC initiator or destination logical address setting.
-  *        Initiator and destination addresses are coded over 4 bits. 
-  * @param  __ADDRESS__: CEC initiator or logical address.               
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)    
-
 /** @brief Check CEC message size.
   *       The message size is the payload size: without counting the header, 
   *       it varies from 0 byte (ping operation, one header only, no payload) to 
@@ -648,12 +702,24 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
   * @param  __SIZE__: CEC message size.               
   * @retval Test result (TRUE or FALSE).
   */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xFU)  
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)  
+                                                 
+/** @brief Check CEC device Own Address Register (OAR) setting.
+  *        OAR address is written in a 15-bit field within CEC_CFGR register. 
+  * @param  __ADDRESS__: CEC own address.               
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
 
+/** @brief Check CEC initiator or destination logical address setting.
+  *        Initiator and destination addresses are coded over 4 bits. 
+  * @param  __ADDRESS__: CEC initiator or logical address.               
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) 
 /**
   * @}
-  */ 
-
+  */
 /* Private functions ---------------------------------------------------------*/
 /** @defgroup CEC_Private_Functions CEC Private Functions
   * @{
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_conf_template.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_conf_template.h
index 519f46fbd5..75cb1f1e3a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_conf_template.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_conf_template.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f4xx_hal_conf.h.
@@ -95,6 +95,7 @@
 #define HAL_HCD_MODULE_ENABLED
 #define HAL_FMPI2C_MODULE_ENABLED
 #define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
 #define HAL_LPTIM_MODULE_ENABLED
 
 /* ########################## HSE/HSI Values adaptation ##################### */
@@ -417,6 +418,10 @@
  #include "stm32f4xx_hal_spdifrx.h"
 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
 
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
 #ifdef HAL_LPTIM_MODULE_ENABLED
  #include "stm32f4xx_hal_lptim.h"
 #endif /* HAL_LPTIM_MODULE_ENABLED */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c
index f3526347ef..cd61b03047 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h
index 9df27c338b..d05077784b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c
index 3251a21c7f..bad69591bc 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h
index 824a564004..aa2f125283 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c
index f9002f7dfc..3cb329c731 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cryp.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   CRYP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cryptography (CRYP) peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h
index 8499224605..069630921f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c
index 10e23e8ca0..90ac1518a3 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cryp_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Extended CRYP HAL module driver
   *          This file provides firmware functions to manage the following 
   *          functionalities of CRYP extension peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h
index 403af80486..bd52084844 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_cryp_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of CRYP HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c
index 566b7dc260..2a0c6bc5b2 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h
index e380bb0c0a..bd1e990c3d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c
index b65e6d135e..852bf31328 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of DAC extension peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h
index 5ef2a8f018..594d6f2c9f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c
index 6eb5ed6f7d..759df2bd75 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c
@@ -2,17 +2,17 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dcmi.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DCMI HAL module driver
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State and Error functions  
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
   *           
-  @verbatim      
+  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
@@ -32,11 +32,11 @@
         register to the destination memory buffer.
 
     (#) Program the required configuration through following parameters:
-        DCMI mode, destination memory Buffer address and the data length 
+        DCMI mode, destination memory Buffer address and the data length
         and enable capture using HAL_DCMI_Start_DMA() function.
 
     (#) Optionally, configure and Enable the CROP feature to select a rectangular
-        window from the received image using HAL_DCMI_ConfigCrop() 
+        window from the received image using HAL_DCMI_ConfigCrop()
         and HAL_DCMI_EnableCROP() functions
 
     (#) The capture can be stopped using HAL_DCMI_Stop() function.
@@ -44,7 +44,7 @@
     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
 
      *** DCMI HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DCMI HAL driver.
        
@@ -55,8 +55,8 @@
       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
- 
-     [..] 
+
+     [..]
        (@) You can refer to the DCMI HAL driver header file for more useful macros
       
   @endverbatim
@@ -88,7 +88,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -108,7 +108,7 @@
     defined(STM32F479xx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000U)  /* 1s  */
+#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)14U)  /* Set timeout to 1s  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -124,10 +124,10 @@ static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
   *  @brief   Initialization and Configuration functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                 ##### Initialization and Configuration functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Initialize and configure the DCMI
       (+) De-initialize the DCMI 
@@ -135,7 +135,7 @@ static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the DCMI according to the specified
   *         parameters in the DCMI_InitTypeDef and create the associated handle.
@@ -144,13 +144,13 @@ static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
-{     
+{
   /* Check the DCMI peripheral state */
   if(hdcmi == NULL)
   {
      return HAL_ERROR;
   }
-  
+
   /* Check function parameters */
   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
@@ -167,10 +167,12 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
     hdcmi->Lock = HAL_UNLOCKED;
     /* Init the low level hardware */
     HAL_DCMI_MspInit(hdcmi);
-  } 
-  
+  }
+
   /* Change the DCMI state */
-  hdcmi->State = HAL_DCMI_STATE_BUSY; 
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Set DCMI parameters */
   /* Configures the HS, VS, DE and PC polarity */
   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |
                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |
@@ -182,19 +184,18 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
 
   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
   {
-    DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8U)|
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16U) |
-                  ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24U));
-
+    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |
+                             ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
   }
 
-  /* Enable DCMI by setting DCMIEN bit */
-  __HAL_DCMI_ENABLE(hdcmi);
+  /* Enable the Line, Vsync, Error and Overrun interrupts */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
 
   /* Update error code */
   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-  
+
   /* Initialize the DCMI state*/
   hdcmi->State  = HAL_DCMI_STATE_READY;
 
@@ -259,15 +260,15 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
 /**
   * @}
   */
-/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions 
-  *  @brief   IO operation functions  
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure destination address and data length and 
+      (+) Configure destination address and data length and
           Enables DCMI DMA request and enables DCMI capture
       (+) Stop the DCMI capture.
       (+) Handles DCMI interrupt request.
@@ -277,7 +278,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
   */
 
 /**
-  * @brief  Enables DCMI DMA request and enables DCMI capture  
+  * @brief  Enables DCMI DMA request and enables DCMI capture
   * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
   *                    the configuration information for DCMI.
   * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
@@ -286,7 +287,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
-{  
+{
   /* Initialize the second memory address */
   uint32_t SecondMemAddress = 0U;
 
@@ -296,17 +297,11 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
   /* Process Locked */
   __HAL_LOCK(hdcmi);
 
-  /* Enable the Line, Vsync, Error and Overrun interrupts */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVF);
-  
-  /* Disable the End of Frame interrupt */
-  __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
-  
   /* Lock the DCMI peripheral state */
   hdcmi->State = HAL_DCMI_STATE_BUSY;
-
-  /* Check the parameters */
-  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+  
+  /* Enable DCMI by setting DCMIEN bit */
+  __HAL_DCMI_ENABLE(hdcmi);
 
   /* Configure the DCMI Mode */
   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
@@ -318,6 +313,13 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
   /* Set the DMA error callback */
   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
 
+  /* Set the dma abort callback */
+  hdcmi->DMA_Handle->XferAbortCallback = NULL;
+  
+  /* Reset transfer counters value */ 
+  hdcmi->XferCount = 0;
+  hdcmi->XferTransferNumber = 0;
+
   if(Length <= 0xFFFFU)
   {
     /* Enable the DMA Stream */
@@ -326,13 +328,13 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
   else /* DCMI_DOUBLE_BUFFER Mode */
   {
     /* Set the DMA memory1 conversion complete callback */
-    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; 
+    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
 
     /* Initialize transfer parameters */
     hdcmi->XferCount = 1U;
     hdcmi->XferSize = Length;
     hdcmi->pBuffPtr = pData;
-      
+
     /* Get the number of buffer */
     while(hdcmi->XferSize > 0xFFFFU)
     {
@@ -352,50 +354,50 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
   }
 
   /* Enable Capture */
-  DCMI->CR |= DCMI_CR_CAPTURE;
+  hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
 
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Disable DCMI DMA request and Disable DCMI capture  
+  * @brief  Disable DCMI DMA request and Disable DCMI capture
   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
-  *                the configuration information for DCMI. 
-  * @retval HAL status     
+  *                the configuration information for DCMI.
+  * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
 {
-  uint32_t tickstart = 0U;
+  __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
+  HAL_StatusTypeDef status = HAL_OK;
 
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+  
   /* Lock the DCMI peripheral state */
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
-  __HAL_DCMI_DISABLE(hdcmi);
-
   /* Disable Capture */
-  DCMI->CR &= ~(DCMI_CR_CAPTURE);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
+  hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
 
   /* Check if the DCMI capture effectively disabled */
-  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U)
+  do
   {
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
+    if (count-- == 0)
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-      
       /* Update error code */
       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-      
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
+
+      status = HAL_TIMEOUT;
     }
   }
+  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
+
+  /* Disable the DCMI */
+  __HAL_DCMI_DISABLE(hdcmi);
 
   /* Disable the DMA */
   HAL_DMA_Abort(hdcmi->DMA_Handle);
@@ -409,6 +411,72 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
+  /* Return function status */
+  return status;
+}
+
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
+{
+  __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if(hdcmi->State == HAL_DCMI_STATE_BUSY)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+    /* Disable Capture */
+    hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+    /* Check if the DCMI capture effectively disabled */
+    do
+    {
+      if (count-- == 0)
+      {        
+        /* Update error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+        
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+        
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+    while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
+  }    
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+  
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Resume DCMI capture  
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI. 
+  * @retval HAL status     
+  */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+  
+  if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_BUSY;
+    
+    /* Disable Capture */
+    hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+  } 
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+  
   /* Return function status */
   return HAL_OK;
 }
@@ -420,112 +488,83 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
   * @retval None
   */
 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
-{  
+{
+  uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
+
   /* Synchronization error interrupt management *******************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
+  if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
-    {
-      /* Clear the Synchronization error flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+    /* Clear the Synchronization error flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
 
-      /* Update error code */
-      hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
 
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_ERROR;
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
+    
+    /* Set the synchronization error callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* Abort the DMA Transfer */
-      HAL_DMA_Abort(hdcmi->DMA_Handle);
-      
-      /* Synchronization error Callback */
-      HAL_DCMI_ErrorCallback(hdcmi);
-    }
+    /* Abort the DMA Transfer */
+    HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
   }
   /* Overflow interrupt management ********************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET) 
+  if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
-    {
-      /* Clear the Overflow flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
+    /* Clear the Overflow flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
 
-      /* Update error code */
-      hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
 
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_ERROR;
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
+    
+    /* Set the overflow callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* Abort the DMA Transfer */
-      HAL_DMA_Abort(hdcmi->DMA_Handle);
-
-      /* Overflow Callback */
-      HAL_DCMI_ErrorCallback(hdcmi);
-    }
+    /* Abort the DMA Transfer */
+    HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
   }
   /* Line Interrupt management ************************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
+  if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
-    {
-      /* Clear the Line interrupt flag */  
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* Line interrupt Callback */
-      HAL_DCMI_LineEventCallback(hdcmi);
-    }
+    /* Clear the Line interrupt flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+    
+    /* Line interrupt Callback */
+    HAL_DCMI_LineEventCallback(hdcmi);
   }
   /* VSYNC interrupt management ***********************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
+  if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
-    {
-      /* Clear the VSYNC flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* VSYNC Callback */
-      HAL_DCMI_VsyncEventCallback(hdcmi);
-    }
+    /* Clear the VSYNC flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+    
+    /* VSYNC Callback */
+    HAL_DCMI_VsyncEventCallback(hdcmi);
   }
-  /* End of Frame interrupt management ****************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+  /* FRAME interrupt management ***********************************************/
+  if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
-    {   
-      /* Disable the Line interrupt when using snapshot mode */
-      if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
-      {
-        __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE);
-      }
-      /* Disable the End of frame, Vsync, Error and Overrun interrupts */
-      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVF);
-      
-      /* Clear the End of Frame flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-      
-      /* End of Frame Callback */
-      HAL_DCMI_FrameEventCallback(hdcmi);
+    /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+    if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    { 
+      /* Disable the Line, Vsync, Error and Overrun interrupts */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
     }
+
+    /* Disable the Frame interrupt */
+    __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+    /* Frame Callback */
+    HAL_DCMI_FrameEventCallback(hdcmi);
   }
 }
 
 /**
-* @brief  Error DCMI callback.
+  * @brief  Error DCMI callback.
   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
@@ -589,12 +628,12 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
   */
 
 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Peripheral Control functions 
+  *  @brief    Peripheral Control functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                     ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
 [..]  This section provides functions allowing to:
       (+) Configure the CROP feature.
       (+) Enable/Disable the CROP feature.
@@ -613,7 +652,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
   * @param  YSize: DCMI Line number
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -628,8 +667,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
 
   /* Configure CROP */
-  DCMI->CWSIZER = (XSize | (YSize << 16U));
-  DCMI->CWSTRTR = (X0 | (Y0 << 16U));
+  hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
+  hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
 
   /* Initialize the DCMI state*/
   hdcmi->State  = HAL_DCMI_STATE_READY;
@@ -646,7 +685,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
   *                the configuration information for DCMI.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -655,15 +694,15 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
   /* Disable DCMI Crop feature */
-  DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;  
+  hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
 
   /* Change the DCMI state*/
-  hdcmi->State = HAL_DCMI_STATE_READY;   
+  hdcmi->State = HAL_DCMI_STATE_READY;
 
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
@@ -672,7 +711,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
   *                the configuration information for DCMI.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -681,7 +720,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
   /* Enable DCMI Crop feature */
-  DCMI->CR |= (uint32_t)DCMI_CR_CROP;
+  hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
 
   /* Change the DCMI state*/
   hdcmi->State = HAL_DCMI_STATE_READY;
@@ -689,7 +728,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
@@ -697,16 +736,16 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   */
 
 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
-  *  @brief    Peripheral State functions 
+  *  @brief    Peripheral State functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Check the DCMI state.
-      (+) Get the specific DCMI error flag.  
+      (+) Get the specific DCMI error flag.
 
 @endverbatim
   * @{
@@ -718,7 +757,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   *                the configuration information for DCMI.
   * @retval HAL state
   */
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)  
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
 {
   return hdcmi->State;
 }
@@ -733,6 +772,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
 {
   return hdcmi->ErrorCode;
 }
+
 /**
   * @}
   */
@@ -741,11 +781,11 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
 /** @defgroup DCMI_Private_Functions DCMI Private Functions
   * @{
   */
-  
+
 /**
-  * @brief  DMA conversion complete callback. 
+  * @brief  DMA conversion complete callback.
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
@@ -753,9 +793,8 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
   uint32_t tmp = 0U;
  
   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hdcmi->State= HAL_DCMI_STATE_READY;
-
-  if(hdcmi->XferCount != 0U)
+  
+  if(hdcmi->XferCount != 0)
   {
     /* Update memory 0 address location */
     tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
@@ -785,9 +824,19 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
     hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4U*hdcmi->XferSize));
     hdcmi->XferCount = hdcmi->XferTransferNumber;
   }
-
-  /* Enable the Frame interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+  
+  /* Check if the frame is transferred */
+  if(hdcmi->XferCount == hdcmi->XferTransferNumber)
+  {
+    /* Enable the Frame interrupt */
+    __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+    
+    /* When snapshot mode, set dcmi state to ready */
+    if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    {  
+      hdcmi->State= HAL_DCMI_STATE_READY;
+    }
+  }
 }
 
 /**
@@ -798,10 +847,18 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
   */
 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
 {
-  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;     
-  hdcmi->State= HAL_DCMI_STATE_READY;
+  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
+  {
+    /* Initialize the DCMI state*/
+    hdcmi->State = HAL_DCMI_STATE_READY;
+  }
+
+  /* DCMI error Callback */
   HAL_DCMI_ErrorCallback(hdcmi);
 }
+
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h
index e4b0feff24..aec384cc0a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dcmi.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_DCMI_H
@@ -60,23 +60,13 @@
 /** @addtogroup DCMI DCMI
   * @brief DCMI HAL module driver
   * @{
-  */  
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Types DCMI Exported Types
   * @{
   */
-/** 
-  * @brief DCMI Error source
-  */
-typedef enum
-{ 
-  DCMI_ERROR_SYNC = 1,     /*!< Synchronisation error */
-  DCMI_OVERRUN   = 2,      /*!< DCMI Overrun */
-}DCMI_ErrorTypeDef;
-
-
-/** 
+/**
   * @brief  HAL DCMI State structures definition
   */ 
 typedef enum
@@ -85,7 +75,8 @@ typedef enum
   HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
   HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
   HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
-  HAL_DCMI_STATE_ERROR             = 0x04U   /*!< DCMI error state                      */
+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
 }HAL_DCMI_StateTypeDef;
 
 /** 
@@ -127,9 +118,10 @@ typedef struct
   * @{
   */
 #define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */
-#define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001U)    /*!< Overflow error        */
+#define HAL_DCMI_ERROR_OVR       ((uint32_t)0x00000001U)    /*!< Overrun error         */
 #define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002U)    /*!< Synchronization error */
 #define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA       ((uint32_t)0x00000040U)    /*!< DMA error             */
 /**
   * @}
   */
@@ -137,9 +129,9 @@ typedef struct
 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
   * @{
   */ 
-#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously 
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
                                                                     into the destination memory through the DMA             */
-#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of 
+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
                                                                     frame and then transfers a single frame through the DMA */
 /**
   * @}
@@ -147,10 +139,10 @@ typedef struct
 
 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
   * @{
-  */ 
-#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
+  */
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)  /*!< Hardware synchronization data capture (frame/line start/stop)
                                                                    is synchronized with the HSYNC/VSYNC signals                  */
-#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with 
+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
                                                                    synchronization codes embedded in the data flow               */
 
 /**
@@ -160,17 +152,17 @@ typedef struct
 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
   * @{
   */
-#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)     /*!< Pixel clock active on Falling edge */
 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
 
 /**
   * @}
   */
- 
+
 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
   * @{
   */
-#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)    /*!< Vertical synchronization active Low  */
 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
 
 /**
@@ -180,7 +172,7 @@ typedef struct
 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
   * @{
   */ 
-#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)    /*!< Horizontal synchronization active Low  */
 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
 
 /**
@@ -190,7 +182,7 @@ typedef struct
 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
   * @{
   */
-#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)   /*!< Mode JPEG Disabled  */
 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
 
 /**
@@ -200,7 +192,7 @@ typedef struct
 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
   * @{
   */
-#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)     /*!< All frames are captured        */
 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
 
@@ -211,7 +203,7 @@ typedef struct
 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
   * @{
   */
-#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                      /*!< Interface captures 8-bit data on every pixel clock  */
 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
@@ -234,6 +226,16 @@ typedef struct
   */ 
 #define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */
 
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
+  * @{
+  */
+#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count       */
+#define DCMI_POSITION_CWSTRT_VST   (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)   /*!< Required left shift to set crop window vertical start line count */
+
 /**
   * @}
   */
@@ -241,11 +243,11 @@ typedef struct
 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
   * @{
   */
-#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
-#define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
-#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
-#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
-#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
 /**
   * @}
   */
@@ -256,29 +258,29 @@ typedef struct
 
 /** 
   * @brief   DCMI SR register
-  */ 
-#define DCMI_FLAG_HSYNC     ((uint32_t)0x2001U) /* State of HSYNC pin with the correct programmed polarity */
-#define DCMI_FLAG_VSYNC     ((uint32_t)0x2002U) /* State of VSYNC pin with the correct programmed polarity */
-#define DCMI_FLAG_FNE       ((uint32_t)0x2004U) /* Status of the FIFO */
+  */
+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                             */
 /** 
-  * @brief   DCMI RISR register  
+  * @brief   DCMI RIS register
   */ 
-#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
-#define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
-#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
-#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
-#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RISR_OVR_RIS)    /*!< Overrun interrupt flag                */
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)    /*!< Synchronization error interrupt flag  */
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)   /*!< Line interrupt flag                   */
 /** 
-  * @brief   DCMI MISR register  
+  * @brief   DCMI MIS register
   */ 
-#define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001U)
-#define DCMI_FLAG_OVFMI      ((uint32_t)0x1002U)
-#define DCMI_FLAG_ERRMI      ((uint32_t)0x1004U)
-#define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008U)
-#define DCMI_FLAG_LINEMI     ((uint32_t)0x1010U)
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */
+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -311,28 +313,28 @@ typedef struct
 
 /* Interrupt & Flag management */
 /**
-  * @brief  Get the DCMI pending flags.
+  * @brief  Get the DCMI pending flag.
   * @param  __HANDLE__: DCMI handle
   * @param  __FLAG__: Get the specified flag.
-  *         This parameter can be any combination of the following values:
-  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
-  *            @arg DCMI_FLAG_OVFRI: Overflow flag
-  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
-  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
-  *            @arg DCMI_FLAG_LINERI: Line flag     
-  *            @arg DCMI_FLAG_FRAMEMI: Frame capture complete flag mask
-  *            @arg DCMI_FLAG_OVFMI: Overflow flag mask
-  *            @arg DCMI_FLAG_ERRMI: Synchronization error flag mask
-  *            @arg DCMI_FLAG_VSYNCMI: VSYNC flag mask
-  *            @arg DCMI_FLAG_LINEMI: Line flag mask
-  *            @arg DCMI_FLAG_HSYNC: HSYNC flag
-  *            @arg DCMI_FLAG_VSYNC: VSYNC flag
-  *            @arg DCMI_FLAG_FNE: FNE flag   
+  *         This parameter can be one of the following values (no combination allowed)
+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+  *            @arg DCMI_FLAG_FNE: FIFO empty flag
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+  *            @arg DCMI_FLAG_LINERI: Line flag mask
+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
   * @retval The state of FLAG.
   */
 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
-((((__FLAG__) & 0x3000U) == 0x00U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
- (((__FLAG__) & 0x2000U) == 0x00U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
 
 /**
   * @brief  Clear the DCMI pending flags.
@@ -340,7 +342,7 @@ typedef struct
   * @param  __FLAG__: specifies the flag to clear.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
-  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
   *            @arg DCMI_FLAG_LINERI: Line flag mask
@@ -351,10 +353,10 @@ typedef struct
 /**
   * @brief  Enable the specified DCMI interrupts.
   * @param  __HANDLE__:    DCMI handle
-  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
-  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_OVR: Overrun interrupt mask
   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
   *            @arg DCMI_IT_LINE: Line interrupt mask
@@ -365,10 +367,10 @@ typedef struct
 /**
   * @brief  Disable the specified DCMI interrupts.
   * @param  __HANDLE__: DCMI handle
-  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
-  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_OVR: Overrun interrupt mask
   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
   *            @arg DCMI_IT_LINE: Line interrupt mask
@@ -382,7 +384,7 @@ typedef struct
   * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
-  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_OVR: Overrun interrupt mask
   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
   *            @arg DCMI_IT_LINE: Line interrupt mask
@@ -393,16 +395,15 @@ typedef struct
 /**
   * @}
   */
-      
+  
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup DCMI_Exported_Functions
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
   * @{
   */
 
-/** @addtogroup DCMI_Exported_Functions_Group1 
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
  * @{
  */
- 
 /* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
@@ -411,35 +412,38 @@ void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
 /**
   * @}
   */
-  
-/** @addtogroup DCMI_Exported_Functions_Group2 
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
  * @{
  */
- 
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
-void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
+void              HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
   
-/** @addtogroup DCMI_Exported_Functions_Group3 
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
  * @{
  */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
-HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
   
-/** @addtogroup DCMI_Exported_Functions_Group4 
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
  * @{
  */
 /* Peripheral State functions *************************************************/
@@ -455,7 +459,15 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/   
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */
+/**
+  * @}
+  */   
 /* Private macro -------------------------------------------------------------*/
 /** @defgroup DCMI_Private_Macros DCMI Private Macros
   * @{
@@ -514,7 +526,7 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
     
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c
index d86d3669eb..d43b8fdfdc 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c
@@ -2,27 +2,27 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dcmi_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
-  * @brief   DCMI Extension HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  * @version V1.5.0
+  * @date    06-May-2016
+  * @brief   DCMI Extension HAL module driver
+  *          This file provides firmware functions to manage the following
   *          functionalities of DCMI extension peripheral:
-  *           + Extension features functions 
-  *           
-  @verbatim      
+  *           + Extension features functions
+  *
+  @verbatim
   ==============================================================================
                ##### DCMI peripheral extension features  #####
   ==============================================================================
-           
+
   [..] Comparing to other previous devices, the DCMI interface for STM32F446xx 
        devices contains the following additional features :
-       
+
        (+) Support of Black and White cameras 
-   
+
                      ##### How to use this driver #####
   ==============================================================================
   [..] This driver provides functions to manage the Black and White feature
-    
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -52,7 +52,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -86,15 +86,15 @@
 @verbatim   
  ===============================================================================
                 ##### Initialization and Configuration functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Initialize and configure the DCMI
-      (+) De-initialize the DCMI 
+      (+) De-initialize the DCMI
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the DCMI according to the specified
   *         parameters in the DCMI_InitTypeDef and create the associated handle.
@@ -103,13 +103,13 @@
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
-{     
+{
   /* Check the DCMI peripheral state */
   if(hdcmi == NULL)
   {
      return HAL_ERROR;
   }
-  
+
   /* Check function parameters */
   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
@@ -129,10 +129,10 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
   {
     /* Init the low level hardware */
     HAL_DCMI_MspInit(hdcmi);
-  } 
-  
+  }
+
   /* Change the DCMI state */
-  hdcmi->State = HAL_DCMI_STATE_BUSY; 
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
                           /* Configures the HS, VS, DE and PC polarity */
   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
@@ -154,19 +154,19 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
                                      );
   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
   {
-    DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8U)|
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16U) |
-                  ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24U));
+    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |
+                             ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
 
   }
 
-  /* Enable DCMI by setting DCMIEN bit */
-  __HAL_DCMI_ENABLE(hdcmi);
+  /* Enable the Line, Vsync, Error and Overrun interrupts */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
 
   /* Update error code */
   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-  
+
   /* Initialize the DCMI state*/
   hdcmi->State  = HAL_DCMI_STATE_READY;
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h
index 0b78f60f3a..0a6ce50593 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dcmi_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DCMI Extension HAL module.
   ******************************************************************************
   * @attention
@@ -81,27 +81,27 @@ typedef struct
 typedef struct
 {
   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
-                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */
+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode   */
 
   uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
-                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity         */
 
   uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
-                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity         */
 
   uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
-                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity         */
 
   uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
-                                             This parameter can be a value of @ref DCMI_Capture_Rate         */
+                                             This parameter can be a value of @ref DCMI_Capture_Rate           */
 
   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
-                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode     */
 
-  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                  */
 
-  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                
-                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode
+                                             This parameter can be a value of @ref DCMI_MODE_JPEG              */
 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
   uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface 
                                             This parameter can be a value of @ref DCMIEx_Byte_Select_Mode      */
@@ -131,10 +131,10 @@ typedef struct
 /** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
   * @{
   */
-#define DCMI_BSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received data */
-#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
-#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
-#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+#define DCMI_BSM_ALL                 ((uint32_t)0x00000000U)                     /*!< Interface captures all received data                       */
+#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0)                   /*!< Interface captures every other byte from the received data */
+#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1)                   /*!< Interface captures one byte out of four                    */
+#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four                   */
 
 /**
   * @}
@@ -143,7 +143,7 @@ typedef struct
 /** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
   * @{
   */ 
-#define DCMI_OEBS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
+#define DCMI_OEBS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped  */
 #define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
 
 /**
@@ -153,7 +153,7 @@ typedef struct
 /** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
   * @{
   */
-#define DCMI_LSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received lines  */
 #define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
 
 /**
@@ -163,7 +163,7 @@ typedef struct
 /** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
   * @{
   */ 
-#define DCMI_OELS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
+#define DCMI_OELS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped  */
 #define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
 
 /**
@@ -173,14 +173,19 @@ typedef struct
 /**
   * @}
   */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
 
 /* Exported macro ------------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+#define DCMI_POSITION_ESCR_LSC     (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)     /*!< Required left shift to set line start delimiter */
+#define DCMI_POSITION_ESCR_LEC     (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)     /*!< Required left shift to set line end delimiter   */
+#define DCMI_POSITION_ESCR_FEC     (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)     /*!< Required left shift to set frame end delimiter  */
 
+/* Private macro -------------------------------------------------------------*/
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
   * @{
   */
@@ -206,10 +211,12 @@ typedef struct
 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
           STM32F479xx */
+
+
 /**
   * @}
   */
-    
+
 /**
   * @}
   */ 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h
index 5bacfa408a..ce15236df3 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.c
new file mode 100644
index 0000000000..7cb5a5a699
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.c
@@ -0,0 +1,2988 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dfsdm.c
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    06-May-2016
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital Filter for Sigma-Delta Modulators
+  *          (DFSDM) peripherals:
+  *           + Initialization and configuration of channels and filters
+  *           + Regular channels configuration
+  *           + Injected channels configuration
+  *           + Regular/Injected Channels DMA Configuration
+  *           + Interrupts and flags management
+  *           + Analog watchdog feature
+  *           + Short-circuit detector feature
+  *           + Extremes detector feature
+  *           + Clock absence detector feature
+  *           + Break generation on analog watchdog or short-circuit event
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    *** Channel initialization ***
+    ==============================
+    [..]
+      (#) User has first to initialize channels (before filters initialization).
+      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
+        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
+        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the output clock, input, serial interface, analog watchdog,
+          offset and data right bit shift parameters for this channel using the 
+          HAL_DFSDM_ChannelInit() function.
+
+    *** Channel clock absence detector ***
+    ======================================
+    [..]
+      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
+          HAL_DFSDM_ChannelCkabStart_IT().
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
+          absence.
+      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
+          clock absence is detected.
+      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
+          HAL_DFSDM_ChannelCkabStop_IT().
+      (#) Please note that the same mode (polling or interrupt) has to be used 
+          for all channels because the channels are sharing the same interrupt.
+      (#) Please note also that in interrupt mode, if clock absence detector is
+          stopped for one channel, interrupt will be disabled for all channels.
+
+    *** Channel short circuit detector ***
+    ======================================
+    [..]    
+      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
+          or HAL_DFSDM_ChannelScdStart_IT().
+      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
+          circuit.
+      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if 
+          short circuit is detected.
+      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
+          or HAL_DFSDM_ChannelScdStop_IT().
+      (#) Please note that the same mode (polling or interrupt) has to be used 
+          for all channels because the channels are sharing the same interrupt.
+      (#) Please note also that in interrupt mode, if short circuit detector is
+          stopped for one channel, interrupt will be disabled for all channels.
+
+    *** Channel analog watchdog value ***
+    =====================================
+    [..]    
+      (#) Get analog watchdog filter value of a channel using
+          HAL_DFSDM_ChannelGetAwdValue().
+
+    *** Channel offset value ***
+    =====================================
+    [..]    
+      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
+
+    *** Filter initialization ***
+    =============================
+    [..]
+      (#) After channel initialization, user has to init filters.
+      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
+        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+            Please note that DFSDMz_FLT0 global interrupt could be already
+            enabled if interrupt is used for channel.
+        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
+            with DFSDMz filter handle using __HAL_LINKDMA().
+      (#) Configure the regular conversion, injected conversion and filter
+          parameters for this filter using the HAL_DFSDM_FilterInit() function.
+
+    *** Filter regular channel conversion ***
+    =========================================
+    [..]    
+      (#) Select regular channel and enable/disable continuous mode using
+          HAL_DFSDM_FilterConfigRegChannel().
+      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
+          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
+          HAL_DFSDM_FilterRegularMsbStart_DMA().
+      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect 
+          the end of regular conversion.
+      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
+          at the end of regular conversion.
+      (#) Get value of regular conversion and corresponding channel using 
+          HAL_DFSDM_FilterGetRegularValue().
+      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and 
+          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
+          half transfer and at the transfer complete. Please note that 
+          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
+          circular mode.
+      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
+          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
+
+    *** Filter injected channels conversion ***
+    ===========================================
+    [..]
+      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
+      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
+          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
+          HAL_DFSDM_FilterInjectedMsbStart_DMA().
+      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect 
+          the end of injected conversion.
+      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
+          at the end of injected conversion.
+      (#) Get value of injected conversion and corresponding channel using 
+          HAL_DFSDM_FilterGetInjectedValue().
+      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and 
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
+          half transfer and at the transfer complete. Please note that 
+          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
+          circular mode.
+      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
+          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
+
+    *** Filter analog watchdog ***
+    ==============================
+    [..]
+      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
+      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
+      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
+
+    *** Filter extreme detector ***
+    ===============================
+    [..]
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
+      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
+      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
+      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
+
+    *** Filter conversion time ***
+    ==============================
+    [..]
+      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_DFSDM_MODULE_ENABLED
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/** @defgroup DFSDM DFSDM
+  * @brief DFSDM HAL driver module
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Define DFSDM Private Define
+ * @{
+ */
+#define DFSDM_CHCFGR1_CLK_DIV_OFFSET    POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
+#define DFSDM_CHAWSCDR_BKSCD_OFFSET     POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
+#define DFSDM_CHAWSCDR_FOSR_OFFSET      POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
+#define DFSDM_CHCFGR2_OFFSET_OFFSET     POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
+#define DFSDM_CHCFGR2_DTRBS_OFFSET      POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
+#define DFSDM_FLTFCR_FOSR_OFFSET        POSITION_VAL(DFSDM_FLTFCR_FOSR)
+#define DFSDM_FLTCR1_MSB_RCH_OFFSET     8U
+#define DFSDM_FLTCR2_EXCH_OFFSET        POSITION_VAL(DFSDM_FLTCR2_EXCH)
+#define DFSDM_FLTCR2_AWDCH_OFFSET       POSITION_VAL(DFSDM_FLTCR2_AWDCH)
+#define DFSDM_FLTISR_CKABF_OFFSET       POSITION_VAL(DFSDM_FLTISR_CKABF)
+#define DFSDM_FLTISR_SCDF_OFFSET        POSITION_VAL(DFSDM_FLTISR_SCDF)
+#define DFSDM_FLTICR_CLRCKABF_OFFSET    POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
+#define DFSDM_FLTICR_CLRSCDF_OFFSET     POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
+#define DFSDM_FLTRDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
+#define DFSDM_FLTJDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
+#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
+#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
+#define DFSDM_FLTEXMAX_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
+#define DFSDM_FLTEXMIN_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
+#define DFSDM_FLTCNVTIMR_DATA_OFFSET    POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
+#define DFSDM_FLTAWSR_HIGH_OFFSET       POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
+#define DFSDM_MSB_MASK                  0xFFFF0000U
+#define DFSDM_LSB_MASK                  0x0000FFFFU
+#define DFSDM_CKAB_TIMEOUT              5000U
+#define DFSDM1_CHANNEL_NUMBER           4U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Variables DFSDM Private Variables
+  * @{
+  */
+__IO uint32_t                v_dfsdm1ChannelCounter = 0U;
+DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DFSDM_Private_Functions DFSDM Private Functions
+  * @{
+  */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
+static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
+static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
+static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+ *  @brief    Channel initialization and de-initialization functions 
+ *
+@verbatim
+  ==============================================================================
+        ##### Channel initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the DFSDM channel.
+      (+) De-initialize the DFSDM channel.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DFSDM channel according to the specified parameters
+  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_channel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
+  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
+  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
+  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
+  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
+  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
+  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
+  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
+  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
+  
+  /* Check that channel has not been already initialized */
+  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Call MSP init function */
+  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+  
+  /* Update the channel counter */
+  v_dfsdm1ChannelCounter++;
+  
+  /* Configure output serial clock and enable global DFSDM interface only for first channel */
+  if(v_dfsdm1ChannelCounter == 1U)
+  {
+    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
+    /* Set the output serial clock source */
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
+    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
+    
+    /* Reset clock divider */
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
+    if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
+    {
+      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
+      /* Set the output clock divider */
+      DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << 
+                                             DFSDM_CHCFGR1_CLK_DIV_OFFSET);
+    }
+    
+    /* enable the DFSDM global interface */
+    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
+  }
+  
+  /* Set channel input parameters */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | 
+                                         DFSDM_CHCFGR1_CHINSEL);
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 
+                                        hdfsdm_channel->Init.Input.DataPacking | 
+                                        hdfsdm_channel->Init.Input.Pins);
+  
+  /* Set serial interface parameters */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
+  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 
+                                        hdfsdm_channel->Init.SerialInterface.SpiClock);
+  
+  /* Set analog watchdog parameters */
+  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
+  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 
+                                       ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_FOSR_OFFSET));
+
+  /* Set channel offset and right bit shift */
+  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
+  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | 
+                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
+
+  /* Enable DFSDM channel */
+  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
+  
+  /* Set DFSDM Channel to ready state */
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
+
+  /* Store channel handle in DFSDM channel handle table */
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize the DFSDM channel.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_channel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check that channel has not been already deinitialized */
+  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the DFSDM channel */
+  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
+  
+  /* Update the channel counter */
+  v_dfsdm1ChannelCounter--;
+  
+  /* Disable global DFSDM at deinit of last channel */
+  if(v_dfsdm1ChannelCounter == 0U)
+  {
+    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
+  }
+
+  /* Call MSP deinit function */
+  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+
+  /* Set DFSDM Channel in reset state */
+  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
+
+  /* Reset channel handle in DFSDM channel handle table */
+  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the DFSDM channel MSP.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  De-initialize the DFSDM channel MSP.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+ *  @brief    Channel operation functions
+ *
+@verbatim
+  ==============================================================================
+                   ##### Channel operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Manage clock absence detector feature.
+      (+) Manage short circuit detector feature.
+      (+) Get analog watchdog value.
+      (+) Modify offset value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start clock absence detection in polling mode.
+  * @note   Same mode has to be used for all channels.
+  * @note   If clock is not available on this channel during 5 seconds,
+  *         clock absence detection will not be activated and function
+  *         will return HAL_TIMEOUT error.  
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Clear clock absence flag */
+    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U)
+    {
+      DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+      /* Check the Timeout */
+      if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
+      {
+        /* Set timeout status */
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(status == HAL_OK)
+    {
+      /* Start clock absence detection */
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the clock absence detection.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 
+                                               uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t channel;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait clock absence detection */
+    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) == 0U)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Clear clock absence detection flag */
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop clock absence detection in polling mode.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop clock absence detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+    
+    /* Clear clock absence flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+  }
+  /* Return function status */
+  return status;
+}
+ 
+/**
+  * @brief  This function allows to start clock absence detection in interrupt mode.
+  * @note   Same mode has to be used for all channels.
+  * @note   If clock is not available on this channel during 5 seconds,
+  *         clock absence detection will not be activated and function
+  *         will return HAL_TIMEOUT error.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+  __IO uint32_t count = DFSDM_CKAB_TIMEOUT * (SystemCoreClock / 36 / 1000);
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+
+    /* Clear clock absence flag */
+    do
+    {
+      DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+      if (count-- == 0)
+      {
+        /* Set timeout status */
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+    while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U);
+
+    if(status == HAL_OK)
+    {
+      /* Activate clock absence detection interrupt */
+      DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
+
+      /* Start clock absence detection */
+      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Clock absence detection callback. 
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function allows to stop clock absence detection in interrupt mode.
+  * @note   Interrupt will be disabled for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop clock absence detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
+    
+    /* Clear clock absence flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+    /* Disable clock absence detection interrupt */
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start short circuit detection in polling mode.
+  * @note   Same mode has to be used for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Threshold : Short circuit detector threshold.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+  * @param  BreakSignal : Break signals assigned to short circuit event.
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                            uint32_t Threshold,
+                                            uint32_t BreakSignal)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Configure threshold and break signals */
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+                                         Threshold);
+    
+    /* Start short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the short circuit detection.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 
+                                              uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t channel;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get channel number from channel instance */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait short circuit detection */
+    while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0U)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Clear short circuit detection flag */
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop short circuit detection in polling mode.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+    
+    /* Clear short circuit detection flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start short circuit detection in interrupt mode.
+  * @note   Same mode has to be used for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Threshold : Short circuit detector threshold.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
+  * @param  BreakSignal : Break signals assigned to short circuit event.
+  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                               uint32_t Threshold,
+                                               uint32_t BreakSignal)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Activate short circuit detection interrupt */
+    DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
+
+    /* Configure threshold and break signals */
+    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
+    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+                                         Threshold);
+    
+    /* Start short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Short circuit detection callback. 
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_channel);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function allows to stop short circuit detection in interrupt mode.
+  * @note   Interrupt will be disabled for all channels
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t channel;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop short circuit detection */
+    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
+    
+    /* Clear short circuit detection flag */
+    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
+    DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+
+    /* Disable short circuit detection interrupt */
+    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get channel analog watchdog value.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval Channel analog watchdog value.
+  */
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
+}
+
+/**
+  * @brief  This function allows to modify channel offset value.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @param  Offset : DFSDM channel offset.
+  *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+                                                int32_t Offset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
+  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
+  
+  /* Check DFSDM channel state */
+  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Modify channel offset */
+    hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
+    hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+ *  @brief    Channel state function
+ *
+@verbatim
+  ==============================================================================
+                   ##### Channel state function #####
+  ==============================================================================
+    [..]  This section provides function allowing to:
+      (+) Get channel handle state.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the current DFSDM channel handle state.
+  * @param  hdfsdm_channel : DFSDM channel handle.
+  * @retval DFSDM channel state.
+  */
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+{
+  /* Return DFSDM channel handle state */
+  return hdfsdm_channel->State;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+ *  @brief    Filter initialization and de-initialization functions 
+ *
+@verbatim
+  ==============================================================================
+        ##### Filter initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the DFSDM filter.
+      (+) De-initialize the DFSDM filter.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DFSDM filter according to the specified parameters
+  *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check DFSDM Channel handle */
+  if(hdfsdm_filter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
+  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
+  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
+  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
+  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
+  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
+
+  /* Check parameters compatibility */
+  if((hdfsdm_filter->Instance == DFSDM1_Filter0) && 
+    ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) || 
+     (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize DFSDM filter variables with default values */
+  hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;
+  hdfsdm_filter->InjectedChannelsNbr = 1U;
+  hdfsdm_filter->InjConvRemaining    = 1U;
+  hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
+  
+  /* Call MSP init function */
+  HAL_DFSDM_FilterMspInit(hdfsdm_filter);
+
+  /* Set regular parameters */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+  if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
+  }
+
+  if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
+  }
+
+  /* Set injected parameters */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
+  if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
+  {
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
+    assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
+    hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
+  }
+
+  if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
+  }
+
+  if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
+  }
+  else
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
+  }
+  
+  /* Set filter parameters */
+  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
+  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
+                                    ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_OFFSET) |
+                                     (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
+
+  /* Store regular and injected triggers and injected scan mode*/
+  hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;
+  hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;
+  hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
+  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
+  
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+  /* Set DFSDM filter to ready state */
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initializes the DFSDM filter.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check DFSDM filter handle */
+  if(hdfsdm_filter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Disable the DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+  
+  /* Call MSP deinit function */
+  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
+
+  /* Set DFSDM filter in reset state */
+  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DFSDM filter MSP.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_FilterMspInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  De-initializes the DFSDM filter MSP.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+ *  @brief    Filter control functions
+ *
+@verbatim
+  ==============================================================================
+                    ##### Filter control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Select channel and enable/disable continuous mode for regular conversion.
+      (+) Select channels for injected conversion.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to select channel and to enable/disable
+  *         continuous mode for regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channel for regular conversion.
+  *         This parameter can be a value of @ref DFSDM_Channel_Selection.
+  * @param  ContinuousMode : Enable/disable continuous mode for regular conversion.
+  *         This parameter can be a value of @ref DFSDM_ContinuousMode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
+  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Configure channel and continuous mode for regular conversion */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
+    if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
+                                                     DFSDM_FLTCR1_RCONT);
+    }
+    else
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
+    }
+    /* Store continuous mode information */
+    hdfsdm_filter->RegularContMode = ContinuousMode;
+  }  
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to select channels for injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channels for injected conversion.
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Configure channel for injected conversion */
+    hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
+    /* Store number of injected channels */
+    hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
+    /* Update number of injected channels remaining */
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                      hdfsdm_filter->InjectedChannelsNbr : 1U;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+ *  @brief    Filter operation functions
+ *
+@verbatim
+  ==============================================================================
+                    ##### Filter operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular/injected channel.
+      (+) Poll for the end of regular/injected conversion.
+      (+) Stop conversion of regular/injected channel.
+      (+) Start conversion of regular/injected channel and enable interrupt.
+      (+) Call the callback functions at the end of regular/injected conversions.
+      (+) Stop conversion of regular/injected channel and disable interrupt.
+      (+) Start conversion of regular/injected channel and enable DMA transfer.
+      (+) Stop conversion of regular/injected channel and disable DMA transfer.
+      (+) Start analog watchdog and enable interrupt.
+      (+) Call the callback function when analog watchdog occurs.
+      (+) Stop analog watchdog and disable interrupt.
+      (+) Start extreme detector.
+      (+) Stop extreme detector.
+      (+) Get result of regular channel conversion.
+      (+) Get result of injected channel conversion.
+      (+) Get extreme detector maximum and minimum values.
+      (+) Get conversion time.
+      (+) Handle DFSDM interrupt request.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start regular conversion in polling mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Start regular conversion */
+    DFSDM_RegConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the end of regular conversion.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       uint32_t                    Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get timeout */
+    tickstart = HAL_GetTick();  
+
+    /* Wait end of regular conversion */
+    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Check if overrun occurs */
+    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
+    {
+      /* Update error code and call error callback */
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+      /* Clear regular overrun flag */
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+    }
+    /* Update DFSDM filter state only if not continuous conversion and SW trigger */
+    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+    }
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in polling mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop regular conversion */
+    DFSDM_RegConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in interrupt mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Enable interrupts for regular conversions */
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+    
+    /* Start regular conversion */
+    DFSDM_RegConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in interrupt mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable interrupts for regular conversions */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
+    
+    /* Stop regular conversion */
+    DFSDM_RegConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in DMA mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  *         Please note that data on buffer will contain signed regular conversion
+  *         value on 24 most significant bits and corresponding channel on 3 least
+  *         significant bits.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   int32_t                    *pData,
+                                                   uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for regular conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+          (Length != 1U))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start regular conversion */
+      DFSDM_RegConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start regular conversion in DMA mode and to get
+  *         only the 16 most significant bits of conversion.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if injected conversion is ongoing.
+  *         Please note that data on buffer will contain signed 16 most significant
+  *         bits of regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                      int16_t                    *pData,
+                                                      uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for regular conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+          (Length != 1U))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
+    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMARegularHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start regular conversion */
+      DFSDM_RegConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop regular conversion in DMA mode.
+  * @note   This function should be called only if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop current DMA transfer */
+    if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Stop regular conversion */
+      DFSDM_RegConvStop(hdfsdm_filter);
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get regular conversion value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel of regular conversion.
+  * @retval Regular conversion value
+  */
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                        uint32_t                   *Channel)
+{
+  uint32_t reg = 0U;
+  int32_t  value = 0U;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of data register for regular channel */
+  reg = hdfsdm_filter->Instance->FLTRDATAR;
+  
+  /* Extract channel and regular conversion value */
+  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
+  value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
+
+  /* return regular conversion value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in polling mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Start injected conversion */
+    DFSDM_InjConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the end of injected conversion.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Timeout : Timeout value in milliseconds.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       uint32_t                    Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Get timeout */
+    tickstart = HAL_GetTick();  
+
+    /* Wait end of injected conversions */
+    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
+    {
+      /* Check the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+        {
+          /* Return timeout status */
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Check if overrun occurs */
+    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
+    {
+      /* Update error code and call error callback */
+      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+
+      /* Clear injected overrun flag */
+      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+    }
+
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining--;
+    if(hdfsdm_filter->InjConvRemaining == 0U)
+    {
+      /* Update DFSDM filter state only if trigger is software */
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+      }
+      
+      /* end of injected sequence, reset the value */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1U;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in polling mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop injected conversion */
+    DFSDM_InjConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in interrupt mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Enable interrupts for injected conversions */
+    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+    
+    /* Start injected conversion */
+    DFSDM_InjConvStart(hdfsdm_filter);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in interrupt mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Disable interrupts for injected conversions */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
+    
+    /* Stop injected conversion */
+    DFSDM_InjConvStop(hdfsdm_filter);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in DMA mode.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  *         Please note that data on buffer will contain signed injected conversion
+  *         value on 24 most significant bits and corresponding channel on 3 least
+  *         significant bits.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                    int32_t                    *pData,
+                                                    uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for injected conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+          (Length > hdfsdm_filter->InjConvRemaining))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start injected conversion */
+      DFSDM_InjConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start injected conversion in DMA mode and to get
+  *         only the 16 most significant bits of conversion.
+  * @note   This function should be called only when DFSDM filter instance is 
+  *         in idle state or if regular conversion is ongoing.
+  *         Please note that data on buffer will contain signed 16 most significant
+  *         bits of injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  pData : The destination buffer address.
+  * @param  Length : The length of data to be transferred from DFSDM filter to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                       int16_t                    *pData,
+                                                       uint32_t                    Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check destination address and length */
+  if((pData == NULL) || (Length == 0U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check that DMA is enabled for injected conversion */
+  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check parameters compatibility */
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+          (Length > hdfsdm_filter->InjConvRemaining))
+  {
+    status = HAL_ERROR;
+  }
+  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
+          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check DFSDM filter state */
+  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
+          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+  {
+    /* Set callbacks on DMA handler */
+    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
+    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
+    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
+                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;
+    
+    /* Start DMA in interrupt mode */
+    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
+                        (uint32_t) pData, Length) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Start injected conversion */
+      DFSDM_InjConvStart(hdfsdm_filter);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop injected conversion in DMA mode.
+  * @note   This function should be called only if injected conversion is ongoing.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
+     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Stop current DMA transfer */
+    if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
+    {
+      /* Set DFSDM filter in error state */
+      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Stop regular conversion */
+      DFSDM_InjConvStop(hdfsdm_filter);
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get injected conversion value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel of injected conversion.
+  * @retval Injected conversion value
+  */
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 
+                                         uint32_t                   *Channel)
+{
+  uint32_t reg = 0U;
+  int32_t  value = 0U;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of data register for injected channel */
+  reg = hdfsdm_filter->Instance->FLTJDATAR;
+  
+  /* Extract channel and injected conversion value */
+  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
+  value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
+
+  /* return regular conversion value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to start filter analog watchdog in interrupt mode.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  awdParam : DFSDM filter analog watchdog parameters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
+  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
+  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Set analog watchdog data source */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+    hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
+
+    /* Set thresholds and break signals */
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+    hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
+                                           awdParam->HighBreakSignal);
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+    hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
+                                           awdParam->LowBreakSignal);
+
+    /* Set channels and interrupt for analog watchdog */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
+    hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
+                                        DFSDM_FLTCR2_AWDIE);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop filter analog watchdog in interrupt mode.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset channels for analog watchdog and deactivate interrupt */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
+
+    /* Clear all analog watchdog flags */
+    hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
+    
+    /* Reset thresholds and break signals */
+    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
+    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
+
+    /* Reset analog watchdog data source */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start extreme detector feature.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Channels where extreme detector is enabled.
+  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                           uint32_t                    Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Set channels for extreme detector */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+    hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);    
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop extreme detector feature.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t     reg1;
+  __IO uint32_t     reg2;
+
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  
+  /* Check DFSDM filter state */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
+     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset channels for extreme detector */
+    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
+
+    /* Clear extreme detector values */
+    reg1 = hdfsdm_filter->Instance->FLTEXMAX;
+    reg2 = hdfsdm_filter->Instance->FLTEXMIN;    
+    UNUSED(reg1); /* To avoid GCC warning */
+    UNUSED(reg2); /* To avoid GCC warning */
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get extreme detector maximum value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @retval Extreme detector maximum value
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
+  */
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                       uint32_t                   *Channel)
+{
+  uint32_t reg = 0U;
+  int32_t  value = 0U;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of extreme detector maximum register */
+  reg = hdfsdm_filter->Instance->FLTEXMAX;
+  
+  /* Extract channel and extreme detector maximum value */
+  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
+  value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
+
+  /* return extreme detector maximum value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to get extreme detector minimum value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @retval Extreme detector minimum value
+  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
+  */
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                       uint32_t                   *Channel)
+{
+  uint32_t reg = 0U;
+  int32_t  value = 0U;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+  assert_param(Channel != NULL);
+
+  /* Get value of extreme detector minimum register */
+  reg = hdfsdm_filter->Instance->FLTEXMIN;
+  
+  /* Extract channel and extreme detector minimum value */
+  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
+  value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
+
+  /* return extreme detector minimum value */
+  return value;
+}
+
+/**
+  * @brief  This function allows to get conversion time value.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval Conversion time value
+  * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
+  */
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  uint32_t reg = 0U;
+  uint32_t value = 0U;
+  
+  /* Check parameters */
+  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
+
+  /* Get value of conversion timer register */
+  reg = hdfsdm_filter->Instance->FLTCNVTIMR;
+  
+  /* Extract conversion time value */
+  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
+
+  /* return extreme detector minimum value */
+  return value;
+}
+
+/**
+  * @brief  This function handles the DFSDM interrupts.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Check if overrun occurs during regular conversion */
+  if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \
+     ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U))
+  {
+    /* Clear regular overrun flag */
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
+
+    /* Update error code */
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+
+    /* Call error callback */
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+  }
+  /* Check if overrun occurs during injected conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U))
+  {
+    /* Clear injected overrun flag */
+    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
+
+    /* Update error code */
+    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+
+    /* Call error callback */
+    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+  }
+  /* Check if end of regular conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
+  {
+    /* Call regular conversion complete callback */
+    HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+
+    /* End of conversion if mode is not continuous and software trigger */
+    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      /* Disable interrupts for regular conversions */
+      hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
+
+      /* Update DFSDM filter state */
+      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+    }
+  }
+  /* Check if end of injected conversion */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
+  {
+    /* Call injected conversion complete callback */
+    HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining--;
+    if(hdfsdm_filter->InjConvRemaining == 0U)
+    {
+      /* End of conversion if trigger is software */
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        /* Disable interrupts for injected conversions */
+        hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
+
+        /* Update DFSDM filter state */
+        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+      }
+      /* end of injected sequence, reset the value */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1U;
+    }
+  }
+  /* Check if analog watchdog occurs */
+  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \
+          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U))
+  {
+    uint32_t reg = 0U;
+    uint32_t threshold = 0U;
+    uint32_t channel = 0U;
+    
+    /* Get channel and threshold */
+    reg = hdfsdm_filter->Instance->FLTAWSR;
+    threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
+    if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
+    {
+      reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
+    }
+    while((reg & 1U) == 0U)
+    {
+      channel++;
+      reg = reg >> 1U;
+    }
+    /* Clear analog watchdog flag */
+    hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
+                                        (1U << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
+                                        (1U << channel);
+
+    /* Call analog watchdog callback */
+    HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
+  }
+  /* Check if clock absence occurs */
+  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
+         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
+  {
+    uint32_t reg = 0U;
+    uint32_t channel = 0U;
+    
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
+
+    while(channel < DFSDM1_CHANNEL_NUMBER)
+    {
+      /* Check if flag is set and corresponding channel is enabled */
+      if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))
+      {
+        /* Check clock absence has been enabled for this channel */
+        if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
+        {
+          /* Clear clock absence flag */
+          hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+
+          /* Call clock absence callback */
+          HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
+        }
+      }
+      channel++;
+      reg = reg >> 1U;
+    }
+  }
+  /* Check if short circuit detection occurs */
+  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
+         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
+         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
+  {
+    uint32_t reg = 0U;
+    uint32_t channel = 0U;
+    
+    /* Get channel */
+    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
+    while((reg & 1U) == 0U)
+    {
+      channel++;
+      reg = reg >> 1U;
+    }
+    
+    /* Clear short circuit detection flag */
+    hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+
+    /* Call short circuit detection callback */
+    HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
+  }
+}
+
+/**
+  * @brief  Regular conversion complete callback. 
+  * @note   In interrupt mode, user has to read conversion value in this function
+  *         using HAL_DFSDM_FilterGetRegularValue.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Half regular conversion complete callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Injected conversion complete callback. 
+  * @note   In interrupt mode, user has to read conversion value in this function
+  *         using HAL_DFSDM_FilterGetInjectedValue.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Half injected conversion complete callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Filter analog watchdog callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @param  Channel : Corresponding channel.
+  * @param  Threshold : Low or high threshold has been reached.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                        uint32_t Channel, uint32_t Threshold)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  UNUSED(Channel);
+  UNUSED(Threshold);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Error callback. 
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdfsdm_filter);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+ *  @brief    Filter state functions
+ *
+@verbatim
+  ==============================================================================
+                     ##### Filter state functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Get the DFSDM filter state.
+      (+) Get the DFSDM filter error.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the current DFSDM filter handle state.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval DFSDM filter state.
+  */
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  /* Return DFSDM filter handle state */
+  return hdfsdm_filter->State;
+}
+
+/**
+  * @brief  This function allows to get the current DFSDM filter error.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval DFSDM filter error code.
+  */
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+  return hdfsdm_filter->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA half transfer complete callback for regular conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call regular half conversion complete callback */
+  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA transfer complete callback for regular conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call regular conversion complete callback */
+  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA half transfer complete callback for injected conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call injected half conversion complete callback */
+  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA transfer complete callback for injected conversion. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Call injected conversion complete callback */
+  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  DMA error callback. 
+  * @param  hdma : DMA handle.
+  * @retval None
+  */
+static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  /* Get DFSDM filter handle */
+  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Update error code */
+  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
+
+  /* Call error callback */
+  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+}
+
+/**
+  * @brief  This function allows to get the number of injected channels.
+  * @param  Channels : bitfield of injected channels.
+  * @retval Number of injected channels.
+  */
+static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
+{
+  uint32_t nbChannels = 0U;
+  uint32_t tmp;
+  
+  /* Get the number of channels from bitfield */
+  tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
+  while(tmp != 0U)
+  {
+    if((tmp & 1U) != 0U)
+    {
+      nbChannels++;
+    }
+    tmp = (uint32_t) (tmp >> 1U);
+  }
+  return nbChannels;
+}
+
+/**
+  * @brief  This function allows to get the channel number from channel instance.
+  * @param  Instance : DFSDM channel instance.
+  * @retval Channel number.
+  */
+static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
+{
+  uint32_t channel = 0xFFU;
+  
+  /* Get channel from instance */
+  if(Instance == DFSDM1_Channel0)
+  {
+    channel = 0U;
+  }
+  else if(Instance == DFSDM1_Channel1)
+  {
+    channel = 1U;
+  }
+  else if(Instance == DFSDM1_Channel2)
+  {
+    channel = 2U;
+  }
+  else if(Instance == DFSDM1_Channel3)
+  {
+    channel = 3U;
+  }
+
+  return channel;
+}
+
+/**
+  * @brief  This function allows to really start regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Check regular trigger */
+  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
+  {
+    /* Software start of regular conversion */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+  }
+  else /* synchronous trigger */
+  {
+    /* Disable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+    
+    /* Set RSYNC bit in DFSDM_FLTCR1 register */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
+
+    /* Enable DFSDM  filter */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+    
+    /* If injected conversion was in progress, restart it */
+    if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
+    {
+      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+      {
+        hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+      }
+      /* Update remaining injected conversions */
+      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                         hdfsdm_filter->InjectedChannelsNbr : 1U;
+    }
+  }
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+                          HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+  * @brief  This function allows to really stop regular conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Disable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
+  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
+  }
+
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+  
+  /* If injected conversion was in progress, restart it */
+  if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
+  {
+    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+    }
+    /* Update remaining injected conversions */
+    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                       hdfsdm_filter->InjectedChannelsNbr : 1U;
+  }
+  
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
+                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+}
+
+/**
+  * @brief  This function allows to really start injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Check injected trigger */
+  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
+  {
+    /* Software start of injected conversion */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
+  }
+  else /* external or synchronous trigger */
+  {
+    /* Disable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+      
+    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+    {
+      /* Set JSYNC bit in DFSDM_FLTCR1 register */
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
+    }
+    else /* external trigger */
+    {
+      /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+      hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
+    }
+    
+    /* Enable DFSDM filter */
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+
+    /* If regular conversion was in progress, restart it */
+    if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
+       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+    {
+      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+    }
+  }
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
+                         HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
+}
+
+/**
+  * @brief  This function allows to really stop injected conversion.
+  * @param  hdfsdm_filter : DFSDM filter handle.
+  * @retval None
+  */
+static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
+{
+  /* Disable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
+
+  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
+  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
+  {
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
+  }
+  else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
+  {
+    /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
+    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
+  }
+
+  /* Enable DFSDM filter */
+  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
+  
+  /* If regular conversion was in progress, restart it */
+  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
+     (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+  {
+    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+  }
+
+  /* Update remaining injected conversions */
+  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
+                                     hdfsdm_filter->InjectedChannelsNbr : 1U;
+
+  /* Update DFSDM filter state */
+  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
+                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+}
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.h
new file mode 100644
index 0000000000..551e98c1ec
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dfsdm.h
@@ -0,0 +1,691 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dfsdm.h
+  * @author  MCD Application Team
+  * @version V1.5.0
+  * @date    06-May-2016
+  * @brief   Header file of DFSDM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DFSDM_H
+#define __STM32F4xx_HAL_DFSDM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL DFSDM Channel states definition  
+  */ 
+typedef enum
+{
+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
+}HAL_DFSDM_Channel_StateTypeDef;
+
+/** 
+  * @brief  DFSDM channel output clock structure definition  
+  */  
+typedef struct
+{
+  FunctionalState Activation; /*!< Output clock enable/disable */
+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+  uint32_t        Divider;    /*!< Output clock divider.
+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+}DFSDM_Channel_OutputClockTypeDef;
+
+/** 
+  * @brief  DFSDM channel input structure definition  
+  */  
+typedef struct
+{
+  uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */
+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.
+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */
+}DFSDM_Channel_InputTypeDef;
+
+/** 
+  * @brief  DFSDM channel serial interface structure definition  
+  */  
+typedef struct
+{
+  uint32_t Type;     /*!< SPI or Manchester modes.
+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */
+}DFSDM_Channel_SerialInterfaceTypeDef;
+
+/** 
+  * @brief  DFSDM channel analog watchdog structure definition  
+  */  
+typedef struct
+{
+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+}DFSDM_Channel_AwdTypeDef;
+
+/** 
+  * @brief  DFSDM channel init structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
+  int32_t                              Offset;          /*!< DFSDM channel offset.
+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+}DFSDM_Channel_InitTypeDef;
+
+/** 
+  * @brief  DFSDM channel handle structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
+}DFSDM_Channel_HandleTypeDef;
+
+/** 
+  * @brief  HAL DFSDM Filter states definition  
+  */ 
+typedef enum
+{
+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
+}HAL_DFSDM_Filter_StateTypeDef;
+
+/** 
+  * @brief  DFSDM filter regular conversion parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
+}DFSDM_Filter_RegularParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter injected conversion parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
+  uint32_t        ExtTrigger;     /*!< External trigger.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
+}DFSDM_Filter_InjectedParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t SincOrder;       /*!< Sinc filter order.
+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
+  uint32_t Oversampling;    /*!< Filter oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+}DFSDM_Filter_FilterParamTypeDef;
+
+/** 
+  * @brief  DFSDM filter init structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
+}DFSDM_Filter_InitTypeDef;
+
+/** 
+  * @brief  DFSDM filter handle structure definition  
+  */  
+typedef struct
+{
+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */  
+}DFSDM_Filter_HandleTypeDef;
+
+/** 
+  * @brief  DFSDM filter analog watchdog parameters structure definition  
+  */  
+typedef struct
+{
+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
+  uint32_t Channel;         /*!< Analog watchdog channel selection.
+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+}DFSDM_Filter_AwdParamTypeDef;
+
+/**
+  * @}
+  */ 
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
+  * @{
+  */
+
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
+  * @{
+  */
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
+#define DFSDM_CHANNEL_INTERNAL_REGISTER   DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
+  * @{
+  */
+#define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000U) /*!< Standard data packing mode */
+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
+  * @{
+  */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000U) /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000U)  /*!< External SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
+  * @{
+  */
+#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
+  * @{
+  */
+#define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000U) /*!< Software trigger */
+#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
+#define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1*/
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0 and 1*/
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
+  * @{
+  */
+#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)               /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
+  * @{
+  */
+#define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000U) /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
+  * @{
+  */ 
+#define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000U) /*!< No error */
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
+#define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003U) /*!< DMA error occurs */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_BreakSignals DFSDM break signals
+  * @{
+  */
+#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
+#define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001U) /*!< Break signal 0 */
+#define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002U) /*!< Break signal 1 */
+#define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004U) /*!< Break signal 2 */
+#define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008U) /*!< Break signal 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
+  * @{
+  */
+/* DFSDM Channels ------------------------------------------------------------*/
+/* The DFSDM channels are defined as follows:
+   - in 16-bit LSB the channel mask is set
+   - in 16-bit MSB the channel number is set
+   e.g. for channel 3 definition:
+        - the channel mask is 0x00000008U (bit 3 is set)
+        - the channel number 3 is 0x00030000 
+        --> Consequently, channel 3 definition is 0x00000008U | 0x00030000 = 0x00030008 */
+#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
+#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
+#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
+#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
+  * @{
+  */
+#define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
+#define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001U) /*!< Conversion are continuous */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
+  * @{
+  */
+#define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
+#define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DFSDM channel handle state.
+  * @param  __HANDLE__: DFSDM channel handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+
+/** @brief  Reset DFSDM filter handle state.
+  * @param  __HANDLE__: DFSDM filter handle.
+  * @retval None
+  */
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+  * @{
+  */
+/* Channel initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+  * @{
+  */
+/* Channel operation functions ************************************************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+  * @{
+  */
+/* Channel state function *****************************************************/
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+  * @{
+  */
+/* Filter initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+  * @{
+  */
+/* Filter control functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode);
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+  * @{
+  */
+/* Filter operation functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef* awdParam);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+  * @{
+  */
+/* Filter state functions *****************************************************/
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
+* @{
+*/
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0x0FU)
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+/**
+  * @}
+  */ 
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DFSDM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c
index ccf39d78f5..df896ff1ee 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DMA HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -12,32 +12,32 @@
   *           + IO operation functions
   *           + Peripheral State and errors functions
   @verbatim     
-  ==============================================================================      
+  ==============================================================================
                         ##### How to use this driver #####
-  ============================================================================== 
+  ==============================================================================
   [..]
    (#) Enable and configure the peripheral to be connected to the DMA Stream
        (except for internal SRAM/FLASH memories: no initialization is 
        necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests . 
-          
-   (#) For a given Stream, program the required configuration through the following parameters:   
+       and DMA requests .
+
+   (#) For a given Stream, program the required configuration through the following parameters:
        Transfer Direction, Source and Destination data formats, 
        Circular, Normal or peripheral flow control mode, Stream Priority level, 
        Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-                     
+
      *** Polling mode IO operation ***
-     =================================   
-    [..] 
+     =================================
+    [..]
           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
               address and destination address and the Length of data to be transferred
           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
               case a fixed Timeout can be configured by User depending from his application.
-               
-     *** Interrupt mode IO operation ***    
-     =================================== 
-    [..]     
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
@@ -46,38 +46,40 @@
           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
               add his own function by customization of function pointer XferCpltCallback and 
-              XferErrorCallback (i.e a member of DMA handle structure). 
-    [..]                
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
          detection.
-         
+
      (#) Use HAL_DMA_Abort() function to abort the current transfer
-     
+
      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-    
+
      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
            Half-Word data size for the peripheral to access its data register and set Word data size
            for the Memory to gain in access time. Each two half words will be packed and written in
            a single access to a Word in the Memory).
-      
+
      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
            and Destination. In this case the Peripheral Data Size will be applied to both Source
-           and Destination.               
-  
+           and Destination.
+
      *** DMA HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DMA HAL driver.
        
       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
-     
-     [..] 
-      (@) You can refer to the DMA HAL driver header file for more useful macros  
-  
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -124,7 +126,6 @@
 #ifdef HAL_DMA_MODULE_ENABLED
 
 /* Private types -------------------------------------------------------------*/
-
 typedef struct
 {
   __IO uint32_t ISR;   /*!< DMA interrupt status register */
@@ -137,7 +138,7 @@ typedef struct
 /** @addtogroup DMA_Private_Constants
  * @{
  */
- #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000U)  /* 1s */
+ #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */
 /**
   * @}
   */
@@ -148,29 +149,30 @@ typedef struct
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
 
 /**
   * @}
   */  
   
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup DMA_Exported_Functions
   * @{
   */
 
 /** @addtogroup DMA_Exported_Functions_Group1
   *
-@verbatim   
+@verbatim
  ===============================================================================
              ##### Initialization and de-initialization functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This section provides functions allowing to initialize the DMA Stream source
     and destination addresses, incrementation and data sizes, transfer direction, 
     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
     [..]
     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.  
+    reference manual.
 
 @endverbatim
   * @{
@@ -186,6 +188,8 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 {
   uint32_t tmp = 0U;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs;
 
   /* Check the DMA peripheral state */
   if(hdma == NULL)
@@ -212,10 +216,32 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
   }
+  
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
 
   /* Change DMA peripheral state */
   hdma->State = HAL_DMA_STATE_BUSY;
-
+  
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+  
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
   /* Get the CR register value */
   tmp = hdma->Instance->CR;
 
@@ -255,6 +281,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   {
     /* Get the FIFO threshold */
     tmp |= hdma->Init.FIFOThreshold;
+    
+    if(DMA_CheckFifoParam(hdma) != HAL_OK)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+      
+      return HAL_ERROR; 
+    }
   }
   
   /* Write to DMA Stream FCR */
@@ -262,11 +299,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 
   /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
      DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
-  DMA_CalcBaseAndBitshift(hdma);
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
 
   /* Initialize the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
+                                                                                     
   /* Initialize the DMA state */
   hdma->State = HAL_DMA_STATE_READY;
 
@@ -282,7 +322,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 {
   DMA_Base_Registers *regs;
-  
+
   /* Check the DMA peripheral state */
   if(hdma == NULL)
   {
@@ -292,7 +332,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   /* Check the DMA peripheral state */
   if(hdma->State == HAL_DMA_STATE_BUSY)
   {
-     return HAL_ERROR;
+    /* Return error status */
+    return HAL_BUSY;
   }
 
   /* Disable the selected DMA Streamx */
@@ -343,7 +384,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 @verbatim   
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Configure the source, destination address and data length and Start DMA transfer
       (+) Configure the source, destination address and data length and 
@@ -359,7 +400,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 /**
   * @brief  Starts the DMA Transfer.
   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
+  *                     the configuration information for the specified DMA Stream.
   * @param  SrcAddress: The source memory Buffer address
   * @param  DstAddress: The destination memory Buffer address
   * @param  DataLength: The length of data to be transferred from source to destination
@@ -367,29 +408,41 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   */
 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
   /* Process locked */
   __HAL_LOCK(hdma);
 
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK; 
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  } 
+  return status; 
 }
 
 /**
-  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @brief  Starts the DMA Transfer with interrupt enabled.
   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream.  
   * @param  SrcAddress: The source memory Buffer address
@@ -399,30 +452,54 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
   */
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 
   /* Process locked */
   __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable all interrupts */
-  hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
-  hdma->Instance->FCR |= DMA_IT_FE;
-
-   /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
-} 
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }
+  
+  return status;
+}
 
 /**
   * @brief  Aborts the DMA Transfer.
@@ -438,37 +515,86 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
   */
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tickstart = 0U;
-
-  /* Disable the stream */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check if the DMA Stream is effectively disabled */
-  while((hdma->Instance->CR & DMA_SxCR_EN) != 0U)
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  uint32_t tickstart = HAL_GetTick();
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
   {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
-    }
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    return HAL_ERROR;
   }
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma);
+  else
+  {
+    /* Disable all the transfer interrupts */
+    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+    hdma->Instance->FCR &= ~(DMA_IT_FE);
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  &= ~(DMA_IT_HT);
+    }
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Check if the DMA Stream is effectively disabled */
+    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Change the DMA state*/
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  return HAL_OK;
+}
 
-  /* Change the DMA state*/
-  hdma->State = HAL_DMA_STATE_READY;
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hdma->State = HAL_DMA_STATE_ABORT;
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+  }
 
   return HAL_OK;
 }
@@ -477,20 +603,30 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
   * @brief  Polling for transfer complete.
   * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
   *                        the configuration information for the specified DMA Stream.
-  * @param  CompleteLevel: Specifies the DMA level complete.  
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
   * @param  Timeout:       Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
 {
-  uint32_t temp, tmp, tmp1, tmp2;
-  uint32_t tickstart = 0U;
-
+  HAL_StatusTypeDef status = HAL_OK; 
+  uint32_t temp;
+  uint32_t tickstart = HAL_GetTick(); 
+  uint32_t tmpisr;
+  
   /* calculate DMA base and stream number */
   DMA_Base_Registers *regs;
   
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
+  /* Polling mode not supported in circular mode and double buffering mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
   /* Get the level transfer complete flag */
   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
   {
@@ -502,126 +638,97 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     /* Half Transfer Complete flag */
     temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
   }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while((regs->ISR & temp) == RESET)
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
+  
+  while((tmpisr & temp) == RESET )
   {
-    tmp  = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
-    tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
-    tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
-    if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
-    {
-      if(tmp != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-        /* Clear the transfer error flag */
-        regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-      }
-      if(tmp1 != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-        /* Clear the FIFO error flag */
-        regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-      }
-      if(tmp2 != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-        /* Clear the Direct Mode error flag */
-        regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-      }
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-    }
-    /* Check for the Timeout */
+    /* Check for the Timeout (Not applicable in circular mode)*/
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 
         /* Process Unlocked */
         __HAL_UNLOCK(hdma);
-
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
         return HAL_TIMEOUT;
       }
     }
+    
+    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      
+      /* Clear the Direct Mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+    }
   }
+  
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      HAL_DMA_Abort(hdma);
+    
+      /* Clear the half transfer and transfer complete flags */
+      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
 
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      return HAL_ERROR;
+   }
+
+   status = HAL_ERROR;
+  }
+  
+  /* Get the level transfer complete flag */
   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
   {
     /* Clear the half transfer and transfer complete flags */
     regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-
-    /* Multi_Buffering mode enabled */
-    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
-    {
-      /* Current memory buffer used is Memory 0 */
-      if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_MEM0;
-      }
-      /* Current memory buffer used is Memory 1 */
-      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_MEM1;
-      }
-    }
-    else
-    {
-      /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
-         are complete) */
-      hdma->State = HAL_DMA_STATE_READY_MEM0;
-    }
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
   }
   else
   {
-    /* Clear the half transfer complete flag */
-    regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
-    /* Multi_Buffering mode enabled */
-    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
-    {
-      /* Current memory buffer used is Memory 0 */
-      if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-      }
-      /* Current memory buffer used is Memory 1 */
-      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
-      }
-    }
-    else
-    {
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-    }
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
   }
-  return HAL_OK;
+  
+  return status;
 }
 
 /**
@@ -632,150 +739,140 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   */
 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 {
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs;
+  uint32_t tmpisr;
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600;
 
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr = regs->ISR;
 
   /* Transfer Error Interrupt management ***************************************/
-  if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
     {
       /* Disable the transfer error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
+      hdma->Instance->CR  &= ~(DMA_IT_TE);
+      
       /* Clear the transfer error flag */
       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-
+      
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* FIFO Error Interrupt management ******************************************/
-  if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
     {
-      /* Disable the FIFO Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
-
       /* Clear the FIFO error flag */
       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* Direct Mode Error Interrupt management ***********************************/
-  if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
     {
-      /* Disable the direct mode Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
-
       /* Clear the direct mode error flag */
       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* Half Transfer Complete Interrupt management ******************************/
-  if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
     {
+      /* Clear the half transfer complete flag */
+      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+      
       /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
       {
-        /* Clear the half transfer complete flag */
-        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
         /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
         {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
         }
         /* Current memory buffer used is Memory 1 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
+        else
         {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
         }
       }
       else
       {
         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
         {
           /* Disable the half transfer interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+        
+        if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
         }
-        /* Clear the half transfer complete flag */
-        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-      }
-
-      if(hdma->XferHalfCpltCallback != NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
       }
     }
   }
   /* Transfer Complete Interrupt management ***********************************/
-  if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
     {
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+      /* Clear the transfer complete flag */
+      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+      
+      if(HAL_DMA_STATE_ABORT == hdma->State)
       {
-        /* Clear the transfer complete flag */
-        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+        /* Disable all the transfer interrupts */
+        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+        hdma->Instance->FCR &= ~(DMA_IT_FE);
+        
+        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+        {
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
 
+        /* Clear all interrupt flags at correct offset within the register */
+        regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        if(hdma->XferAbortCallback != NULL)
+        {
+          hdma->XferAbortCallback(hdma);
+        }
+        return;
+      }
+
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
         /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
         {
           if(hdma->XferM1CpltCallback != NULL)
           {
@@ -784,7 +881,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           }
         }
         /* Current memory buffer used is Memory 1 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
+        else
         {
           if(hdma->XferCpltCallback != NULL)
           {
@@ -796,22 +893,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
       else
       {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
         {
           /* Disable the transfer complete interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+          hdma->Instance->CR  &= ~(DMA_IT_TC);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
         }
-        /* Clear the transfer complete flag */
-        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY_MEM0;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
 
         if(hdma->XferCpltCallback != NULL)
         {
@@ -821,6 +913,169 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       }
     }
   }
+  
+  /* manage error case */
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+
+      do
+      {
+        if (++count > timeout)
+        {
+          break;
+        }
+      }
+      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+    }
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifer
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback:            pointer to private callbacsk function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                      
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifer
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
 }
 
 /**
@@ -871,7 +1126,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-  
+
 /** @addtogroup DMA_Private_Functions
   * @{
   */
@@ -907,7 +1162,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
   {
     /* Configure DMA Stream source address */
     hdma->Instance->PAR = SrcAddress;
-    
+
     /* Configure DMA Stream destination address */
     hdma->Instance->M0AR = DstAddress;
   }
@@ -940,10 +1195,104 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
   
   return hdma->StreamBaseAddress;
 }
+
+/**
+  * @brief  Checks compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmp = hdma->Init.FIFOThreshold;
+  
+  /* Memory Data size equal to Byte */
+  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (tmp)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+        if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if(hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+      case DMA_FIFO_THRESHOLD_FULL:
+        break;
+      default:
+        break;
+    }
+  }
+  
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (tmp)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+        status = HAL_ERROR;
+        break;
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;   
+      default:
+        break;
+    }
+  }
+  
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (tmp)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+      case DMA_FIFO_THRESHOLD_FULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+		break;
+      default:
+        break;
+    }
+  } 
+  
+  return status; 
+}
+
 /**
   * @}
-  */  
-  
+  */
+
 #endif /* HAL_DMA_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h
index aa62373765..13258838fe 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
@@ -108,7 +108,7 @@ typedef struct
                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 
   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
-                                      It specifies the amount of data to be transferred in a single non interruptable 
+                                      It specifies the amount of data to be transferred in a single non interruptible 
                                       transaction. 
                                       This parameter can be a value of @ref DMA_Peripheral_burst
                                       @note The burst mode is possible only if the address Increment mode is enabled. */
@@ -122,15 +122,10 @@ typedef enum
 {
   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_READY_MEM0        = 0x11U,  /*!< DMA Mem0 process success            */
-  HAL_DMA_STATE_READY_MEM1        = 0x21U,  /*!< DMA Mem1 process success            */
-  HAL_DMA_STATE_READY_HALF_MEM0   = 0x31U,  /*!< DMA Mem0 Half process success       */
-  HAL_DMA_STATE_READY_HALF_MEM1   = 0x41U,  /*!< DMA Mem1 Half process success       */
   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_BUSY_MEM0         = 0x12U,  /*!< DMA Mem0 process is ongoing         */
-  HAL_DMA_STATE_BUSY_MEM1         = 0x22U,  /*!< DMA Mem1 process is ongoing         */
   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04U   /*!< DMA error state                     */
+  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
 }HAL_DMA_StateTypeDef;
 
 /** 
@@ -142,6 +137,20 @@ typedef enum
   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
 }HAL_DMA_LevelCompleteTypeDef;
 
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
 /** 
   * @brief  DMA handle Structure definition
   */
@@ -155,21 +164,26 @@ typedef struct __DMA_HandleTypeDef
 
   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 
-  void                       *Parent;                                                      /*!< Parent object state                    */  
+  void                       *Parent;                                                      /*!< Parent object state                    */ 
 
   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 
   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 
   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
-
+  
+  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
+  
   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
+  
+  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  
 
- __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                         */
-
+ __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
+  
  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
 
- uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */ 
+ uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
+ 
 }DMA_HandleTypeDef;
 
 /**
@@ -187,11 +201,14 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA Error Code 
   * @{
   */ 
-#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error             */
-#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001U)    /*!< Transfer error       */
-#define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002U)    /*!< FIFO error           */
-#define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004U)    /*!< Direct Mode error    */
-#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error        */
+#define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                               */
+#define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                         */
+#define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                             */
+#define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                      */
+#define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                          */
+#define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                        */
+#define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing   */ 
+#define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                     */     
 /**
   * @}
   */
@@ -221,7 +238,7 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 /**
   * @}
-  */  
+  */
         
 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
   * @brief    DMA peripheral incremented mode 
@@ -326,7 +343,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA peripheral burst 
   * @{
   */ 
-#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)  
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
@@ -654,8 +671,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
 /**
   * @}
   */ 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c
index a4709ac561..929c5c5f0d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c
@@ -2,87 +2,98 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma2d.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DMA2D HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the DMA2D peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral Control functions 
   *           + Peripheral State and Errors functions
   *
-  @verbatim 
+  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
     [..]
-      (#) Program the required configuration through following parameters:   
-          the Transfer Mode, the output color mode and the output offset using 
+      (#) Program the required configuration through the following parameters:
+          the transfer mode, the output color mode and the output offset using
           HAL_DMA2D_Init() function.
 
-      (#) Program the required configuration through following parameters:   
-          the input color mode, the input color, input alpha value, alpha mode 
-          and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
+      (#) Program the required configuration through the following parameters:
+          the input color mode, the input color, the input alpha value, the alpha mode,
+          and the input offset using HAL_DMA2D_ConfigLayer() function for foreground 
           or/and background layer.
           
      *** Polling mode IO operation ***
-     =================================   
-    [..]        
-       (+) Configure the pdata, Destination and data length and Enable 
-           the transfer using HAL_DMA2D_Start() 
-       (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+     =================================
+    [..]
+       (#) Configure pdata parameter (explained hereafter), destination and data length
+           and enable the transfer using HAL_DMA2D_Start().
+       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
            user can specify the value of timeout according to his end application.
-               
-     *** Interrupt mode IO operation ***    
+
+     *** Interrupt mode IO operation ***
      ===================================
-     [..] 
-       (#) Configure the pdata, Destination and data length and Enable 
-           the transfer using HAL_DMA2D_Start_IT() 
-       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
-       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can 
-           add his own function by customization of function pointer XferCpltCallback and 
-           XferErrorCallback (i.e a member of DMA2D handle structure). 
+     [..]
+       (#) Configure pdata parameter, destination and data length and enable 
+           the transfer using HAL_DMA2D_Start_IT().
+       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
+       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
+           add his own function by customization of function pointer XferCpltCallback (member
+           of DMA2D handle structure).
+       (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
+           XferErrorCallback.
 
-         -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
-               color, in Memory-to-memory or memory-to-memory with pixel format
-               conversion the pdata is the source address.
+         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
+               color, in Memory-to-memory or Memory-to-Memory with pixel format
+               conversion pdata is the source address.
 
-         -@-   Configure the foreground source address, the background source address, 
-               the Destination and data length and Enable the transfer using 
+         -@-   Configure the foreground source address, the background source address,
+               the destination and data length then Enable the transfer using
                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
-               in interrupt mode.
-               
+               in interrupt mode
+
          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
                are used if the memory to memory with blending transfer mode is selected.
-                   
-      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
-          HAL_DMA2D_EnableCLUT() functions.
 
-      (#) Optionally, configure and enable LineInterrupt using the following function:
-          HAL_DMA2D_ProgramLineEvent().
-   
-      (#) The transfer can be suspended, continued and aborted using the following
+      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
+
+      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two 
+          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
+          HAL_DMA2D_DisableDeadTime().
+
+      (#) The transfer can be suspended, resumed and aborted using the following
           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
-                     
-      (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()                   
+
+      (#) The CLUT loading can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
+          HAL_DMA2D_CLUTLoading_Abort().
+
+      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
+      
+      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
 
      *** DMA2D HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DMA2D HAL driver :
-       
+
       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
-      (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
-      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
-     
-     [..] 
+      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
+
+     [..]
       (@) You can refer to the DMA2D HAL driver header file for more useful macros
-                                  
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -112,7 +123,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -120,7 +131,8 @@
 /** @addtogroup STM32F4xx_HAL_Driver
   * @{
   */
-/** @addtogroup DMA2D
+
+/** @defgroup DMA2D  DMA2D
   * @brief DMA2D HAL module driver
   * @{
   */
@@ -131,11 +143,41 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @addtogroup DMA2D_Private_Defines
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
   * @{
   */
-#define HAL_TIMEOUT_DMA2D_ABORT      ((uint32_t)1000U)  /* 1s  */
-#define HAL_TIMEOUT_DMA2D_SUSPEND    ((uint32_t)1000U)  /* 1s  */
+
+/** @defgroup DMA2D_TimeOut DMA2D Time Out
+  * @{
+  */
+#define DMA2D_TIMEOUT_ABORT           ((uint32_t)1000U)  /*!<  1s  */
+#define DMA2D_TIMEOUT_SUSPEND         ((uint32_t)1000U)  /*!<  1s  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Shifts DMA2D Shifts
+  * @{
+  */
+#define DMA2D_POSITION_FGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)    /*!< Required left shift to set foreground CLUT size */
+#define DMA2D_POSITION_BGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)    /*!< Required left shift to set background CLUT size */
+
+#define DMA2D_POSITION_FGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)   /*!< Required left shift to set foreground CLUT color mode */
+#define DMA2D_POSITION_BGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)   /*!< Required left shift to set background CLUT color mode */
+
+#define DMA2D_POSITION_AMTCR_DT       (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)      /*!< Required left shift to set deadtime value */
+
+#define DMA2D_POSITION_FGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)    /*!< Required left shift to set foreground alpha mode */
+#define DMA2D_POSITION_BGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)    /*!< Required left shift to set background alpha mode */
+
+#define DMA2D_POSITION_FGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
+#define DMA2D_POSITION_BGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
+
+#define DMA2D_POSITION_NLR_PL         (uint32_t)POSITION_VAL(DMA2D_NLR_PL)        /*!< Required left shift to set pixels per lines value */
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -154,36 +196,34 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
 
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA2D_Exported_Functions
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
   * @{
   */
 
-/** @defgroup DMA2D_Group1 Initialization and Configuration functions
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief   Initialization and Configuration functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                 ##### Initialization and Configuration functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Initialize and configure the DMA2D
-      (+) De-initialize the DMA2D 
+      (+) De-initialize the DMA2D
 
 @endverbatim
   * @{
   */
-    
+
 /**
-  * @brief  Initializes the DMA2D according to the specified
+  * @brief  Initialize the DMA2D according to the specified
   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
   *                 the configuration information for the DMA2D.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
-{ 
-  uint32_t tmp = 0U;
-
+{
   /* Check the DMA2D peripheral state */
   if(hdma2d == NULL)
   {
@@ -203,48 +243,18 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
     /* Init the low level hardware */
     HAL_DMA2D_MspInit(hdma2d);
   }
-  
+
   /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY;  
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
 
-/* DMA2D CR register configuration -------------------------------------------*/
-  /* Get the CR register value */
-  tmp = hdma2d->Instance->CR;
+  /* DMA2D CR register configuration -------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
 
-  /* Clear Mode bits */
-  tmp &= (uint32_t)~DMA2D_CR_MODE;
+  /* DMA2D OPFCCR register configuration ---------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
 
-  /* Prepare the value to be wrote to the CR register */
-  tmp |= hdma2d->Init.Mode;
-
-  /* Write to DMA2D CR register */
-  hdma2d->Instance->CR = tmp;
-
-/* DMA2D OPFCCR register configuration ---------------------------------------*/
-  /* Get the OPFCCR register value */
-  tmp = hdma2d->Instance->OPFCCR;
-
-  /* Clear Color Mode bits */
-  tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
-
-  /* Prepare the value to be wrote to the OPFCCR register */
-  tmp |= hdma2d->Init.ColorMode;
-
-  /* Write to DMA2D OPFCCR register */
-  hdma2d->Instance->OPFCCR = tmp;
-
-/* DMA2D OOR register configuration ------------------------------------------*/  
-  /* Get the OOR register value */
-  tmp = hdma2d->Instance->OOR;
-
-  /* Clear Offset bits */
-  tmp &= (uint32_t)~DMA2D_OOR_LO;
-
-  /* Prepare the value to be wrote to the OOR register */
-  tmp |= hdma2d->Init.OutputOffset;
-
-  /* Write to DMA2D OOR register */
-  hdma2d->Instance->OOR = tmp;
+  /* DMA2D OOR register configuration ------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);  
 
   /* Update error code */
   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
@@ -271,9 +281,56 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
      return HAL_ERROR;
   }
 
-  /* DeInit the low level hardware */
+  /* Before aborting any DMA2D transfer or CLUT loading, check
+     first whether or not DMA2D clock is enabled */
+  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+  {
+    /* Abort DMA2D transfer if any */
+    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+    {
+      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+      {
+        /* Issue when aborting DMA2D transfer */
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Abort background CLUT loading if any */
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {
+        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
+        {
+          /* Issue when aborting background CLUT loading */
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Abort foreground CLUT loading if any */
+        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+        {
+          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
+          {
+            /* Issue when aborting foreground CLUT loading */
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+  }
+
+  /* Carry on with de-initialization of low level hardware */
   HAL_DMA2D_MspDeInit(hdma2d);
 
+  /* Reset DMA2D control registers*/
+  hdma2d->Instance->CR = 0U;
+  hdma2d->Instance->FGOR = 0U;
+  hdma2d->Instance->BGOR = 0U;
+  hdma2d->Instance->FGPFCCR = 0U;
+  hdma2d->Instance->BGPFCCR = 0U;
+  hdma2d->Instance->OPFCCR = 0U;
+
   /* Update error code */
   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
 
@@ -296,9 +353,10 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdma2d);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DMA2D_MspInit could be implemented in the user file
-   */ 
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspInit can be implemented in the user file.
+   */
 }
 
 /**
@@ -311,55 +369,61 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdma2d);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DMA2D_MspDeInit could be implemented in the user file
-   */ 
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspDeInit can be implemented in the user file.
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup DMA2D_Group2 IO operation functions 
- *  @brief   IO operation functions  
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+ *  @brief   IO operation functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure the pdata, destination address and data size and 
-          Start DMA2D transfer.
-      (+) Configure the source for foreground and background, destination address 
-          and data size and Start MultiBuffer DMA2D transfer.
-      (+) Configure the pdata, destination address and data size and 
-          Start DMA2D transfer with interrupt.
-      (+) Configure the source for foreground and background, destination address 
-          and data size and Start MultiBuffer DMA2D transfer with interrupt.
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer.
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer with interrupt.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer with interrupt.
       (+) Abort DMA2D transfer.
       (+) Suspend DMA2D transfer.
-      (+) Continue DMA2D transfer.
-      (+) Configure CLUT Loading with interrupt enabled
+      (+) Resume DMA2D transfer.
+      (+) Enable CLUT transfer.
+      (+) Configure CLUT loading then start transfer in polling mode.
+      (+) Configure CLUT loading then start transfer in interrupt mode.
+      (+) Abort DMA2D CLUT loading.
+      (+) Suspend DMA2D CLUT loading.
+      (+) Resume DMA2D CLUT loading.
       (+) Poll for transfer complete.
       (+) handle DMA2D interrupt request.
       (+) Transfer watermark callback.
       (+) CLUT Transfer Complete callback.
-        
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Start the DMA2D Transfer.
-  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
-  *                     the configuration information for the DMA2D.  
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
   * @param  pdata:      Configure the source memory Buffer address if 
-  *                     the memory to memory or memory to memory with pixel format 
-  *                     conversion DMA2D mode is selected, and configure 
-  *                     the color value if register to memory DMA2D mode is selected.
+  *                     Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure 
+  *                     the color value if Register-to-Memory mode is selected.
   * @param  DstAddress: The destination memory Buffer address.
-  * @param  Width:      The width of data to be transferred from source to destination.
-  * @param  Height:      The height of data to be transferred from source to destination.
+  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
@@ -367,7 +431,7 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u
   /* Check the parameters */
   assert_param(IS_DMA2D_LINE(Height));
   assert_param(IS_DMA2D_PIXEL(Width));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
 
@@ -385,23 +449,23 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u
 
 /**
   * @brief  Start the DMA2D Transfer with interrupt enabled.
-  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
-  *                     the configuration information for the DMA2D.  
-  * @param  pdata:      Configure the source memory Buffer address if 
-  *                     the memory to memory or memory to memory with pixel format 
-  *                     conversion DMA2D mode is selected, and configure 
-  *                     the color value if register to memory DMA2D mode is selected.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  pdata:      Configure the source memory Buffer address if
+  *                     the Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure 
+  *                     the color value if Register-to-Memory mode is selected.
   * @param  DstAddress: The destination memory Buffer address.
-  * @param  Width:      The width of data to be transferred from source to destination.
-  * @param  Height:     The height of data to be transferred from source to destination.
+  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
-{  
+{
   /* Check the parameters */
   assert_param(IS_DMA2D_LINE(Height));
   assert_param(IS_DMA2D_PIXEL(Width));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
 
@@ -411,8 +475,8 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata
   /* Configure the source, destination address and the data size */
   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
 
- /* Enable the transfer complete,transfer Error and configuration error interrupts */
-  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
 
   /* Enable the Peripheral */
   __HAL_DMA2D_ENABLE(hdma2d);
@@ -422,13 +486,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata
 
 /**
   * @brief  Start the multi-source DMA2D Transfer.
-  * @param  hdma2d:      pointer to a DMA2D_HandleTypeDef structure that contains
-  *                      the configuration information for the DMA2D.  
-  * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
-  * @param  SrcAddress2: The source memory Buffer address of the background layer.
-  * @param  DstAddress:  The destination memory Buffer address
-  * @param  Width:       The width of data to be transferred from source to destination.
-  * @param  Height:      The height of data to be transferred from source to destination.
+  * @param  hdma2d:      Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                      the configuration information for the DMA2D.
+  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address for the background layer.
+  * @param  DstAddress:  The destination memory Buffer address.
+  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
@@ -436,15 +500,15 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t
   /* Check the parameters */
   assert_param(IS_DMA2D_LINE(Height));
   assert_param(IS_DMA2D_PIXEL(Width));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
 
   /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
 
   /* Configure DMA2D Stream source2 address */
-  hdma2d->Instance->BGMAR = SrcAddress2;
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
 
   /* Configure the source, destination address and the data size */
   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
@@ -457,13 +521,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t
 
 /**
   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
-  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
-  *                     the configuration information for the DMA2D.  
-  * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
-  * @param  SrcAddress2: The source memory Buffer address of the background layer.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address for the background layer.
   * @param  DstAddress:  The destination memory Buffer address.
-  * @param  Width:       The width of data to be transferred from source to destination.
-  * @param  Height:      The height of data to be transferred from source to destination.
+  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).
+  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
@@ -471,21 +535,21 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
   /* Check the parameters */
   assert_param(IS_DMA2D_LINE(Height));
   assert_param(IS_DMA2D_PIXEL(Width));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
 
   /* Change DMA2D peripheral state */
   hdma2d->State = HAL_DMA2D_STATE_BUSY;
- 
+
   /* Configure DMA2D Stream source2 address */
-  hdma2d->Instance->BGMAR = SrcAddress2;
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
 
   /* Configure the source, destination address and the data size */
   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
 
-  /* Enable the transfer complete,transfer Error and configuration error interrupts */
-  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
 
   /* Enable the Peripheral */
   __HAL_DMA2D_ENABLE(hdma2d);
@@ -502,46 +566,50 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
 {
   uint32_t tickstart = 0U;
-  uint32_t regValue; 
 
-  /* Abort the current DMA2D transfer */
-  /* Calculate the new CR register value : Reset START bit and Set Abort bit*/
-  regValue = (hdma2d->Instance->CR & (~DMA2D_CR_START)) | DMA2D_CR_ABORT;
-  hdma2d->Instance->CR = regValue;
+  /* Abort the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no
+     effect on START bitvalue). */
+   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
   /* Check if the DMA2D is effectively disabled */
-  while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
   {
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
     {
       /* Update error code */
       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-      
+
       /* Change the DMA2D state */
-      hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-      
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
       /* Process Unlocked */
       __HAL_UNLOCK(hdma2d);
-      
+
       return HAL_TIMEOUT;
     }
   }
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma2d);
+
+  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
 
   /* Change the DMA2D state*/
   hdma2d->State = HAL_DMA2D_STATE_READY;
 
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Suspend the DMA2D Transfer.
   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
-  *                 the configuration information for the DMA2D. 
+  *                 the configuration information for the DMA2D.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
@@ -549,31 +617,41 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
   uint32_t tickstart = 0U;
 
   /* Suspend the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no
+     effect on START bitvalue). */
   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
   /* Check if the DMA2D is effectively suspended */
-  while(((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) && \
-        ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))        
+  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+    && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
   {
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
     {
       /* Update error code */
       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-      
+
       /* Change the DMA2D state */
-      hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-      
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
       return HAL_TIMEOUT;
     }
   }
-  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
-  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
-  {	  
+
+   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+  {
     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
   }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no tranfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
 
   return HAL_OK;
 }
@@ -581,29 +659,121 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
 /**
   * @brief  Resume the DMA2D Transfer.
   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
-  *                 the configuration information for the DMA2D.  
+  *                 the configuration information for the DMA2D.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
 {
-  /* Check the suspend bit and START bit */
+  /* Check the SUSP and START bits */
   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
   {
-    /* ongoing transfer is suspended :  Change the DMA2D state before resuming*/
+    /* Ongoing transfer is suspended: change the DMA2D state before resuming */
     hdma2d->State = HAL_DMA2D_STATE_BUSY;
   }
 
   /* Resume the DMA2D transfer */
-  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));  
-  
-  return HAL_OK;  
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing ‘0’ has no
+     effect on START bitvalue). */
+  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the DMA2D CLUT Transfer.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  if(LayerIdx == 0U)
+  {
+    /* Enable the background CLUT loading */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  else
+  {
+    /* Enable the foreground CLUT loading */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if(LayerIdx == 0U)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+              ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+
+ /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
-  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
   *                   the configuration information for the DMA2D.
-  * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
   *                   the configuration information for the color look up table.
   * @param  LayerIdx: DMA2D Layer index.
   *                   This parameter can be one of the following values:
@@ -613,90 +783,244 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
 {
   /* Check the parameters */
-  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
-  
+
   /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
-  
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
   /* Configure the CLUT of the background DMA2D layer */
   if(LayerIdx == 0U)
   {
-    /* Write to DMA2D BGCMAR register */
-    hdma2d->Instance->BGCMAR = (uint32_t)CLUTCfg.pCLUT;
-    
-   /* Write background CLUT size and CLUT color mode */
-    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));     
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
 
-    /* Enable the C-LUT Transfer Complete,transfer Error and C-LUT Access Error interrupts */
-    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CAE);
-  
     /* Enable the CLUT loading for the background */
-    hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;  
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
   }
   /* Configure the CLUT of the foreground DMA2D layer */
   else
   {
-    /* Write to DMA2D FGCMAR register */
-    hdma2d->Instance->FGCMAR = (uint32_t)CLUTCfg.pCLUT;
-    
-    /* Write foreground CLUT size and CLUT color mode */
-    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));  
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
 
-    /* Enable the C-LUT Transfer Complete,transfer Error and C-LUT Access Error interrupts */
-    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CAE);
-    
-     /* Enable the CLUT loading for the foreground */
-    hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;   
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+              ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
   }
- 
-  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D CLUT loading.
+  * @param  hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground) 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart  = 0U;
+  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+  /* Abort the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if(LayerIdx == 1)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is aborted */
+  while((*reg & DMA2D_BGPFCCR_START) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D CLUT loading.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart = 0U;
+  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+
+  /* Suspend the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if(LayerIdx == 1U)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is suspended */
+  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
+    && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+  {
+    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((*reg & DMA2D_BGPFCCR_START) != RESET)
+  {
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no tranfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D CLUT loading.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the SUSP and START bits for background or foreground CLUT loading */
+  if(LayerIdx == 0U)
+  {
+    /* Background CLUT loading suspension check */
+    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+      && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+    {
+      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+      hdma2d->State = HAL_DMA2D_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* Foreground CLUT loading suspension check */
+    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+      && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
+    {
+      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+      hdma2d->State = HAL_DMA2D_STATE_BUSY;
+    }
+  }
+
+  /* Resume the CLUT loading */
+  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Polling for transfer complete or CLUT loading.
-  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
-  *                 the configuration information for the DMA2D. 
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
 {
   uint32_t tickstart = 0U;
+  __IO uint32_t isrflags = 0x0U;
 
   /* Polling for DMA2D transfer */
-  if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
   {
    /* Get tick */
    tickstart = HAL_GetTick();
 
     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
     {
-      if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE|DMA2D_FLAG_TE) != RESET))
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
       {
-        if (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
+        if ((isrflags & DMA2D_FLAG_CE) != RESET)
         {
-          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;          
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
         }
-        
-        if (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
+        if ((isrflags & DMA2D_FLAG_TE) != RESET)
         {
-          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;          
-        }        
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
         /* Clear the transfer and configuration error flags */
         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
 
         /* Change DMA2D state */
-        hdma2d->State= HAL_DMA2D_STATE_ERROR;
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
 
         /* Process unlocked */
         __HAL_UNLOCK(hdma2d);
-        
+
         return HAL_ERROR;
       }
       /* Check for the Timeout */
@@ -704,123 +1028,108 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
       {
         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
         {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
           /* Process unlocked */
           __HAL_UNLOCK(hdma2d);
-        
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Polling for CLUT loading (foreground or background) */
+  if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  ||
+      ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+      {
+        if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+        }
+        if ((isrflags & DMA2D_FLAG_CE) != RESET)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != RESET)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
+        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State= HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
           /* Update error code */
           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
 
           /* Change the DMA2D state */
           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-          
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+
           return HAL_TIMEOUT;
         }
-      }        
+      }
     }
   }
-  /* Polling for foreground CLUT loading */
-  if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0U)
-  {
-    /* Get tick */
-    tickstart = HAL_GetTick();
-   
-    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
-    {
-      if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
-      {      
-        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
-        
-        /* Clear the CLUT Access Error flag */
-        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
-        
-        /* Change DMA2D state */
-        hdma2d->State= HAL_DMA2D_STATE_ERROR;
-        
-        return HAL_ERROR;      
-      }      
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Update error code */
-          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-    
-          /* Change the DMA2D state */
-          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-          
-          return HAL_TIMEOUT;
-        }
-      }      
-    }
-  }
-  /* Polling for background CLUT loading */
-  if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != 0U)
-  {
-    /* Get tick */
-    tickstart = HAL_GetTick();
-   
-    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
-    {
-      if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
-      {
-        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
-        
-        /* Clear the CLUT Access Error flag */
-        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
-        
-        /* Change DMA2D state */
-        hdma2d->State= HAL_DMA2D_STATE_ERROR;
-        
-        return HAL_ERROR;      
-      }      
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Update error code */
-          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-    
-          /* Change the DMA2D state */
-          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-          
-          return HAL_TIMEOUT;
-        }
-      }      
-    }
-  }  
-  
+
   /* Clear the transfer complete and CLUT loading flags */
-  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); 
-  
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
+
   /* Change DMA2D state */
   hdma2d->State = HAL_DMA2D_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdma2d);
-  
+
   return HAL_OK;
 }
 /**
-  * @brief  Handles DMA2D interrupt request.
-  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
-  *                 the configuration information for the DMA2D.  
+  * @brief  Handle DMA2D interrupt request.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
   * @retval HAL status
   */
 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
-{    
+{
+  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+  uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+
   /* Transfer Error Interrupt management ***************************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
+  if ((isrflags & DMA2D_FLAG_TE) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
+    if ((crflags & DMA2D_IT_TE) != RESET)
     {
       /* Disable the transfer Error interrupt */
-      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);  
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
 
       /* Update error code */
       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
-    
+
       /* Clear the transfer error flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
 
@@ -828,8 +1137,8 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
       hdma2d->State = HAL_DMA2D_STATE_ERROR;
 
       /* Process Unlocked */
-      __HAL_UNLOCK(hdma2d);       
-      
+      __HAL_UNLOCK(hdma2d);
+
       if(hdma2d->XferErrorCallback != NULL)
       {
         /* Transfer error Callback */
@@ -838,25 +1147,25 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
     }
   }
   /* Configuration Error Interrupt management **********************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
+  if ((isrflags & DMA2D_FLAG_CE) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
+    if ((crflags & DMA2D_IT_CE) != RESET)
     {
       /* Disable the Configuration Error interrupt */
       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
-  
+
       /* Clear the Configuration error flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
 
       /* Update error code */
-      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;    
-    
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+
       /* Change DMA2D state */
       hdma2d->State = HAL_DMA2D_STATE_ERROR;
 
       /* Process Unlocked */
-      __HAL_UNLOCK(hdma2d);       
-      
+      __HAL_UNLOCK(hdma2d);
+
       if(hdma2d->XferErrorCallback != NULL)
       {
         /* Transfer error Callback */
@@ -865,99 +1174,98 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
     }
   }
   /* CLUT access Error Interrupt management ***********************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET)
+  if ((isrflags & DMA2D_FLAG_CAE) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CAE) != RESET)
+    if ((crflags & DMA2D_IT_CAE) != RESET)
     {
       /* Disable the CLUT access error interrupt */
       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
-  
+
       /* Clear the CLUT access error flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
 
       /* Update error code */
-      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;    
-    
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+
       /* Change DMA2D state */
       hdma2d->State = HAL_DMA2D_STATE_ERROR;
 
       /* Process Unlocked */
-      __HAL_UNLOCK(hdma2d);       
-      
+      __HAL_UNLOCK(hdma2d);
+
       if(hdma2d->XferErrorCallback != NULL)
       {
         /* Transfer error Callback */
         hdma2d->XferErrorCallback(hdma2d);
       }
     }
-  }  
+  }
   /* Transfer watermark Interrupt management **********************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TW) != RESET)
+  if ((isrflags & DMA2D_FLAG_TW) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TW) != RESET)
-    { 
+    if ((crflags & DMA2D_IT_TW) != RESET)
+    {
       /* Disable the transfer watermark interrupt */
       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
-  
-      /* Clear the transfer watermark flag */  
+
+      /* Clear the transfer watermark flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
 
       /* Transfer watermark Callback */
       HAL_DMA2D_LineEventCallback(hdma2d);
     }
-  }  
+  }
   /* Transfer Complete Interrupt management ************************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
+  if ((isrflags & DMA2D_FLAG_TC) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
-    { 
+    if ((crflags & DMA2D_IT_TC) != RESET)
+    {
       /* Disable the transfer complete interrupt */
       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
-  
-      /* Clear the transfer complete flag */  
+
+      /* Clear the transfer complete flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
 
       /* Update error code */
-      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    
-    
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
       /* Change DMA2D state */
       hdma2d->State = HAL_DMA2D_STATE_READY;
-    
+
       /* Process Unlocked */
-      __HAL_UNLOCK(hdma2d);       
-      
+      __HAL_UNLOCK(hdma2d);
+
       if(hdma2d->XferCpltCallback != NULL)
       {
         /* Transfer complete Callback */
         hdma2d->XferCpltCallback(hdma2d);
-      }         
+      }
     }
   }
   /* CLUT Transfer Complete Interrupt management ******************************/
-  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) != RESET)
+  if ((isrflags & DMA2D_FLAG_CTC) != RESET)
   {
-    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CTC) != RESET)
-    { 
+    if ((crflags & DMA2D_IT_CTC) != RESET)
+    {
       /* Disable the CLUT transfer complete interrupt */
       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
-  
-      /* Clear the CLUT transfer complete flag */  
+
+      /* Clear the CLUT transfer complete flag */
       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
 
       /* Update error code */
-      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    
-    
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
       /* Change DMA2D state */
       hdma2d->State = HAL_DMA2D_STATE_READY;
-    
+
       /* Process Unlocked */
-      __HAL_UNLOCK(hdma2d);       
-      
+      __HAL_UNLOCK(hdma2d);
+
       /* CLUT Transfer complete Callback */
-      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);         
+      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
     }
-  }  
-  
+  }
 }
 
 /**
@@ -970,9 +1278,9 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdma2d);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DMA2D_LineEventCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_LineEventCallback can be implemented in the user file.
    */
 }
 
@@ -986,9 +1294,9 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdma2d);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DMA2D_CLUTLoadingCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
    */
 }
 
@@ -996,23 +1304,24 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
   * @}
   */
 
-/** @defgroup DMA2D_Group3 Peripheral Control functions
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
  *  @brief    Peripheral Control functions 
  *
-@verbatim   
+@verbatim
  ===============================================================================
                     ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure the DMA2D foreground or/and background parameters.
+      (+) Configure the DMA2D foreground or background layer parameters.
       (+) Configure the DMA2D CLUT transfer.
-      (+) Enable DMA2D CLUT.
-      (+) Disable DMA2D CLUT.
       (+) Configure the line watermark
+      (+) Configure the dead time value.
+      (+) Enable or disable the dead time value functionality.
 
 @endverbatim
   * @{
   */
+
 /**
   * @brief  Configure the DMA2D Layer according to the specified
   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
@@ -1024,17 +1333,15 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{ 
+{
   DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
-  
-  uint32_t tmp = 0U;
+  uint32_t regValue = 0U;
 
   /* Check the parameters */
-  assert_param(IS_DMA2D_LAYER(LayerIdx));  
-  assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));  
-  
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
   if(hdma2d->Init.Mode != DMA2D_R2M)
-  {  
+  {
     assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
     if(hdma2d->Init.Mode != DMA2D_M2M)
     {
@@ -1044,116 +1351,66 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
 
   /* Process locked */
   __HAL_LOCK(hdma2d);
-  
+
   /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY;  
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* DMA2D BGPFCR register configuration -----------------------------------*/
+  /* Prepare the value to be written to the BGPFCCR register */
+
+  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+  {
+    regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+  }
+  else
+  {
+    regValue =  pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
+  }
   
   /* Configure the background DMA2D layer */
-  if(LayerIdx == 0U)
+  if(LayerIdx == 0)
   {
-    /* DMA2D BGPFCR register configuration -----------------------------------*/
-    /* Get the BGPFCCR register value */
-    tmp = hdma2d->Instance->BGPFCCR;
-    
-    /* Clear Input color mode, alpha value and alpha mode bits */
-    tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); 
-    
-    if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
+    /* Write DMA2D BGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+
+    /* DMA2D BGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D BGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
     {
-      /* Prepare the value to be wrote to the BGPFCCR register */
-      tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | ((pLayerCfg->InputAlpha) & 0xFF000000U));
+      WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
     }
-    else
-    {
-      /* Prepare the value to be wrote to the BGPFCCR register */
-      tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | (pLayerCfg->InputAlpha << 24U));
-    }
-    
-    /* Write to DMA2D BGPFCCR register */
-    hdma2d->Instance->BGPFCCR = tmp; 
-    
-    /* DMA2D BGOR register configuration -------------------------------------*/  
-    /* Get the BGOR register value */
-    tmp = hdma2d->Instance->BGOR;
-    
-    /* Clear colors bits */
-    tmp &= (uint32_t)~DMA2D_BGOR_LO; 
-    
-    /* Prepare the value to be wrote to the BGOR register */
-    tmp |= pLayerCfg->InputOffset;
-    
-    /* Write to DMA2D BGOR register */
-    hdma2d->Instance->BGOR = tmp;
-    
-    if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
-    {
-      /* Prepare the value to be wrote to the BGCOLR register */
-      tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFFU);
-    
-      /* Write to DMA2D BGCOLR register */
-      hdma2d->Instance->BGCOLR = tmp;
-    }    
   }
   /* Configure the foreground DMA2D layer */
   else
   {
-    /* DMA2D FGPFCR register configuration -----------------------------------*/
-    /* Get the FGPFCCR register value */
-    tmp = hdma2d->Instance->FGPFCCR;
-    
-    /* Clear Input color mode, alpha value and alpha mode bits */
-    tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); 
-    
-    if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
+     /* Write DMA2D FGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+
+    /* DMA2D FGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D FGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
     {
-      /* Prepare the value to be wrote to the FGPFCCR register */
-      tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | ((pLayerCfg->InputAlpha) & 0xFF000000U));
+      WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
     }
-    else
-    {
-      /* Prepare the value to be wrote to the FGPFCCR register */
-      tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | (pLayerCfg->InputAlpha << 24U));
-    }
-    
-    /* Write to DMA2D FGPFCCR register */
-    hdma2d->Instance->FGPFCCR = tmp; 
-    
-    /* DMA2D FGOR register configuration -------------------------------------*/  
-    /* Get the FGOR register value */
-    tmp = hdma2d->Instance->FGOR;
-    
-    /* Clear colors bits */
-    tmp &= (uint32_t)~DMA2D_FGOR_LO; 
-    
-    /* Prepare the value to be wrote to the FGOR register */
-    tmp |= pLayerCfg->InputOffset;
-    
-    /* Write to DMA2D FGOR register */
-    hdma2d->Instance->FGOR = tmp;
-   
-    if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
-    {
-      /* Prepare the value to be wrote to the FGCOLR register */
-      tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFFU);
-    
-      /* Write to DMA2D FGCOLR register */
-      hdma2d->Instance->FGCOLR = tmp;
-    }   
-  }    
+  }
   /* Initialize the DMA2D state*/
-  hdma2d->State  = HAL_DMA2D_STATE_READY;
-  
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
   /* Process unlocked */
-  __HAL_UNLOCK(hdma2d);  
-  
+  __HAL_UNLOCK(hdma2d);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Configure the DMA2D CLUT Transfer.
-  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
+  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains
   *                   the configuration information for the DMA2D.
-  * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
   *                   the configuration information for the color look up table.
   * @param  LayerIdx: DMA2D Layer index.
   *                   This parameter can be one of the following values:
@@ -1163,152 +1420,176 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
 {
   /* Check the parameters */
-  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma2d);
-  
+
   /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
-  
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
   /* Configure the CLUT of the background DMA2D layer */
   if(LayerIdx == 0U)
   {
-    /* Write to DMA2D BGCMAR register */
-    hdma2d->Instance->BGCMAR = (uint32_t)CLUTCfg.pCLUT;
-    
-   /* Write background CLUT size and CLUT color mode */
-    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));     
-  }
-  /* Configure the CLUT of the foreground DMA2D layer */
-  else
-  {
-    /* Write to DMA2D FGCMAR register */
-    hdma2d->Instance->FGCMAR = (uint32_t)CLUTCfg.pCLUT;
-    
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+              ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+   /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
     /* Write foreground CLUT size and CLUT color mode */
-    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));  
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+              ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
   }
 
-  /* Set the DMA2D state to Ready*/
-  hdma2d->State  = HAL_DMA2D_STATE_READY;
-  
+  /* Set the DMA2D state to Ready */
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
   /* Process unlocked */
-  __HAL_UNLOCK(hdma2d); 
-  
+  __HAL_UNLOCK(hdma2d);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Enable the DMA2D CLUT Transfer.
-  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
-  *                   the configuration information for the DMA2D.
-  * @param  LayerIdx: DMA2D Layer index.
-  *                   This parameter can be one of the following values:
-  *                   0(background) / 1(foreground)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA2D_LAYER(LayerIdx));
-  
-  /* Process locked */
-  __HAL_LOCK(hdma2d);
-  
-  /* Change DMA2D peripheral state */
-  hdma2d->State = HAL_DMA2D_STATE_BUSY;
-  
-  if(LayerIdx == 0U)
-  {
-    /* Enable the CLUT loading for the background */
-    hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
-  }
-  else
-  {
-    /* Enable the CLUT loading for the foreground */
-    hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the DMA2D CLUT Transfer.
-  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
-  *                   the configuration information for the DMA2D.
-  * @param  LayerIdx: DMA2D Layer index.
-  *                   This parameter can be one of the following values:
-  *                   0(background) / 1(foreground)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA2D_LAYER(LayerIdx));
-  
-  if(LayerIdx == 0U)
-  {
-    /* Disable the CLUT loading for the background */
-    hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
-  }
-  else
-  {
-    /* Disable the CLUT loading for the foreground */
-    hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
-  } 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Define the configuration of the line watermark .
-  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  * @brief  Configure the line watermark.
+  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
   *                 the configuration information for the DMA2D.
-  * @param  Line:   Line Watermark configuration.
+  * @param  Line:   Line Watermark configuration (maximum 16-bit long value expected).
+  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+  * @note   The transfer watermark interrupt is disabled once it has occurred.
   * @retval HAL status
   */
 
 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
 {
   /* Check the parameters */
-  assert_param(IS_DMA2D_LineWatermark(Line));
-  
-  /* Process locked */
+  assert_param(IS_DMA2D_LINEWATERMARK(Line));
+
+  if (Line > DMA2D_LWR_LW)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdma2d);
+
+    /* Change DMA2D peripheral state */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+    /* Sets the Line watermark configuration */
+    WRITE_REG(hdma2d->Instance->LWR, Line);
+
+    /* Enable the Line interrupt */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+
+    /* Initialize the DMA2D state */
+    hdma2d->State = HAL_DMA2D_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma2d);
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief Enable DMA2D dead time feature.
+  * @param hdma2d: DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
   __HAL_LOCK(hdma2d);
-  
-  /* Change DMA2D peripheral state */
+
   hdma2d->State = HAL_DMA2D_STATE_BUSY;
 
-  /* Sets the Line watermark configuration */
-  DMA2D->LWR = (uint32_t)Line;
-  
-  /* Initialize the DMA2D state*/
+  /* Set DMA2D_AMTCR EN bit */
+  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
   hdma2d->State = HAL_DMA2D_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdma2d);  
-  
-  return HAL_OK;  
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable DMA2D dead time feature.
+  * @param hdma2d: DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Clear DMA2D_AMTCR EN bit */
+  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure dead time.
+  * @note The dead time value represents the guaranteed minimum number of cycles between
+  *       two consecutive transactions on the AHB bus.
+  * @param hdma2d: DMA2D handle.
+  * @param DeadTime: dead time value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR DT field */
+  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup DMA2D_Group4 Peripheral State functions
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
  *  @brief    Peripheral State functions 
  *
-@verbatim   
+@verbatim
  ===============================================================================
                   ##### Peripheral State and Errors functions #####
  ===============================================================================  
     [..]
     This subsection provides functions allowing to :
-      (+) Check the DMA2D state
-      (+) Get error code  
+      (+) Get the DMA2D state
+      (+) Get the DMA2D error code
 
 @endverbatim
   * @{
@@ -1317,11 +1598,11 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32
 /**
   * @brief  Return the DMA2D state
   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
-  *                 the configuration information for the DMA2D.  
+  *                 the configuration information for the DMA2D.
   * @retval HAL state
   */
 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
-{  
+{
   return hdma2d->State;
 }
 
@@ -1336,15 +1617,22 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
   return hdma2d->ErrorCode;
 }
 
+/**
+  * @}
+  */
+  
 /**
   * @}
   */
 
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
 
 /**
-  * @brief  Set the DMA2D Transfer parameter.
-  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA2D.  
+  * @brief  Set the DMA2D transfer parameters.
+  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA2D.
   * @param  pdata:      The source memory Buffer address
   * @param  DstAddress: The destination memory Buffer address
   * @param  Width:      The width of data to be transferred from source to destination.
@@ -1352,68 +1640,66 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
   * @retval HAL status
   */
 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{  
+{
   uint32_t tmp = 0U;
   uint32_t tmp1 = 0U;
   uint32_t tmp2 = 0U;
   uint32_t tmp3 = 0U;
   uint32_t tmp4 = 0U;
-  
-  tmp = Width << 16U;
-  
+
   /* Configure DMA2D data size */
-  hdma2d->Instance->NLR = (Height | tmp);
-  
+  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
+
   /* Configure DMA2D destination address */
-  hdma2d->Instance->OMAR = DstAddress;
- 
+  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+
   /* Register to memory DMA2D mode selected */
   if (hdma2d->Init.Mode == DMA2D_R2M)
-  {    
+  {
     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
     tmp2 = pdata & DMA2D_OCOLR_RED_1;
     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
-    
-    /* Prepare the value to be wrote to the OCOLR register according to the color mode */
-    if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
+
+    /* Prepare the value to be written to the OCOLR register according to the color mode */
+    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
     {
       tmp = (tmp3 | tmp2 | tmp1| tmp4);
     }
-    else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
     {
-      tmp = (tmp3 | tmp2 | tmp4);  
+      tmp = (tmp3 | tmp2 | tmp4);
     }
-    else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
     {
       tmp2 = (tmp2 >> 19U);
       tmp3 = (tmp3 >> 10U);
       tmp4 = (tmp4 >> 3U);
-      tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); 
+      tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
     }
-    else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
-    { 
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+    {
       tmp1 = (tmp1 >> 31U);
       tmp2 = (tmp2 >> 19U);
       tmp3 = (tmp3 >> 11U);
-      tmp4 = (tmp4 >> 3U);      
-      tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);    
-    } 
-    else /* DMA2D_CMode = DMA2D_ARGB4444 */
+      tmp4 = (tmp4 >> 3U);
+      tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
+    }
+    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
     {
       tmp1 = (tmp1 >> 28U);
       tmp2 = (tmp2 >> 20U);
       tmp3 = (tmp3 >> 12U);
       tmp4 = (tmp4 >> 4U);
       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
-    }    
+    }
     /* Write to DMA2D OCOLR register */
-    hdma2d->Instance->OCOLR = tmp;
-  } 
+    WRITE_REG(hdma2d->Instance->OCOLR, tmp);
+  }
   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
   {
     /* Configure DMA2D source address */
-    hdma2d->Instance->FGMAR = pdata;
+    WRITE_REG(hdma2d->Instance->FGMAR, pdata);
   }
 }
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h
index 39ee30582d..4aa1388296 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma2d.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DMA2D HAL module.
   ******************************************************************************
   * @attention
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_DMA2D_H
@@ -52,7 +52,7 @@
   * @{
   */
 
-/** @defgroup DMA2D DMA2D
+/** @addtogroup DMA2D DMA2D
   * @brief DMA2D HAL module driver
   * @{
   */
@@ -61,7 +61,7 @@
 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
   * @{
   */
-#define MAX_DMA2D_LAYER  2
+#define MAX_DMA2D_LAYER  2U
 
 /** 
   * @brief DMA2D color Structure definition
@@ -85,10 +85,10 @@ typedef struct
 {
   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
 
-  uint32_t CLUTColorMode;           /*!< configures the DMA2D CLUT color mode.
-                                         This parameter can be one value of @ref DMA2D_CLUT_CM */
+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */
 
-  uint32_t Size;                    /*!< configures the DMA2D CLUT size. 
+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
 } DMA2D_CLUTCfgTypeDef;
 
@@ -97,14 +97,15 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t             Mode;               /*!< configures the DMA2D transfer mode.
-                                                This parameter can be one value of @ref DMA2D_Mode */
+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode. */
 
-  uint32_t             ColorMode;          /*!< configures the color format of the output image.
-                                                This parameter can be one value of @ref DMA2D_Color_Mode */
+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value.
+                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 
-  uint32_t             OutputOffset;       /*!< Specifies the Offset value. 
-                                                This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0x3FFF. */ 
 } DMA2D_InitTypeDef;
 
 /** 
@@ -112,20 +113,24 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t             InputOffset;       /*!< configures the DMA2D foreground offset.
-                                               This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0x3FFF. */
+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 
-  uint32_t             InputColorMode;    /*!< configures the DMA2D foreground color mode . 
-                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode */
+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode. 
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
 
-  uint32_t             AlphaMode;         /*!< configures the DMA2D foreground alpha mode. 
-                                               This parameter can be one value of @ref DMA2D_ALPHA_MODE */
-
-  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode. 
-                                               This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFFU 
-                                               in case of A8 or A4 color mode (ARGB). 
-                                               Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */
 
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
+                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
+                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 
+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+                                               - InputAlpha[16:23] is the red value RED[0:7]
+                                               - InputAlpha[8:15] is the green value GREEN[0:7]
+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+  
 } DMA2D_LayerCfgTypeDef;
 
 /** 
@@ -135,32 +140,32 @@ typedef enum
 {
   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing              */
+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
 }HAL_DMA2D_StateTypeDef;
 
-/** 
+/**
   * @brief  DMA2D handle Structure definition
   */
 typedef struct __DMA2D_HandleTypeDef
 {
-  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D Register base address       */
+  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
 
-  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters    */ 
+  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
 
-  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback  */
+  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
 
-  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback     */
+  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
 
-  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */  
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters                    */
 
-  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D Lock                        */  
+  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
 
-  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state              */
+  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
 
-  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D Error code                  */  
+  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
 } DMA2D_HandleTypeDef;
 /**
   * @}
@@ -174,11 +179,11 @@ typedef struct __DMA2D_HandleTypeDef
 /** @defgroup DMA2D_Error_Code DMA2D Error Code
   * @{
   */
-#define HAL_DMA2D_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error             */
-#define HAL_DMA2D_ERROR_TE        ((uint32_t)0x00000001U)    /*!< Transfer error       */
-#define HAL_DMA2D_ERROR_CE        ((uint32_t)0x00000002U)    /*!< Configuration error  */
-#define HAL_DMA2D_ERROR_CAE       ((uint32_t)0x00000004U)    /*!< CLUT access error    */
-#define HAL_DMA2D_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error        */
+#define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */
+#define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */
+#define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */
 /**
   * @}
   */
@@ -186,127 +191,94 @@ typedef struct __DMA2D_HandleTypeDef
 /** @defgroup DMA2D_Mode DMA2D Mode 
   * @{
   */
-#define DMA2D_M2M                            ((uint32_t)0x00000000U)             /*!< DMA2D memory to memory transfer mode */
-#define DMA2D_M2M_PFC                        ((uint32_t)0x00010000U)             /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000U)             /*!< DMA2D memory to memory with blending transfer mode */
-#define DMA2D_R2M                            ((uint32_t)0x00030000U)             /*!< DMA2D register to memory transfer mode */
+#define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode                              */
+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode                */
+#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode                            */
 /**
   * @}
   */
 
-/** @defgroup DMA2D_Color_Mode DMA2D Color Mode 
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 
   * @{
   */
-#define DMA2D_ARGB8888                       ((uint32_t)0x00000000U)             /*!< ARGB8888 DMA2D color mode */
-#define DMA2D_RGB888                         ((uint32_t)0x00000001U)             /*!< RGB888 DMA2D color mode   */
-#define DMA2D_RGB565                         ((uint32_t)0x00000002U)             /*!< RGB565 DMA2D color mode   */
-#define DMA2D_ARGB1555                       ((uint32_t)0x00000003U)             /*!< ARGB1555 DMA2D color mode */
-#define DMA2D_ARGB4444                       ((uint32_t)0x00000004U)             /*!< ARGB4444 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
 /**
   * @}
   */
 
-/** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
-  * @{
-  */
-#define COLOR_VALUE             ((uint32_t)0x000000FFU)                          /*!< color value mask */
-/**
-  * @}
-  */    
-
-/** @defgroup DMA2D_SIZE DMA2D SIZE 
-  * @{
-  */
-#define DMA2D_PIXEL          (DMA2D_NLR_PL >> 16U)                              /*!< DMA2D pixel per line */
-#define DMA2D_LINE           DMA2D_NLR_NL                                       /*!< DMA2D number of line */
-/**
-  * @}
-  */
-
-/** @defgroup DMA2D_Offset DMA2D Offset 
-  * @{
-  */
-#define DMA2D_OFFSET      DMA2D_FGOR_LO            /*!< Line Offset */
-/**
-  * @}
-  */ 
-
 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
   * @{
   */
-#define CM_ARGB8888        ((uint32_t)0x00000000U)                               /*!< ARGB8888 color mode */
-#define CM_RGB888          ((uint32_t)0x00000001U)                               /*!< RGB888 color mode */
-#define CM_RGB565          ((uint32_t)0x00000002U)                               /*!< RGB565 color mode */
-#define CM_ARGB1555        ((uint32_t)0x00000003U)                               /*!< ARGB1555 color mode */
-#define CM_ARGB4444        ((uint32_t)0x00000004U)                               /*!< ARGB4444 color mode */
-#define CM_L8              ((uint32_t)0x00000005U)                               /*!< L8 color mode */
-#define CM_AL44            ((uint32_t)0x00000006U)                               /*!< AL44 color mode */
-#define CM_AL88            ((uint32_t)0x00000007U)                               /*!< AL88 color mode */
-#define CM_L4              ((uint32_t)0x00000008U)                               /*!< L4 color mode */
-#define CM_A8              ((uint32_t)0x00000009U)                               /*!< A8 color mode */
-#define CM_A4              ((uint32_t)0x0000000AU)                               /*!< A4 color mode */
+#define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */
+#define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */
+#define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */
+#define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */
+#define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */
+#define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */
+#define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */
+#define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */
 /**
   * @}
   */
 
-/** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
   * @{
   */
-#define DMA2D_NO_MODIF_ALPHA       ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
-#define DMA2D_REPLACE_ALPHA        ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
-#define DMA2D_COMBINE_ALPHA        ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
-                                                                with original alpha channel value                              */
+#define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value                     */
+#define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
+                                                                with original alpha channel value                                */
 /**
   * @}
-  */    
+  */ 
 
-/** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
   * @{
   */
-#define DMA2D_CCM_ARGB8888    ((uint32_t)0x00000000U)    /*!< ARGB8888 DMA2D C-LUT color mode */
-#define DMA2D_CCM_RGB888      ((uint32_t)0x00000001U)    /*!< RGB888 DMA2D C-LUT color mode   */
+#define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */
 /**
   * @}
   */
 
-/** @defgroup DMA2D_Size_Clut DMA2D Size Clut
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
   * @{
   */
-#define DMA2D_CLUT_SIZE    (DMA2D_FGPFCCR_CS >> 8U)    /*!< DMA2D C-LUT size */
+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt    */
+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt      */
+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt     */
+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt      */
+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt         */
 /**
   * @}
   */
 
-/** @defgroup DMA2D_DeadTime DMA2D DeadTime 
+/** @defgroup DMA2D_Flags DMA2D Flags
   * @{
   */
-#define LINE_WATERMARK            DMA2D_LWR_LW
+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag    */
+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag         */
 /**
   * @}
   */
-
-/** @defgroup DMA2D_Interrupts DMA2D Interrupts 
+  
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
   * @{
   */
-#define DMA2D_IT_CE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
-#define DMA2D_IT_CTC            DMA2D_CR_CTCIE   /*!< C-LUT Transfer Complete Interrupt */
-#define DMA2D_IT_CAE            DMA2D_CR_CAEIE   /*!< C-LUT Access Error Interrupt */
-#define DMA2D_IT_TW             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
-#define DMA2D_IT_TC             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
-#define DMA2D_IT_TE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
-/**
-  * @}
-  */
-
-/** @defgroup DMA2D_Flag DMA2D Flag 
-  * @{
-  */
-#define DMA2D_FLAG_CE          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
-#define DMA2D_FLAG_CTC         DMA2D_ISR_CTCIF    /*!< C-LUT Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_CAE         DMA2D_ISR_CAEIF    /*!< C-LUT Access Error Interrupt Flag */
-#define DMA2D_FLAG_TW          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_FLAG_TC          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_TE          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
 /**
   * @}
   */
@@ -314,7 +286,7 @@ typedef struct __DMA2D_HandleTypeDef
 /**
   * @}
   */
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
   * @{
   */
@@ -332,16 +304,15 @@ typedef struct __DMA2D_HandleTypeDef
   */
 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
 
-
 /* Interrupt & Flag management */
 /**
   * @brief  Get the DMA2D pending flags.
   * @param  __HANDLE__: DMA2D handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __FLAG__: flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg DMA2D_FLAG_CE:  Configuration error flag
-  *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
-  *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
   *            @arg DMA2D_FLAG_TE:  Transfer error flag   
@@ -350,28 +321,28 @@ typedef struct __DMA2D_HandleTypeDef
 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
 
 /**
-  * @brief  Clears the DMA2D pending flags.
+  * @brief  Clear the DMA2D pending flags.
   * @param  __HANDLE__: DMA2D handle
   * @param  __FLAG__: specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA2D_FLAG_CE:  Configuration error flag
-  *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
-  *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
-  *            @arg DMA2D_FLAG_TE:  Transfer error flag    
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
   * @retval None
   */
 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
 
 /**
-  * @brief  Enables the specified DMA2D interrupts.
+  * @brief  Enable the specified DMA2D interrupts.
   * @param  __HANDLE__: DMA2D handle
-  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. 
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
   *          This parameter can be any combination of the following values:
   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
-  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
-  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
@@ -380,13 +351,13 @@ typedef struct __DMA2D_HandleTypeDef
 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 
 /**
-  * @brief  Disables the specified DMA2D interrupts.
+  * @brief  Disable the specified DMA2D interrupts.
   * @param  __HANDLE__: DMA2D handle
-  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. 
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
   *          This parameter can be any combination of the following values:
   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
-  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
-  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
@@ -395,32 +366,46 @@ typedef struct __DMA2D_HandleTypeDef
 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 
 /**
-  * @brief  Checks whether the specified DMA2D interrupt has occurred or not.
+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
   * @param  __HANDLE__: DMA2D handle
   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
-  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
-  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
-  * @retval The state of INTERRUPT.
+  * @retval The state of INTERRUPT source.
   */
 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
 /**
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/  
-/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
   * @{
   */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
 /* Initialization and de-initialization functions *******************************/
-HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
 
 /* IO operation functions *******************************************************/
 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
@@ -430,58 +415,108 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
 
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
 /* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef  HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef  HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef  HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef  HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef  HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
 
 /* Peripheral State functions ***************************************************/
 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Types DMA2D Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -------------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Defines DMA2D Private Defines
-  * @{
-  */
 
 /**
   * @}
   */
 
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Variables DMA2D Private Variables
-  * @{
-  */
-
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+  
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
   * @{
   */
 
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 
+  * @{
+  */
+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW          /*!< DMA2D maximum line watermark */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+  * @{
+  */
+#define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+  * @{
+  */
+#define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+  * @{
+  */
+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA2D_Size DMA2D Size
+  * @{
+  */
+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */
+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+  * @{
+  */
+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D CLUT size */
+/**
+  * @}
+  */
+
 /**
   * @}
   */ 
@@ -490,53 +525,42 @@ uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
   * @{
   */
-#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= MAX_DMA2D_LAYER)
+#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)
 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888)   || \
-                                               ((MODE_ARGB) == DMA2D_RGB565)   || ((MODE_ARGB) == DMA2D_ARGB1555) || \
-                                               ((MODE_ARGB) == DMA2D_ARGB4444))
-#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= COLOR_VALUE)
+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888)   || \
-                                               ((INPUT_CM) == CM_RGB565)   || ((INPUT_CM) == CM_ARGB1555) || \
-                                               ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8)       || \
-                                               ((INPUT_CM) == CM_AL44)     || ((INPUT_CM) == CM_AL88)     || \
-                                               ((INPUT_CM) == CM_L4)       || ((INPUT_CM) == CM_A8)       || \
-                                               ((INPUT_CM) == CM_A4))
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A4))
 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
-#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
-/**
-  * @}
-  */
-
-/* Private functions prototypes ---------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
-  * @{
-  */
-
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c
index 4cd72142fb..472e5be6b4 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:
@@ -118,39 +118,46 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  /* Process Locked */
-  __HAL_LOCK(hdma);
-
-  /* Current memory buffer used is Memory 0 */
-  if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
-  {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
-  }
-  /* Current memory buffer used is Memory 1 */
-  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
-  {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
-  }
-
-   /* Check the parameters */
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);  
-
-  /* Enable the double buffer mode */
-  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-
-  /* Configure DMA Stream destination address */
-  hdma->Instance->M1AR = SecondMemAddress;
-
-  /* Configure the source, destination address and the data length */
-  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+    
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY; 
+      
+      /* Enable the double buffer mode */
+      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+      
+      /* Configure DMA Stream destination address */
+      hdma->Instance->M1AR = SecondMemAddress;
+      
+      /* Configure the source, destination address and the data length */
+      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+      
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_BUSY;
+    }
+  }
+  return status;
 }
 
 /**
@@ -165,54 +172,73 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  /* Process Locked */
-  __HAL_LOCK(hdma);
-
-  /* Current memory buffer used is Memory 0 */
-  if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
-  {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
-  }
-  /* Current memory buffer used is Memory 1 */
-  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
-  {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
-  }
-
+  HAL_StatusTypeDef status = HAL_OK;
+  
   /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Check callback functions */
+  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Enable the Double buffer mode */
+    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M1AR = SecondMemAddress;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+    
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
 
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);  
-
-  /* Enable the Double buffer mode */
-  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-
-  /* Configure DMA Stream destination address */
-  hdma->Instance->M1AR = SecondMemAddress;
-
-  /* Configure the source, destination address and the data length */
-  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
-
-  /* Enable the transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
-  /* Enable the Half transfer interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
-  /* Enable the fifo Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);  
-
-  /* Enable the direct mode Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); 
-
-  /* Enable the peripheral */
-  __HAL_DMA_ENABLE(hdma); 
-
-  return HAL_OK; 
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma); 
+  }
+  else
+  {     
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }  
+  return status; 
 }
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h
index 0261217f91..ea11a092d8 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
@@ -66,7 +66,7 @@
 typedef enum
 {
   MEMORY0      = 0x00U,    /*!< Memory 0     */
-  MEMORY1      = 0x01U    /*!< Memory 1     */
+  MEMORY1      = 0x01U     /*!< Memory 1     */
 }HAL_DMA_MemoryTypeDef;
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c
index be8dcb4395..21338a894e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dsi.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   DSI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the DSI peripheral:
@@ -329,61 +329,61 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A
   /* Store active errors to the handle */
   hdsi->ErrorMsk = ActiveErrors;
   
-  if(ActiveErrors & HAL_DSI_ERROR_ACK)
+  if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_PHY)
+  if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_TX)
+  if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_RX)
+  if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_ECC)
+  if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_CRC)
+  if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_PSE)
+  if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_EOT)
+  if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_OVF)
+  if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
   }
   
-  if(ActiveErrors & HAL_DSI_ERROR_GEN)
+  if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
   {
     /* Enable the interrupt generation on selected errors */
     hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
@@ -486,52 +486,52 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
     ErrorStatus1 = hdsi->Instance->ISR[1U];
     ErrorStatus1 &= hdsi->Instance->IER[1U];
     
-    if(ErrorStatus0 & DSI_ERROR_ACK_MASK)
+    if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
     }
     
-    if(ErrorStatus0 & DSI_ERROR_PHY_MASK)
+    if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_TX_MASK)
+    if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_RX_MASK)
+    if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_ECC_MASK)
+    if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_CRC_MASK)
+    if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_PSE_MASK)
+    if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_EOT_MASK)
+    if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_OVF_MASK)
+    if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
     }
     
-    if(ErrorStatus1 & DSI_ERROR_GEN_MASK)
+    if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
     {
       hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
     }
@@ -1266,17 +1266,17 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
     if(uicounter == 0x00U)
     {
       hdsi->Instance->GPDR=(Param1 | \
-                            ((*(ParametersTable+uicounter))<<8U) | \
-                            ((*(ParametersTable+uicounter+1U))<<16U) | \
-                            ((*(ParametersTable+uicounter+2U))<<24U));
-      uicounter += 3U;
+                            ((uint32_t)(*(ParametersTable + uicounter)) << 8U) | \
+                            ((uint32_t)(*(ParametersTable + uicounter+1U))<<16U) | \
+                            ((uint32_t)(*(ParametersTable + uicounter+2U))<<24U));
+      uicounter+=3U;
     }
     else
     {
-      hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \
-                            ((*(ParametersTable+uicounter+1U))<<8U) | \
-                            ((*(ParametersTable+uicounter+2U))<<16U) | \
-                            ((*(ParametersTable+uicounter+3U))<<24U));
+      hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \
+                            ((uint32_t)(*(ParametersTable + uicounter+1U)) << 8U) | \
+                            ((uint32_t)(*(ParametersTable + uicounter+2U)) << 16U) | \
+                            ((uint32_t)(*(ParametersTable + uicounter+3U)) << 24U));
       uicounter+=4U;
     }
   }
@@ -1346,6 +1346,13 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
   {
     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
   }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+      
+    return HAL_ERROR;    
+  }
   
   /* Get tick */ 
   tickstart = HAL_GetTick();
@@ -1837,7 +1844,7 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
   
   /* Activate/Disactivate additional current path on all lanes */
   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
-  hdsi->Instance->WPCR[1U] |= State<<12U;
+  hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
   
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
@@ -1873,19 +1880,19 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
     {
       /* Swap pins on clock lane */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
-      hdsi->Instance->WPCR[0U] |= (State<<6U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
     }
     else if(Lane == DSI_DATA_LANE0)
     {
       /* Swap pins on data lane 0 */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
-      hdsi->Instance->WPCR[0U] |= (State<<7U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
     }
     else if(Lane == DSI_DATA_LANE1)
     {
       /* Swap pins on data lane 1 */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
-      hdsi->Instance->WPCR[0U] |= (State<<8U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
     }
     break;
   case DSI_INVERT_HS_SIGNAL:
@@ -1893,19 +1900,19 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
     {
       /* Invert HS signal on clock lane */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
-      hdsi->Instance->WPCR[0U] |= (State<<9U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
     }
     else if(Lane == DSI_DATA_LANE0)
     {
       /* Invert HS signal on data lane 0 */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
-      hdsi->Instance->WPCR[0U] |= (State<<10U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
     }
     else if(Lane == DSI_DATA_LANE1)
     {
       /* Invert HS signal on data lane 1 */
       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
-      hdsi->Instance->WPCR[0U] |= (State<<11U);
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
     }
     break;
   default:
@@ -1942,7 +1949,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_TCLK_POST:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
-    hdsi->Instance->WPCR[0U] |= (State<<27U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
     
     if(State)
     {
@@ -1955,7 +1962,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_TLPX_CLK:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
-    hdsi->Instance->WPCR[0U] |= (State<<26U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
     
     if(State)
     {
@@ -1968,7 +1975,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_THS_EXIT:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
-    hdsi->Instance->WPCR[0U] |= (State<<25U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
     
     if(State)
     {
@@ -1981,7 +1988,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_TLPX_DATA:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
-    hdsi->Instance->WPCR[0U] |= (State<<24U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
     
     if(State)
     {
@@ -1994,7 +2001,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_THS_ZERO:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
-    hdsi->Instance->WPCR[0U] |= (State<<23U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
     
     if(State)
     {
@@ -2007,7 +2014,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_THS_TRAIL:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
-    hdsi->Instance->WPCR[0U] |= (State<<22U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
     
     if(State)
     {
@@ -2020,7 +2027,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_THS_PREPARE:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
-    hdsi->Instance->WPCR[0U] |= (State<<21U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
     
     if(State)
     {
@@ -2033,7 +2040,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_TCLK_ZERO:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
-    hdsi->Instance->WPCR[0U] |= (State<<20U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
     
     if(State)
     {
@@ -2046,7 +2053,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
   case DSI_TCLK_PREPARE:
     /* Enable/Disable custom timing setting */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
-    hdsi->Instance->WPCR[0U] |= (State<<19U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
     
     if(State)
     {
@@ -2088,13 +2095,13 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane
   {
     /* Force/Unforce the Clock Lane in TX Stop Mode */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
-    hdsi->Instance->WPCR[0U] |= (State<<12U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
   }
   else if(Lane == DSI_DATA_LANES)
   {
     /* Force/Unforce the Data Lanes in TX Stop Mode */
     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
-    hdsi->Instance->WPCR[0U] |= (State<<13U);
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
   }
   
   /* Process unlocked */
@@ -2120,7 +2127,7 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta
   
   /* Force/Unforce LP Receiver in Low-Power Mode */
   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
-  hdsi->Instance->WPCR[1U] |= State<<22U;
+  hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
   
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
@@ -2145,7 +2152,7 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional
   
   /* Force Data Lanes in RX Mode */
   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
-  hdsi->Instance->WPCR[0U] |= State<<16U;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
   
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
@@ -2170,7 +2177,7 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S
   
   /* Enable/Disable pull-down on lanes */
   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
-  hdsi->Instance->WPCR[0U] |= State<<18U;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
   
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
@@ -2195,7 +2202,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
   
   /* Contention Detection on Data Lanes OFF */
   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
-  hdsi->Instance->WPCR[0U] |= State<<14U;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
   
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h
index c68d5745a5..8e7daa4d78 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_dsi.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of DSI HAL module.
   ******************************************************************************
   * @attention
@@ -1035,7 +1035,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
-HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimings);
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
@@ -1050,7 +1050,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
                                     uint32_t ChannelID,
                                     uint32_t Mode,
-                                    uint32_t Nbparams,
+                                    uint32_t NbParams,
                                     uint32_t Param1,
                                     uint8_t* ParametersTable);
 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c
index cfc1f3ed36..6443b5ff2f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_eth.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   ETH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Ethernet (ETH) peripheral:
@@ -144,6 +144,7 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+static void ETH_Delay(uint32_t mdelay);
 
 /**
   * @}
@@ -1895,7 +1896,7 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
@@ -1915,7 +1916,7 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
@@ -1935,7 +1936,7 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
@@ -1955,7 +1956,7 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
@@ -2023,10 +2024,25 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->DMAOMR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->DMAOMR = tmpreg1;
 }
 
+/**
+  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
+  * @param  mdelay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+static void ETH_Delay(uint32_t mdelay)
+{
+  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8 / 1000);
+  do 
+  {
+    __NOP();
+  } 
+  while (Delay --);
+}
+
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h
index e6bf8f4600..7a547745eb 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_eth.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of ETH HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c
index 7e08f0af58..9db0b8ac95 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h
index ba7d8a3d33..538b5a61b7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c
index f22ce1a63b..fefa2e278d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
@@ -129,10 +129,10 @@ static uint8_t            FLASH_OB_GetRDP(void);
 static uint8_t            FLASH_OB_GetBOR(void);
 
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx)
+    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
 static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
@@ -378,7 +378,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /**
   * @brief   Program option bytes
   * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
@@ -402,21 +403,23 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
     {
       /*Enable of Write protection on the selected Sector*/
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
       status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
 #else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
       status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
     }
     else
     {
       /*Disable of Write protection on the selected Sector*/
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) 
       status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
 #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
       status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
     }
   }
    
@@ -441,7 +444,8 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
 {
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
   /*Get Sector*/
   pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
 #else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
@@ -453,7 +457,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
 
   /*Get Boot config OB*/
   pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 }
 
 /**
@@ -464,7 +468,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
   * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
   * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
   * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx devices.
+  *         STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
   * 
   * @retval HAL Status
   */
@@ -489,7 +493,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
   * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
   * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
   * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx devices.
+  *         STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
   * 
   * @retval HAL Status
   */
@@ -506,7 +510,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
   return HAL_OK;
 }
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
-          STM32F411xE || STM32F469xx || STM32F479xx */
+          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /**
@@ -936,7 +940,8 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Mass erase of FLASH memory
   * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
@@ -1089,10 +1094,11 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
   
   return status;
 }
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /**
   * @brief  Enable the read/write protection (PCROP) of the desired sectors.
   * @note   This function can be used only for STM32F401xx devices.
@@ -1148,7 +1154,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
   return status;
 
 }
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /**
   * @brief  Set the read protection level.
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h
index 01a5e2c3b1..0e25e3818b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
@@ -114,7 +114,8 @@ typedef struct
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 typedef struct
 {
   uint32_t OptionType;     /*!< Option byte to be configured for extension.
@@ -123,10 +124,12 @@ typedef struct
   uint32_t PCROPState;     /*!< PCROP activation or deactivation.
                                 This parameter can be a value of @ref FLASHEx_PCROP_State */
 
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
   uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
                                 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
+          STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
   uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
@@ -143,7 +146,7 @@ typedef struct
 
 #endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 }FLASH_AdvOBProgramInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */
@@ -247,7 +250,8 @@ typedef struct
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /** @defgroup FLASHEx_PCROP_State FLASH PCROP State
   * @{
   */ 
@@ -257,7 +261,9 @@ typedef struct
   * @}
   */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx) || defined(STM32F412Rx) ||\
+          STM32F412Cx */
 
 /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
   * @{
@@ -269,9 +275,10 @@ typedef struct
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 #define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!<PCROP option byte configuration */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */
@@ -304,7 +311,8 @@ typedef struct
 /*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/ 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE)
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)
      
 #define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
 #define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
@@ -314,7 +322,7 @@ typedef struct
 #define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
 #define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
 #define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*--------------------------------------------------------------------------------------------------------------*/
 
 /**
@@ -334,9 +342,10 @@ typedef struct
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 #define FLASH_BANK_1     ((uint32_t)1U) /*!< Bank 1   */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */ 
@@ -351,9 +360,10 @@ typedef struct
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) 
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */ 
@@ -392,7 +402,8 @@ typedef struct
 /*-----------------------------------------------------------------------------------------------------*/  
 
 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define FLASH_SECTOR_0     ((uint32_t)0U)  /*!< Sector Number 0   */
 #define FLASH_SECTOR_1     ((uint32_t)1U)  /*!< Sector Number 1   */
 #define FLASH_SECTOR_2     ((uint32_t)2U)  /*!< Sector Number 2   */
@@ -405,7 +416,7 @@ typedef struct
 #define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
 #define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
 #define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*-----------------------------------------------------------------------------------------------------*/
 
 /*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
@@ -481,7 +492,8 @@ typedef struct
 /*-----------------------------------------------------------------------------------------------------*/
 
 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
@@ -495,7 +507,7 @@ typedef struct
 #define OB_WRP_SECTOR_10      ((uint32_t)0x00000400U) /*!< Write protection of Sector10    */
 #define OB_WRP_SECTOR_11      ((uint32_t)0x00000800U) /*!< Write protection of Sector11    */
 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*-----------------------------------------------------------------------------------------------------*/
 
 /*--------------------------------------------- STM32F401xC -------------------------------------------*/
@@ -595,8 +607,9 @@ typedef struct
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 /*-----------------------------------------------------------------------------------------------------*/
 
-/*------------------ STM32F401xE/STM32F411xE/STM32F446xx ----------------------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) 
+/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
 #define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
 #define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
@@ -606,7 +619,7 @@ typedef struct
 #define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector6      */
 #define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector7      */
 #define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*-----------------------------------------------------------------------------------------------------*/
 
 /**
@@ -631,11 +644,13 @@ typedef struct
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)  
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)  
 #define OB_PCROP_DESELECTED     ((uint8_t)0x00U) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
 #define OB_PCROP_SELECTED       ((uint8_t)0x80U) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */
@@ -663,13 +678,15 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) 
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)  
 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
 void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
     defined(STM32F469xx) || defined(STM32F479xx)
@@ -694,9 +711,10 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 
 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)  
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define FLASH_SECTOR_TOTAL  12U
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
 #if defined(STM32F401xC)
@@ -708,7 +726,7 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #define FLASH_SECTOR_TOTAL  5U
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
-/*-------------------------------------- STM32F401xE/STM32F411xE/STM32F446xx --------------------------*/
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
 #define FLASH_SECTOR_TOTAL  8U
 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
@@ -762,11 +780,13 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)  
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)  
 #define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
                              ((VALUE) == OB_PCROP_STATE_ENABLE))  
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F469xx) || defined(STM32F479xx)
@@ -775,9 +795,11 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) 
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
   
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -801,7 +823,8 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE)  
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
                                    ((LATENCY) == FLASH_LATENCY_1)  || \
                                    ((LATENCY) == FLASH_LATENCY_2)  || \
@@ -810,7 +833,8 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
                                    ((LATENCY) == FLASH_LATENCY_5)  || \
                                    ((LATENCY) == FLASH_LATENCY_6)  || \
                                    ((LATENCY) == FLASH_LATENCY_7))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
@@ -820,9 +844,11 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)  
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
  
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
@@ -839,14 +865,15 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
                                   ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F401xC)
 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
@@ -886,9 +913,10 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) 
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
    
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
@@ -902,9 +930,10 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) 
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F469xx) || defined(STM32F479xx) 
@@ -914,10 +943,12 @@ uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) 
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)   
 #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c
index 6e16d55aef..aa9702635f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash_ramfunc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FLASH RAMFUNC module driver.
   *          This file provides a FLASH firmware functions which should be 
   *          executed from internal SRAM
@@ -75,7 +75,9 @@
   * @{
   */
 #ifdef HAL_FLASH_MODULE_ENABLED
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -178,7 +180,7 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void)
   * @}
   */
 
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 #endif /* HAL_FLASH_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h
index a006cbe8b5..8f8360b44a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_flash_ramfunc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FLASH RAMFUNC driver.
   ******************************************************************************
   * @attention
@@ -42,7 +42,8 @@
 #ifdef __cplusplus
  extern "C" {
 #endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)  
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
@@ -85,7 +86,7 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
   * @}
   */
 
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c
index 1d80fd46af..a85dfe2d36 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c
@@ -2,25 +2,24 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_fmpi2c.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FMPI2C HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral State and Errors functions
-  *         
+  *
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
     [..]
     The FMPI2C HAL driver can be used as follows:
-    
+
     (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
-        FMPI2C_HandleTypeDef  hfmpi2c; 
+        FMPI2C_HandleTypeDef  hfmpi2c;
 
     (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API:
         (##) Enable the FMPI2Cx interface clock
@@ -36,13 +35,13 @@
             (+++) Configure the DMA handle parameters
             (+++) Configure the DMA Tx or Rx channel
             (+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                   the DMA Tx or Rx channel
 
     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
 
-    (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware 
+    (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware
         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API.
 
     (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
@@ -67,66 +66,84 @@
     *** Interrupt mode IO operation ***
     ===================================
     [..]
-      (+) Transmit in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Transmit_IT()
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT()
       (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Receive_IT()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT()
       (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
       (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Receive_IT()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT()
       (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
-		   
-	*** Interrupt mode IO sequential operation ***
-    ==============================================
-    [..]
-      (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-      (+) A specific option manage the different steps of a sequential transfer
-      (+) Different steps option FMPI2C_XferOptions_definition are listed below :
-      (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode 
-      (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition 
-      (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or 
-             manage only the new data to transfer if no direction change and without a final stop condition in both cases
-      (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or 
-             manage only the new data to transfer if no direction change and with a final stop condition in both cases
-
-      (+) Sequential transmit in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
-      (++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
-      (+) Sequential receive in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
-      (++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
       (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
-      (++) The associated previous transfer callback is called at the end of abort process
-      (++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit
-      (++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive
-      (+) Enable/disable the Address listen mode in slave FMPI2C mode
-           using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
-      (++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
+      (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback()
+      (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode IO sequential operation ***
+    ===================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below:
+      (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+
+      (+) Differents sequential FMPI2C interfaces are listed below:
+      (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
+      (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
+      (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
+      (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
+      (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+      (+++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit
+      (+++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive
+      (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
+      (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
+      (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback()
-      (+) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
-      (++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+      (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
+      (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
-      (+) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
-      (++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()	   
+      (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
+      (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+      (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+      (++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
+      (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
 
     *** Interrupt mode IO MEM operation ***
     =======================================
     [..]
-      (+) Write an amount of data in no blocking mode with Interrupt to a specific memory address using
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
           HAL_FMPI2C_Mem_Write_IT()
       (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
-      (+) Read an amount of data in no blocking mode with Interrupt from a specific memory address using
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
           HAL_FMPI2C_Mem_Read_IT()
       (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
@@ -136,39 +153,45 @@
     *** DMA mode IO operation ***
     ==============================
     [..]
-      (+) Transmit in master mode an amount of data in no blocking mode (DMA) using
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
           HAL_FMPI2C_Master_Transmit_DMA()
       (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in no blocking mode (DMA) using
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
           HAL_FMPI2C_Master_Receive_DMA()
       (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in no blocking mode (DMA) using
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
           HAL_FMPI2C_Slave_Transmit_DMA()
       (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in no blocking mode (DMA) using
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
           HAL_FMPI2C_Slave_Receive_DMA()
       (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+      (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
+      (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback()
+      (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
 
     *** DMA mode IO MEM operation ***
     =================================
     [..]
-      (+) Write an amount of data in no blocking mode with DMA to a specific memory address using
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
           HAL_FMPI2C_Mem_Write_DMA()
       (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
-      (+) Read an amount of data in no blocking mode with DMA from a specific memory address using
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
           HAL_FMPI2C_Mem_Read_DMA()
       (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
 
+
      *** FMPI2C HAL driver macros list ***
      ==================================
      [..]
@@ -176,10 +199,11 @@
 
       (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
       (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
-      (+) __HAL_FMPI2C_GET_FLAG : Checks whether the specified FMPI2C flag is set or not
-      (+) __HAL_FMPI2C_CLEAR_FLAG : Clears the specified FMPI2C pending flag
-      (+) __HAL_FMPI2C_ENABLE_IT: Enables the specified FMPI2C interrupt
-      (+) __HAL_FMPI2C_DISABLE_IT: Disables the specified FMPI2C interrupt
+      (+) __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode
+      (+) __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not
+      (+) __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag
+      (+) __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt
+      (+) __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt
 
      [..]
        (@) You can refer to the FMPI2C HAL driver header file for more useful macros
@@ -213,7 +237,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -229,7 +253,8 @@
 
 #ifdef HAL_FMPI2C_MODULE_ENABLED
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -262,40 +287,73 @@
 #define FMPI2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
 #define FMPI2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
 
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define FMPI2C_XFER_TX_IT          ((uint32_t)0x00000001U)
+#define FMPI2C_XFER_RX_IT          ((uint32_t)0x00000002U)
+#define FMPI2C_XFER_LISTEN_IT      ((uint32_t)0x00000004U)
+
+#define FMPI2C_XFER_ERROR_IT       ((uint32_t)0x00000011U)
+#define FMPI2C_XFER_CPLT_IT        ((uint32_t)0x00000012U)
+#define FMPI2C_XFER_RELOAD_IT      ((uint32_t)0x00000012U)
 /**
   * @}
   */
 
 /* Private macro -------------------------------------------------------------*/
+#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_FMPI2C_STATE_BUSY_TX)   ? \
+                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
+                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
+
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 
 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
   * @{
   */
+/* Private functions to handle DMA transfer */
 static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
 static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
 static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
 static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
 static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
+static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma);
 
-static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
-static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
+/* Private functions to handle IT transfer */
+static void FMPI2C_ITAddrCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITMasterSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITSlaveSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITMasterCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITSlaveCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITListenCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITError (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
 
-static HAL_StatusTypeDef FMPI2C_Master_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
-static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
 
-static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+/* Private functions for FMPI2C transfer IRQ handler */
+static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
 
-static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static HAL_StatusTypeDef FMPI2C_Enable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef FMPI2C_Disable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+
+/* Private functions to flush TXDR register */
+static void FMPI2C_Flush_TXDR (FMPI2C_HandleTypeDef *hfmpi2c);
+
+/* Private functions to handle  start, restart or stop a transfer */
+static void FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
 /**
   * @}
   */
@@ -307,19 +365,19 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAd
   */
 
 /** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions 
-  *
-@verbatim    
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
+    [..]  This subsection provides a set of functions allowing to initialize and
           deinitialize the FMPI2Cx peripheral:
 
-      (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures 
+      (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 
-      (+) Call the function HAL_FMPI2C_Init() to configure the selected device with 
+      (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
           the selected configuration:
         (++) Clock Timing
         (++) Own Address 1
@@ -330,15 +388,15 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAd
         (++) General call mode
         (++) Nostretch mode
 
-      (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration 
-          of the selected FMPI2Cx peripheral.       
+      (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
+          of the selected FMPI2Cx peripheral.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the FMPI2C according to the specified parameters 
+  * @brief  Initializes the FMPI2C according to the specified parameters
   *         in the FMPI2C_InitTypeDef and initialize the associated handle.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
@@ -372,7 +430,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
   }
 
   hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
-  
+
   /* Disable the selected FMPI2C peripheral */
   __HAL_FMPI2C_DISABLE(hfmpi2c);
 
@@ -406,7 +464,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
 
   /*---------------------------- FMPI2Cx OAR2 Configuration ---------------------*/
   /* Configure FMPI2Cx: Dual mode and Own Address2 */
-  hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8U));
+  hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8));
 
   /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
   /* Configure FMPI2Cx: Generalcall and NoStretch mode */
@@ -419,12 +477,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
   hfmpi2c->State = HAL_FMPI2C_STATE_READY;
   hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitialize the FMPI2C peripheral. 
+  * @brief  DeInitialize the FMPI2C peripheral.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @retval HAL status
@@ -465,13 +523,14 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_FMPI2C_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -480,38 +539,39 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_FMPI2C_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions 
-  *  @brief   Data transfers functions 
-  *
-@verbatim   
+/** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to manage the FMPI2C data 
+    This subsection provides a set of functions allowing to manage the FMPI2C data
     transfers.
 
     (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
+       (++) Blocking mode : The communication is performed in the polling mode.
             The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No Blocking mode : The communication is performed using Interrupts 
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when 
+            The end of the data processing will be indicated through the
+            dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
 
     (#) Blocking mode functions are :
@@ -522,16 +582,20 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
         (++) HAL_FMPI2C_Mem_Write()
         (++) HAL_FMPI2C_Mem_Read()
         (++) HAL_FMPI2C_IsDeviceReady()
-        
-    (#) No Blocking mode functions with Interrupt are :
+
+    (#) No-Blocking mode functions with Interrupt are :
         (++) HAL_FMPI2C_Master_Transmit_IT()
         (++) HAL_FMPI2C_Master_Receive_IT()
         (++) HAL_FMPI2C_Slave_Transmit_IT()
         (++) HAL_FMPI2C_Slave_Receive_IT()
+        (++) HAL_FMPI2C_Master_Sequential_Transmit_IT()
+        (++) HAL_FMPI2C_Master_Sequential_Receive_IT()
+        (++) HAL_FMPI2C_Slave_Sequential_Transmit_IT()
+        (++) HAL_FMPI2C_Slave_Sequential_Receive_IT()
         (++) HAL_FMPI2C_Mem_Write_IT()
         (++) HAL_FMPI2C_Mem_Read_IT()
 
-    (#) No Blocking mode functions with DMA are :
+    (#) No-Blocking mode functions with DMA are :
         (++) HAL_FMPI2C_Master_Transmit_DMA()
         (++) HAL_FMPI2C_Master_Receive_DMA()
         (++) HAL_FMPI2C_Slave_Transmit_DMA()
@@ -539,7 +603,7 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
         (++) HAL_FMPI2C_Mem_Write_DMA()
         (++) HAL_FMPI2C_Mem_Read_DMA()
 
-    (#) A set of Transfer Complete Callbacks are provided in no Blocking mode:
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
         (++) HAL_FMPI2C_MemTxCpltCallback()
         (++) HAL_FMPI2C_MemRxCpltCallback()
         (++) HAL_FMPI2C_MasterTxCpltCallback()
@@ -547,6 +611,7 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
         (++) HAL_FMPI2C_SlaveTxCpltCallback()
         (++) HAL_FMPI2C_SlaveRxCpltCallback()
         (++) HAL_FMPI2C_ErrorCallback()
+		(++) HAL_FMPI2C_AbortCpltCallback()
 
 @endverbatim
   * @{
@@ -556,7 +621,8 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
   * @brief  Transmits in master mode an amount of data in blocking mode.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
@@ -564,45 +630,47 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t sizetmp = 0U;
+  uint32_t tickstart = 0;
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-    
-    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+    
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
 
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if(Size > MAX_NBYTE_SIZE)
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
-      sizetmp = MAX_NBYTE_SIZE;
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
     }
     else
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
-      sizetmp = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
     }
 
-    do
+    while(hfmpi2c->XferSize > 0)
     {
       /* Wait until TXIS flag is set */
-      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
       {
         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
         {
@@ -614,35 +682,34 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
         }
       }
       /* Write data to TXDR */
-      hfmpi2c->Instance->TXDR = (*pData++);
-      sizetmp--;
-      Size--;
+      hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+      hfmpi2c->XferCount--;
+      hfmpi2c->XferSize--;
 
-      if((sizetmp == 0U)&&(Size!=0U))
+      if((hfmpi2c->XferSize == 0) && (hfmpi2c->XferCount!=0))
       {
-        /* Wait until TXE flag is set */
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+        /* Wait until TCR flag is set */
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
 
-        if(Size > MAX_NBYTE_SIZE)
+        if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-          sizetmp = MAX_NBYTE_SIZE;
+          hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
         }
         else
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-          sizetmp = Size;
+          hfmpi2c->XferSize = hfmpi2c->XferCount;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
         }
       }
-
-    }while(Size > 0U);
+    }
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is set */
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -661,7 +728,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
     FMPI2C_RESET_CR2(hfmpi2c);
 
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
@@ -675,10 +742,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
 }
 
 /**
-  * @brief  Receives in master mode an amount of data in blocking mode. 
+  * @brief  Receives in master mode an amount of data in blocking mode.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
@@ -686,79 +754,87 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t sizetmp = 0U;
+  uint32_t tickstart = 0;
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-    
-    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
+  {    
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
 
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if(Size > MAX_NBYTE_SIZE)
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-      sizetmp = MAX_NBYTE_SIZE;
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
     }
     else
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
-      sizetmp = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
     }
 
-    do
+    while(hfmpi2c->XferSize > 0)
     {
       /* Wait until RXNE flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)      
+      if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
-      }
-
-      /* Write data to RXDR */
-      (*pData++) =hfmpi2c->Instance->RXDR;
-      sizetmp--;
-      Size--;
-
-      if((sizetmp == 0U)&&(Size!=0U))
-      {
-        /* Wait until TCR flag is set */
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)      
+        if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
         {
-          return HAL_TIMEOUT;
-        }
-        
-        if(Size > MAX_NBYTE_SIZE)
-        {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-          sizetmp = MAX_NBYTE_SIZE;
+          return HAL_ERROR;
         }
         else
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-          sizetmp = Size;
+          return HAL_TIMEOUT;
         }
       }
 
-    }while(Size > 0U);
+      /* Read data from RXDR */
+      (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+      hfmpi2c->XferSize--;
+      hfmpi2c->XferCount--;
+
+      if((hfmpi2c->XferSize == 0) && (hfmpi2c->XferCount != 0))
+      {
+        /* Wait until TCR flag is set */
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hfmpi2c->XferSize = hfmpi2c->XferCount;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+        }
+      }
+    }
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is set */
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -769,16 +845,16 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Clear STOP Flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
 
     /* Clear Configuration Register 2 */
     FMPI2C_RESET_CR2(hfmpi2c);
-    
+
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;	
-    
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
 
@@ -786,7 +862,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
@@ -801,25 +877,34 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
   */
 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0;
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0U))
+    if((pData == NULL ) || (Size == 0))
     {
       return  HAL_ERROR;
     }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
+    
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
-    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
     /* Wait until ADDR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -833,7 +918,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
     if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
     {
       /* Wait until ADDR flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -845,17 +930,17 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
     }
 
     /* Wait until DIR flag is set Transmitter mode */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
 
-    do
+    while(hfmpi2c->XferCount > 0)
     {
       /* Wait until TXIS flag is set */
-      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -871,21 +956,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
       }
 
       /* Write data to TXDR */
-      hfmpi2c->Instance->TXDR = (*pData++);
-      Size--;
-    }while(Size > 0U);
+      hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+      hfmpi2c->XferCount--;
+    }
 
     /* Wait until STOP flag is set */
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
 
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
-        /* Normal use case for Transmitter mode */
-        /* A NACK is generated to confirm the end of transfer */
-        hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+	/* Normal use case for Transmitter mode */
+	/* A NACK is generated to confirm the end of transfer */
+	hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
       }
       else
       {
@@ -897,7 +982,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
 
     /* Wait until BUSY flag is reset */ 
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -908,21 +993,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
     hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
 
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in blocking mode 
+  * @brief  Receive in slave mode an amount of data in blocking mode
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
@@ -932,25 +1017,34 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
   */
 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0;
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0U)) 
+  {  
+    if((pData == NULL ) || (Size == 0))
     {
       return  HAL_ERROR;
     }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
-    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
     /* Wait until ADDR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -959,22 +1053,31 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
 
     /* Clear ADDR flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-    
+
     /* Wait until DIR flag is reset Receiver mode */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
 
-    while(Size > 0U)
+    while(hfmpi2c->XferCount > 0)
     {
       /* Wait until RXNE flag is set */
-      if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+          hfmpi2c->XferCount--;
+        }
+
         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
         {
           return HAL_TIMEOUT;
@@ -986,12 +1089,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
       }
 
       /* Read data from RXDR */
-      (*pData++) = hfmpi2c->Instance->RXDR;
-      Size--;
+      (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+      hfmpi2c->XferCount--;
     }
 
     /* Wait until STOP flag is set */
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -1008,21 +1111,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
 
     /* Clear STOP flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
-    
-    /* Wait until BUSY flag is reset */ 
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+
+    /* Wait until BUSY flag is reset */
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
       return HAL_TIMEOUT;
     }
 
-    
     /* Disable Address Acknowledge */
     hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-    
+
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
@@ -1030,103 +1132,27 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
     return HAL_OK;
   }
   else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in no blocking mode with Interrupt
-  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hfmpi2c);
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
-
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
-    {
-      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
-    }
-    else
-    {
-      hfmpi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
-
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
-              to avoid the risk of FMPI2C interrupt handle execution before current
-              process unlock */
-
-
-    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
-    /* possible to enable all of these */
-    /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
-
-    return HAL_OK;
-  }
-  else
   {
     return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receive in master mode an amount of data in no blocking mode with Interrupt
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  uint32_t xfermode = 0;
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U)) 
-    {
-      return  HAL_ERROR;
-    }
-    
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
@@ -1135,55 +1161,122 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
 
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
-    }
-    
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c); 
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
-    
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Transmit in slave mode an amount of data in no blocking mode with Interrupt 
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified FMPI2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode = 0;
+
+  if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+  {
+    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hfmpi2c);
+
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
+    }
+    else
+    {
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
@@ -1194,37 +1287,34 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
 {
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-    
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_SLAVE;
     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferSize = Size;
-    hfmpi2c->XferCount = Size;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_IT;
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
 
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_TXI );
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
@@ -1235,7 +1325,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in no blocking mode with Interrupt 
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
@@ -1246,64 +1336,59 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
 {
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_SLAVE;
     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferSize = Size;
-    hfmpi2c->XferCount = Size;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_IT;
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
 
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI);
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Transmit in master mode an amount of data in no blocking mode with DMA
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  uint32_t xfermode = 0;
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
@@ -1312,63 +1397,59 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_DMA;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
 
     /* Set the FMPI2C DMA transfer complete callback */
     hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
-    
+
     /* Set the DMA error callback */
     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
-    
+
+    /* Set the unused DMA callbacks to NULL */
+    hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the DMA channel */
     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
 
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
-    }
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
 
-    /* Wait until TXIS flag is set */
-    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+    /* Update XferCount value */
+    hfmpi2c->XferCount -= hfmpi2c->XferSize;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR and NACK interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+    /* Enable DMA Request */
+    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+
     return HAL_OK;
   }
   else
@@ -1378,23 +1459,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
 }
 
 /**
-  * @brief  Receive in master mode an amount of data in no blocking mode with DMA 
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  uint32_t xfermode = 0;
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
@@ -1403,54 +1482,69 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MASTER;
     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_DMA;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
 
-    /* Set the FMPI2C DMA transfer complete callback */
-    hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
-
-    /* Set the DMA error callback */
-    hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
+    if(hfmpi2c->XferSize > 0)
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+      /* Set the FMPI2C DMA transfer complete callback */
+      hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+                to avoid the risk of FMPI2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
     }
     else
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
     }
-
-    /* Wait until RXNE flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    
-    /* Enable DMA Request */
-    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
-
     return HAL_OK;
   }
   else
@@ -1460,7 +1554,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
 }
 
 /**
-  * @brief  Transmit in slave mode an amount of data in no blocking mode with DMA 
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
@@ -1471,20 +1565,23 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
 {
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
-    }
+    }   
     /* Process Locked */
-    __HAL_LOCK(hfmpi2c); 
+    __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_SLAVE;
     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    hfmpi2c->XferSize = Size;
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_DMA;
 
     /* Set the FMPI2C DMA transfer complete callback */
     hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
@@ -1492,52 +1589,28 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
     /* Set the DMA error callback */
     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
 
+    /* Set the unused DMA callbacks to NULL */
+    hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the DMA channel */
     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
-    /* Wait until ADDR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-
-    /* If 10bits addressing mode is selected */
-    if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-    }
-
-    /* Wait until DIR flag is set Transmitter mode */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
-
-    /* Enable DMA Request */
-    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
-
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; 
+
     return HAL_OK;
   }
   else
@@ -1547,7 +1620,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in no blocking mode with DMA 
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
@@ -1558,20 +1631,23 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
 {
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
-    }
+    }   
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferSize = Size;
-    hfmpi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_DMA;
 
     /* Set the FMPI2C DMA transfer complete callback */
     hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
@@ -1579,37 +1655,28 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
     /* Set the DMA error callback */
     hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
 
+    /* Set the unused DMA callbacks to NULL */
+    hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
     /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, Size);
+    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
-    /* Wait until ADDR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
 
-    /* Clear ADDR flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-
-    /* Wait until DIR flag is set Receiver mode */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, FMPI2C_TIMEOUT_DIR) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-      return HAL_TIMEOUT;
-    }
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
 
     /* Enable DMA Request */
     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
-
     return HAL_OK;
   }
   else
@@ -1617,7 +1684,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
     return HAL_BUSY;
   }
 }
-
 /**
   * @brief  Write an amount of data in blocking mode to a specific memory address
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
@@ -1632,32 +1698,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t Sizetmp = 0U;
+  uint32_t tickstart = 0;
 
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-  
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  { 
-    if((pData == NULL) || (Size == 0U)) 
+  {
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
 
-    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MEM;
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
 
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
+
     /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -1673,23 +1747,22 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
       }
     }
 
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if(Size > MAX_NBYTE_SIZE)
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-      Sizetmp = MAX_NBYTE_SIZE;
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
     }
     else
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-      Sizetmp = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
     }
 
     do
     {
       /* Wait until TXIS flag is set */
-      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
       {
         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
         {
@@ -1701,36 +1774,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
         }
       }
 
-      /* Write data to DR */
-      hfmpi2c->Instance->TXDR = (*pData++);
-      Sizetmp--;
-      Size--;
+      /* Write data to TXDR */
+      hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+      hfmpi2c->XferCount--;
+      hfmpi2c->XferSize--;
 
-      if((Sizetmp == 0U)&&(Size!=0U))
+      if((hfmpi2c->XferSize == 0) && (hfmpi2c->XferCount!=0))
       {
         /* Wait until TCR flag is set */
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        
-        if(Size > MAX_NBYTE_SIZE)
+
+        if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-          Sizetmp = MAX_NBYTE_SIZE;
+          hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
         }
         else
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-          Sizetmp = Size;
+          hfmpi2c->XferSize = hfmpi2c->XferCount;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
         }
       }
-      
-    }while(Size > 0U);
+
+    }while(hfmpi2c->XferCount > 0);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -1741,7 +1814,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
         return HAL_TIMEOUT;
       }
     }
-    
+
     /* Clear STOP Flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
 
@@ -1749,7 +1822,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
     FMPI2C_RESET_CR2(hfmpi2c);
 
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
@@ -1776,32 +1849,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t Sizetmp = 0U;
+  uint32_t tickstart = 0;
 
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-  
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {    
-    if((pData == NULL) || (Size == 0U))
+  {
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
 
-    if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MEM;
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
 
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr  = pData;
+    hfmpi2c->XferCount = Size;
+    hfmpi2c->XferISR   = NULL;
+
     /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -1818,59 +1899,55 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
     }
 
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if(Size > MAX_NBYTE_SIZE)
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-      Sizetmp = MAX_NBYTE_SIZE;
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
     }
     else
     {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
-      Sizetmp = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
     }
 
     do
-    {  
+    {
       /* Wait until RXNE flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
-          
+
       /* Read data from RXDR */
-      (*pData++) = hfmpi2c->Instance->RXDR;
+      (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+      hfmpi2c->XferSize--;
+      hfmpi2c->XferCount--;
 
-      /* Decrement the Size counter */
-      Sizetmp--;
-      Size--;   
-
-      if((Sizetmp == 0U)&&(Size!=0U))
+      if((hfmpi2c->XferSize == 0) && (hfmpi2c->XferCount != 0))
       {
         /* Wait until TCR flag is set */
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        
-        if(Size > MAX_NBYTE_SIZE)
+
+        if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-          Sizetmp = MAX_NBYTE_SIZE;
+          hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
         }
         else
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-          Sizetmp = Size;
+          hfmpi2c->XferSize = hfmpi2c->XferCount;
+          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
         }
       }
-
-    }while(Size > 0U);
+    }while(hfmpi2c->XferCount > 0);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -1889,7 +1966,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
     FMPI2C_RESET_CR2(hfmpi2c);
 
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+    hfmpi2c->Mode  = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
@@ -1901,9 +1978,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
     return HAL_BUSY;
   }
 }
-
 /**
-  * @brief  Write an amount of data in no blocking mode with Interrupt to a specific memory address
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  DevAddress Target device address
@@ -1915,16 +1991,19 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0;
+  uint32_t xfermode = 0;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
-
+    
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
@@ -1933,24 +2012,32 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MEM;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
-    
+
     /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -1966,16 +2053,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
       }
     }
 
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-    }
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c); 
@@ -1983,12 +2062,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
     /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
-    
+
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
-    
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
     return HAL_OK;
   }
   else
@@ -1998,7 +2077,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
 }
 
 /**
-  * @brief  Read an amount of data in no blocking mode with Interrupt from a specific memory address
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  DevAddress Target device address
@@ -2010,12 +2089,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0;
+  uint32_t xfermode = 0;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-  
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U))
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
@@ -2028,24 +2110,32 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MEM;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
 
     /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -2061,39 +2151,30 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
       }
     }
 
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
-    }
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
+    __HAL_UNLOCK(hfmpi2c);
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
 
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
-    __HAL_FMPI2C_ENABLE_IT(hfmpi2c, FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
-  }
+    return HAL_BUSY;
+  }   
 }
-
 /**
-  * @brief  Write an amount of data in no blocking mode with DMA to a specific memory address
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  DevAddress Target device address
@@ -2105,16 +2186,19 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0;
+  uint32_t xfermode = 0;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-  
+
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
-    
+
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
     {
       return HAL_BUSY;
@@ -2123,76 +2207,78 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MEM;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_DMA;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hfmpi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hfmpi2c);
+        return HAL_TIMEOUT;
+      }
     }
 
     /* Set the FMPI2C DMA transfer complete callback */
-    hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMemTransmitCplt;
+    hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
 
     /* Set the DMA error callback */
     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
 
+    /* Set the unused DMA callbacks to NULL */
+    hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the DMA channel */
     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
 
-    /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
     /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-    }
-    
-    /* Wait until TXIS flag is set */
-    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
-    {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+
+    /* Update XferCount value */
+    hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR and NACK interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
 
     /* Enable DMA Request */
     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
 
     return HAL_OK;
   }
@@ -2203,7 +2289,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
 }
 
 /**
-  * @brief  Reads an amount of data in no blocking mode with DMA from a specific memory address.
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  DevAddress Target device address
@@ -2215,12 +2301,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
   */
 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0;
+  uint32_t xfermode = 0;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-
+  
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
@@ -2233,31 +2322,32 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
 
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    if(Size > MAX_NBYTE_SIZE)
+    hfmpi2c->State       = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode        = HAL_FMPI2C_MODE_MEM;
+    hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_DMA;
+    
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = FMPI2C_AUTOEND_MODE;
     }
 
-    /* Set the FMPI2C DMA transfer complete callback */
-    hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMemReceiveCplt;
-
-    /* Set the DMA error callback */
-    hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
-
-    /* Enable the DMA channel */
-    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
-
     /* Send Slave Address and Memory Address */
-    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
+    if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -2273,27 +2363,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
       }
     }
 
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-    }
-    else
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
-    }
+    /* Set the FMPI2C DMA transfer complete callback */
+    hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
 
-    /* Wait until RXNE flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
+    /* Set the DMA error callback */
+    hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+
+    /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+
+    /* Update XferCount value */
+    hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
 
     /* Enable DMA Request */
     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+              to avoid the risk of FMPI2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR and NACK interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
 
     return HAL_OK;
   }
@@ -2304,7 +2403,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
 }
 
 /**
-  * @brief  Checks if target device is ready for communication. 
+  * @brief  Checks if target device is ready for communication.
   * @note   This function is used with Memory devices
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
@@ -2314,10 +2413,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
-  uint32_t tickstart = 0U;
+{  
+  uint32_t tickstart = 0;
 
-  __IO uint32_t FMPI2C_Trials = 0U;
+  __IO uint32_t FMPI2C_Trials = 0;
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
@@ -2336,15 +2435,15 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
     {
       /* Generate Start */
       hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress);
-
+      
       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
       /* Wait until STOPF flag is set or a NACK flag is set*/
       tickstart = HAL_GetTick();
       while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
       {
-        if(Timeout != HAL_MAX_DELAY)
-        {
-          if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      	if(Timeout != HAL_MAX_DELAY)
+      	{
+          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
           {
             /* Device is ready */
             hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -2352,33 +2451,33 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
             __HAL_UNLOCK(hfmpi2c);
             return HAL_TIMEOUT;
           }
-        }
+        } 
       }
-      
+
       /* Check if the NACKF flag has not been set */
-      if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
+      if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
       {
         /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        
+
         /* Clear STOP Flag */
         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
 
         /* Device is ready */
         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-        
+
         /* Process Unlocked */
         __HAL_UNLOCK(hfmpi2c);
-        
+
         return HAL_OK;
       }
       else
       {
         /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -2391,13 +2490,13 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
       }
 
       /* Check if the maximum allowed number of trials has been reached */
-      if(FMPI2C_Trials++ == Trials)
+      if (FMPI2C_Trials++ == Trials)
       {
         /* Generate Stop */
         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
         
-        /* Wait until STOPF flag is reset */
-        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        /* Wait until STOPF flag is reset */ 
+        if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -2411,7 +2510,7 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
-        
+
     return HAL_TIMEOUT;
   }
   else
@@ -2421,18 +2520,22 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
 }
 
 /**
-  * @brief  Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
+  * @brief  Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode with Interrupt.
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
+  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
+  uint32_t xfermode = 0;
+  uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -2440,53 +2543,47 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef
   {
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
-    
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_TX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MASTER;
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
 
     /* Prepare transfer parameters */
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
     hfmpi2c->XferOptions = XferOptions;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
 
-    if(Size > MAX_NBYTE_SIZE)
+    /* If size > MAX_NBYTE_SIZE, use reload mode */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
-    }
-
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if((hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
-    {
-      FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
-    }
-    else
-    {
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = hfmpi2c->XferOptions;
+      
       /* If transfer direction not change, do not generate Restart Condition */
       /* Mean Previous state is same as current state */
       if(hfmpi2c->PreviousState == FMPI2C_STATE_SLAVE_BUSY_TX)
       {
-        FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_GENERATE_START_WRITE);
+        xferrequest = FMPI2C_NO_STARTSTOP;
       }
     }
+    
+
+    /* Send Slave Address and set NBYTES to write */
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c); 
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
-    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX);
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
 
     return HAL_OK;
   }
@@ -2497,18 +2594,22 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef
 }
 
 /**
-  * @brief  Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt
+  * @brief  Sequential receive in master FMPI2C mode an amount of data in non-blocking mode with Interrupt
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
+  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
+  uint32_t xfermode = 0;
+  uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
+
   /* Check the parameters */
   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -2516,70 +2617,63 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *
   {
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
-    
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    
-    /* Prepare transfer parameters */
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferCount = Size;
-    hfmpi2c->XferOptions = XferOptions;
 
-    if(Size > MAX_NBYTE_SIZE)
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_RX;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_MASTER;
+    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferOptions = XferOptions;
+    hfmpi2c->XferISR     = FMPI2C_Master_ISR_IT;
+
+    /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = FMPI2C_RELOAD_MODE;
     }
     else
     {
-      hfmpi2c->XferSize = Size;
-    }
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+      xfermode = hfmpi2c->XferOptions;
 
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-    {
-      FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
-    }
-    else
-    {
       /* If transfer direction not change, do not generate Restart Condition */
       /* Mean Previous state is same as current state */
       if(hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
       {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
-      }
-      /* Else transfer direction change, so generate Restart with new transfer direction */
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_GENERATE_START_READ);
+        xferrequest = FMPI2C_NO_STARTSTOP;
       }
     }
 
+    /* Send Slave Address and set NBYTES to read */
+    FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
+
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c); 
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
-    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-    
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt
+  * @brief  Sequential transmit in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
+  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
@@ -2589,59 +2683,63 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U))
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
 
     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_TX);
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
 
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_SLAVE;
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    
+
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
     /* Prepare transfer parameters */
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferSize = Size;
-    hfmpi2c->XferCount = Size;
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
     hfmpi2c->XferOptions = XferOptions;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_IT;
 
-    /* Clear ADDR flag after prepare the transfer parameters */
-    /* This action will generate an acknowledge to the Master */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+    if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+    }
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c); 
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
     to avoid the risk of FMPI2C interrupt handle execution before current
     process unlock */
     /* REnable ADDR interrupt */
-    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX | FMPI2C_IT_ADDR);
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_ERROR; 
+    return HAL_ERROR;
   }
 }
 
 /**
-  * @brief  Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt
+  * @brief  Sequential receive in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
+  * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
@@ -2651,48 +2749,52 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h
 
   if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if((pData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
 
     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_RX);
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT);
 
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+    hfmpi2c->State     = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
+    hfmpi2c->Mode      = HAL_FMPI2C_MODE_SLAVE;
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
 
     /* Enable Address Acknowledge */
     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
 
     /* Prepare transfer parameters */
-    hfmpi2c->pBuffPtr = pData;
-    hfmpi2c->XferSize = Size;
-    hfmpi2c->XferCount = Size;
+    hfmpi2c->pBuffPtr    = pData;
+    hfmpi2c->XferCount   = Size;
+    hfmpi2c->XferSize    = hfmpi2c->XferCount;
     hfmpi2c->XferOptions = XferOptions;
+    hfmpi2c->XferISR     = FMPI2C_Slave_ISR_IT;
 
-    /* Clear ADDR flag after prepare the transfer parameters */
-    /* This action will generate an acknowledge to the Master */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+    if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+    }
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
+    __HAL_UNLOCK(hfmpi2c);
 
-    /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
+    /* Note : The FMPI2C interrupts must be enabled after unlocking current process
     to avoid the risk of FMPI2C interrupt handle execution before current
     process unlock */
     /* REnable ADDR interrupt */
-    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX | FMPI2C_IT_ADDR);
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_ERROR; 
+    return HAL_ERROR;
   }
 }
 
@@ -2707,9 +2809,10 @@ HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
   {
     hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+    hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
 
     /* Enable the Address Match interrupt */
-    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_ADDR);
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
@@ -2737,9 +2840,10 @@ HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
     hfmpi2c->PreviousState = tmp | (uint32_t)(hfmpi2c->Mode);
     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
+    hfmpi2c->XferISR = NULL;
+    
     /* Disable the Address Match interrupt */
-    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR);
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
 
     return HAL_OK;
   }
@@ -2750,55 +2854,39 @@ HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
 }
 
 /**
-  * @brief  Abort a master/host FMPI2C process communication with Interrupt.
-  * @note   This abort can be called only if state is ready
+  * @brief  Abort a master FMPI2C IT or DMA process communication with Interrupt.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
 {
-  if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || \
-     ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) && ((hfmpi2c->PreviousState & ((uint32_t)HAL_FMPI2C_MODE_MASTER)) == HAL_FMPI2C_MODE_MASTER)))
+  if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
   {
     /* Process Locked */
     __HAL_LOCK(hfmpi2c);
-    
-    /* Keep the same state as previous */
-    /* to perform as well the call of the corresponding end of transfer callback */
-    if((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE))
-    {
-      hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    }
-    else if((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE))
-    {
-      hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
-    }
 
-    hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    
+    /* Disable Interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+    /* Set State at HAL_FMPI2C_STATE_ABORT */
+    hfmpi2c->State = HAL_FMPI2C_STATE_ABORT;
+
     /* Set NBYTES to 1 to generate a dummy read on FMPI2C peripheral */
     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
-    FMPI2C_TransferConfig(hfmpi2c, DevAddress, 1U, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_STOP);
-    
+    FMPI2C_TransferConfig(hfmpi2c, DevAddress, 1, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_STOP);
+
     /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c); 
+    __HAL_UNLOCK(hfmpi2c);
 
     /* Note : The FMPI2C interrupts must be enabled after unlocking current process 
               to avoid the risk of FMPI2C interrupt handle execution before current
               process unlock */
-    if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
-    {
-      FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-    }
-    if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
-    {
-      FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-    }
-
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+    
     return HAL_OK;
   }
   else
@@ -2814,8 +2902,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint
   */
 
 /** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
+ * @{
+ */   
 
 /**
   * @brief  This function handles FMPI2C event interrupt request.
@@ -2825,59 +2913,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint
   */
 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
 {
-  uint32_t tmpisrvalue = 0U;
-  
-  /* Use a local variable to store the current ISR flags */
-  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
-  tmpisrvalue = FMPI2C_GET_ISR_REG(hfmpi2c);
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hfmpi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
 
-  /* FMPI2C in mode Transmitter ---------------------------------------------------*/
-  if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TXIS) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TCR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TC) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI)) != RESET))
+  /* FMPI2C events treatment -------------------------------------*/
+  if(hfmpi2c->XferISR != NULL)
   {
-    /* Slave mode selected */
-    if(hfmpi2c->Mode  == HAL_FMPI2C_MODE_SLAVE)
-    {
-      FMPI2C_Slave_ISR(hfmpi2c);
-    }
-    /* Master or Memory mode selected */
-    if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
-    {
-      FMPI2C_Master_ISR(hfmpi2c);
-    }
-  }
-
-  /* FMPI2C in mode Receiver ----------------------------------------------------*/
-  if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_RXNE) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TCR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TC) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI)) != RESET))
-  {
-    /* Slave mode selected */
-    if(hfmpi2c->Mode  == HAL_FMPI2C_MODE_SLAVE)
-    {
-      FMPI2C_Slave_ISR(hfmpi2c);
-    }
-    /* Master or Memory mode selected */
-    if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
-    {
-      FMPI2C_Master_ISR(hfmpi2c);
-    }
-  }
-
-   /* FMPI2C in mode Listener Only --------------------------------------------------*/
-  if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_ADDR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && ((__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ADDRI) != RESET) || (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_STOPI) != RESET) || (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_NACKI) != RESET)))
-  {
-    if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
-    {
-      if((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
-      {
-        FMPI2C_Slave_ISR(hfmpi2c);
-      }
-    }
-    else
-    {
-      if(hfmpi2c->Mode == HAL_FMPI2C_MODE_SLAVE)
-      {
-        FMPI2C_Slave_ISR(hfmpi2c);
-      }
-    }
+    hfmpi2c->XferISR(hfmpi2c, itflags, itsources);
   }
 }
 
@@ -2889,17 +2932,20 @@ void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
   */
 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
 {
+  uint32_t itflags   = READ_REG(hfmpi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
+
   /* FMPI2C Bus error interrupt occurred ------------------------------------*/
-  if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BERR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
-  { 
+  if(((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+  {
     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
-   
+
     /* Clear BERR flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR);
   }
-  
+
   /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_OVR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+  if(((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
   {
     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
 
@@ -2908,7 +2954,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
   }
 
   /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
+  if(((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
   {
     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
 
@@ -2919,20 +2965,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
   /* Call the Error Callback in case of Error detected */
   if((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) !=  HAL_FMPI2C_ERROR_NONE)
   {
-    if(((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_SLAVE))
-    {
-      /* Reset only HAL_FMPI2C_STATE_SLAVE_BUSY_XX */
-      /* keep HAL_FMPI2C_STATE_LISTEN if set */
-      hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
-      hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
-    }
-    else
-    {
-      hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
-      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    }
-
-    HAL_FMPI2C_ErrorCallback(hfmpi2c);
+    FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
   }
 }
 
@@ -2942,12 +2975,13 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
+
   /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+            the HAL_FMPI2C_MasterTxCpltCallback could be implemented in the user file
    */
 }
 
@@ -2961,8 +2995,9 @@ __weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FMPI2C_MasterRxCpltCallback could be implemented in the user file
    */
 }
 
@@ -2971,12 +3006,13 @@ __weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FMPI2C_SlaveTxCpltCallback could be implemented in the user file
    */
 }
 
@@ -2990,8 +3026,9 @@ __weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FMPI2C_SlaveRxCpltCallback could be implemented in the user file
    */
 }
 
@@ -2999,7 +3036,7 @@ __weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
   * @brief  Slave Address Match callback.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XferOptions_definition
+  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFEROPTIONS
   * @param  AddrMatchCode: Address Match Code
   * @retval None
   */
@@ -3009,6 +3046,7 @@ __weak void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t Trans
   UNUSED(hfmpi2c);
   UNUSED(TransferDirection);
   UNUSED(AddrMatchCode);
+
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_FMPI2C_AddrCallback() could be implemented in the user file
    */
@@ -3024,6 +3062,7 @@ __weak void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
+
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_FMPI2C_ListenCpltCallback() could be implemented in the user file
    */
@@ -3035,13 +3074,14 @@ __weak void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
+
   /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
-   */ 
+            the HAL_FMPI2C_MemTxCpltCallback could be implemented in the user file
+   */
 }
 
 /**
@@ -3054,8 +3094,9 @@ __weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FMPI2C_MemRxCpltCallback could be implemented in the user file
    */
 }
 
@@ -3065,28 +3106,45 @@ __weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
   *                the configuration information for the specified FMPI2C.
   * @retval None
   */
- __weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+__weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfmpi2c);
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_FMPI2C_ErrorCallback could be implemented in the user file
    */
 }
 
+/**
+  * @brief  FMPI2C abort callback.
+  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified FMPI2C.
+  * @retval None
+  */
+__weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfmpi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FMPI2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   Peripheral State and Errors functions
-  *
-@verbatim   
+/** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
  ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================  
     [..]
-    This subsection permit to get in run-time the status of the peripheral 
+    This subsection permit to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -3117,11 +3175,11 @@ HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
 }
 
 /**
-  * @brief  Return the FMPI2C error code.
+* @brief  Return the FMPI2C error code.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *              the configuration information for the specified FMPI2C.
-  * @retval FMPI2C Error Code
-  */
+* @retval FMPI2C Error Code
+*/
 uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
 {
   return hfmpi2c->ErrorCode;
@@ -3133,484 +3191,207 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
 
 /**
   * @}
-  */   
+  */
 
 /** @addtogroup FMPI2C_Private_Functions
   * @{
   */
+
 /**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_Master_ISR(FMPI2C_HandleTypeDef *hfmpi2c) 
+static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) 
 {
-  uint16_t DevAddress;
+  uint16_t devaddress = 0;
 
   /* Process Locked */
   __HAL_LOCK(hfmpi2c);
 
-  if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+  if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
   {
     /* Clear NACK Flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
 
     /* Set corresponding Error Code */
     /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
-    
-    /* Call the Error callback to prevent upper layer */
-    HAL_FMPI2C_ErrorCallback(hfmpi2c);
+    /* Flush TX register */
+    FMPI2C_Flush_TXDR(hfmpi2c);
   }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) != RESET)
-  {
-    if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
-    {
-      /* Disable Interrupt */
-      FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-      {
-        /* Disable the selected FMPI2C peripheral */
-        __HAL_FMPI2C_DISABLE(hfmpi2c);
-
-        hfmpi2c->PreviousState = FMPI2C_STATE_MEM_BUSY_TX;
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* REenable the selected FMPI2C peripheral */
-        __HAL_FMPI2C_ENABLE(hfmpi2c);
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
-      }
-      else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-      {
-        /* Flush TX register if not empty */
-        if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
-        {
-          __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
-        }
-
-        hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
-      }
-    }
-    else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
-    {
-      /* Disable Interrupt */
-      FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-      {
-        hfmpi2c->PreviousState = FMPI2C_STATE_MEM_BUSY_RX;
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
-      }
-      else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-      {
-        hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-        
-        /* Call the corresponding callback to inform upper layer of End of Transfer */
-        HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
-      }
-    }
-  }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
   {
     /* Read data from RXDR */
     (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
     hfmpi2c->XferSize--;
     hfmpi2c->XferCount--;
   }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
   {
     /* Write data to TXDR */
     hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
     hfmpi2c->XferSize--;
     hfmpi2c->XferCount--;	
   }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
   {
-    if((hfmpi2c->XferSize == 0U)&&(hfmpi2c->XferCount!=0U))
+    if((hfmpi2c->XferSize == 0) && (hfmpi2c->XferCount != 0))
     {
-      DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+      devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
       
       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
       {
-        FMPI2C_TransferConfig(hfmpi2c, DevAddress, MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+        FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
       }
       else
       {
         hfmpi2c->XferSize = hfmpi2c->XferCount;
         if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
         {
-          FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
+          FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
         }
         else
         {
-          FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+          FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
         }
       }
     }
-    else if((hfmpi2c->XferSize == 0U)&&(hfmpi2c->XferCount==0U))
+    else
     {
       /* Call TxCpltCallback() if no stop mode is set */
-      if(FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+      if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
       {
-        if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
-        {
-          /* Disable Interrupt */
-          FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-          hfmpi2c->PreviousState = hfmpi2c->State;
-          hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-          
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-          {
-            HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
-          }
-          else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-          {
-            HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
-          }
-        }
-        else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
-        {
-          FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-          hfmpi2c->PreviousState = hfmpi2c->State;
-          hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-          {
-            HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
-          }
-          else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-          {
-            HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
-          }
-        }
+        /* Call FMPI2C Master Sequential complete process */
+        FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
       }
     }
   }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
   {
-    if(hfmpi2c->XferCount == 0U)
+    if(hfmpi2c->XferCount == 0)
     {
-      if(FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+      if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
       {
-        /* No Generate Stop, to permit restart mode */
-        /* The stop will be done at the end of transfer, when FMPI2C_AUTOEND_MODE enable */
-        if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
-        {
-          /* Disable Interrupt */
-          FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-          hfmpi2c->PreviousState = hfmpi2c->State;
-          hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-          {
-            HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
-          }
-          else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-          {
-            HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
-          }
-        }
-        else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
-        {
-          FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-          hfmpi2c->PreviousState = hfmpi2c->State;
-          hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-          
-          /* Call the corresponding callback to inform upper layer of End of Transfer */
-          if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
-          {
-            HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
-          }
-          else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
-          {
-            HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
-          }
-        }
+        /* Call FMPI2C Master Sequential complete process */
+        FMPI2C_ITMasterSequentialCplt(hfmpi2c);
       }
     }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
+    }
+  }
+
+  if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+  {
+    /* Call FMPI2C Master complete process */
+    FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
   }
 
   /* Process Unlocked */
-  __HAL_UNLOCK(hfmpi2c); 
+  __HAL_UNLOCK(hfmpi2c);
 
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
-  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c) 
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) 
 {
-  uint8_t TransferDirection = 0U;
-  uint16_t SlaveAddrCode = 0U;
-  uint16_t OwnAdd1Code = 0U;
-  uint16_t OwnAdd2Code = 0U;
-
-  /* Process Locked */
+  /* Process locked */
   __HAL_LOCK(hfmpi2c);
-
-  if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
+  
+  if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
   {
     /* Check that FMPI2C transfer finished */
-    /* if yes, normal usecase, a NACK is sent by the Master when Transfer is finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
     /* Mean XferCount == 0*/
     /* So clear Flag NACKF only */
-    if(hfmpi2c->XferCount == 0U)
-    {  
-       if(((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
+    if(hfmpi2c->XferCount == 0)
+    {
+      if(((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
         (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
       {
-        hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
-        /* Disable all Interrupts*/
-        FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_RX | FMPI2C_IT_TX);
-
-        /* Clear NACK Flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
-
-        hfmpi2c->PreviousState = hfmpi2c->State;
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-        /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-        HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+        /* Call FMPI2C Listen complete process */
+        FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
       }
       else if((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
       {
-        /* Last Byte is Transmitted */
-        /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
-        FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-        hfmpi2c->PreviousState = hfmpi2c->State;
-        hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
-
         /* Clear NACK Flag */
         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
 
-        /* Check if TXIS flag is SET */
-        if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
-        {
-          /* Send a dummy data, to clear TXIS event */
-          hfmpi2c->Instance->TXDR = 0x00U;
+        /* Flush TX register */
+        FMPI2C_Flush_TXDR(hfmpi2c);
 
-          /* Flush TX register if not empty */
-          if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
-          {
-            __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
-          }
-        }
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* Call the Tx complete callback to inform upper layer of the end of transmit process */
-        HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+        /* Last Byte is Transmitted */
+        /* Call FMPI2C Slave Sequential complete process */
+        FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
       }
       else
       {
         /* Clear NACK Flag */
         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
       }
     }
     else
     {
-      /* if no, error usecase, a Non-Acknowledge of last Data is generated by the Master*/
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
       /* Clear NACK Flag */
       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
 
-      if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
-      { 
-        /* Set HAL State to "Idle" State, mean to LISTEN state */
-        /* So reset Slave Busy state */
-        hfmpi2c->PreviousState = hfmpi2c->State;
-        hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
-
-        /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
-        FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX | FMPI2C_IT_TX);
-      }
-
       /* Set ErrorCode corresponding to a Non-Acknowledge */
       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hfmpi2c);
-
-      /* Call the Error callback to prevent upper layer */
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
     }
   }
-
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
   {
-    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
-    /* Other ADDRInterrupt will be treat in next Listen usecase */
-    if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
-    {
-      TransferDirection = FMPI2C_GET_DIR(hfmpi2c);
-      SlaveAddrCode = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
-      OwnAdd1Code = FMPI2C_GET_OWN_ADDRESS1(hfmpi2c);
-      OwnAdd2Code = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c);
-
-      /* If 10bits addressing mode is selected */
-      if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
-      {
-        if((SlaveAddrCode & SlaveAddr_MSK) == ((OwnAdd1Code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
-        {
-          SlaveAddrCode = OwnAdd1Code;
-          hfmpi2c->AddrEventCount++;
-          if(hfmpi2c->AddrEventCount == 2U)
-          {
-            /* Reset Address Event counter  */
-            hfmpi2c->AddrEventCount = 0U;
-
-            /* Clear ADDR flag */
-            __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-
-            /* Process Unlocked */
-            __HAL_UNLOCK(hfmpi2c);
-
-            /* Call Slave Addr callback */
-            HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
-          }
-        }
-        else
-        {
-          SlaveAddrCode = OwnAdd2Code;
-          __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_ADDRI);
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-
-          /* Call Slave Addr callback */
-          HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
-        }
-      }
-
-      /* If 7 bits addressing mode is selected */
-      else if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
-      {
-        __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_ADDRI);
-
-        /* Clear ADDR flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* Call Slave Addr callback */
-        HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
-      }
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hfmpi2c);
-    }
-  }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) != RESET)
-  {
-    if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
-    { 
-      if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
-      {
-        /* Read data from RXDR */
-        (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
-        hfmpi2c->XferSize--;
-        hfmpi2c->XferCount--;
-
-        if(hfmpi2c->XferCount == 0U)
-        {
-          /* Last Byte is received, disable Interrupt */
-          FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
-
-          /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */
-          hfmpi2c->PreviousState = hfmpi2c->State;
-          hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-
-          /* Call the Rx complete callback to inform upper layer of the end of receive process */
-          HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
-        }
-      }
-    }
-    else
+    if(hfmpi2c->XferCount > 0)
     {
       /* Read data from RXDR */
       (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
       hfmpi2c->XferSize--;
       hfmpi2c->XferCount--;
     }
+
+    if((hfmpi2c->XferCount == 0) && \
+       (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME))
+    {
+      /* Call FMPI2C Slave Sequential complete process */
+      FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+   }
   }
-  else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
+  else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+  {
+    FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
+  }
+  else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
   {
     /* Write data to TXDR only if XferCount not reach "0" */
     /* A TXIS flag can be set, during STOP treatment      */
     /* Check if all Datas have already been sent */
     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
-    if(hfmpi2c->XferCount > 0U)
+    if(hfmpi2c->XferCount > 0)
     {
       /* Write data to TXDR */
       hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
@@ -3619,63 +3400,161 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
     }
     else
     {
-      if((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+      if((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME))
       {
         /* Last Byte is Transmitted */
-        /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
-        FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
-        hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
-        hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hfmpi2c);
-
-        /* Call the Tx complete callback to inform upper layer of the end of transmit process */
-        HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+        /* Call FMPI2C Slave Sequential complete process */
+        FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
       }
     }
   }
 
   /* Check if STOPF is set */
-  if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) != RESET)
+  if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
   {
-    /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
-    __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI);
+    /* Call FMPI2C Slave complete process */
+    FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+  }
 
-    /* Disable Address Acknowledge */
-    hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hfmpi2c);
 
-    /* Clear Configuration Register 2 */
-    FMPI2C_RESET_CR2(hfmpi2c);
+  return HAL_OK;
+}
 
-    /* Clear STOP Flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified FMPI2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  uint16_t devaddress = 0;
+  uint32_t xfermode = 0;
 
-    /* Clear ADDR flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+  /* Process Locked */
+  __HAL_LOCK(hfmpi2c);
 
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+  if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
 
-    if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+    /* Set corresponding Error Code */
+    hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+    
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    FMPI2C_Flush_TXDR(hfmpi2c);
+  }
+  else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI);
+    
+    if(hfmpi2c->XferCount != 0)
     {
-      hfmpi2c->XferOptions = 0U;
-      hfmpi2c->PreviousState = hfmpi2c->State;
+      /* Recover Slave address */
+      devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+      
+      /* Prepare the new XferSize to transfer */
+      if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = FMPI2C_RELOAD_MODE;
+      }
+      else
+      {
+        hfmpi2c->XferSize = hfmpi2c->XferCount;
+        xfermode = FMPI2C_AUTOEND_MODE;
+      }
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hfmpi2c);
+      /* Set the new XferSize in Nbytes register */
+      FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
 
-      /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
-      HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+      /* Update XferCount value */
+      hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+      /* Enable DMA Request */
+      if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+      {
+        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+      }
     }
     else
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hfmpi2c);
-
-      /* Call the Slave Tx Complete callback */
-      HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
     }
   }
+  else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+  {
+    /* Call FMPI2C Master complete process */
+    FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hfmpi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified FMPI2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) 
+{
+  /* Process locked */
+  __HAL_LOCK(hfmpi2c);
+  
+  if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+  {
+    /* Check that FMPI2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if(FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0)
+    {
+      /* Clear NACK Flag */
+      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+      
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+    }
+  }
+  else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+  {
+    /* Clear ADDR flag */
+    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+  }
+  else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+  {
+    /* Call FMPI2C Slave complete process */
+    FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+  }
 
   /* Process Unlocked */
   __HAL_UNLOCK(hfmpi2c);
@@ -3691,14 +3570,15 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
   * @param  MemAddress Internal memory address
   * @param  MemAddSize Size of internal memory address
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
 
   /* Wait until TXIS flag is set */
-  if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+  if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
   {
     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
     {
@@ -3723,7 +3603,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXIS flag is set */
-    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -3734,13 +3614,13 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Send LSB of Memory Address */
     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
   }
 
   /* Wait until TCR flag is set */
-  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -3756,14 +3636,15 @@ return HAL_OK;
   * @param  MemAddress Internal memory address
   * @param  MemAddSize Size of internal memory address
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
 
   /* Wait until TXIS flag is set */
-  if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+  if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
   {
     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
     {
@@ -3786,9 +3667,9 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
   {
     /* Send MSB of Memory Address */
     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
-    
+
     /* Wait until TXIS flag is set */
-    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
+    if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
     {
       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
       {
@@ -3799,20 +3680,553 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
         return HAL_TIMEOUT;
       }
     }
-
+    
     /* Send LSB of Memory Address */
     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
   }
 
   /* Wait until TC flag is set */
-  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
-
+  
   return HAL_OK;
 }
 
+/**
+  * @brief  FMPI2C Address complete process callback.
+  * @param  hfmpi2c FMPI2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection = 0;
+  uint16_t slaveaddrcode = 0;
+  uint16_t ownadd1code = 0;
+  uint16_t ownadd2code = 0;
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+  {
+    transferdirection = FMPI2C_GET_DIR(hfmpi2c);
+    slaveaddrcode     = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
+    ownadd1code       = FMPI2C_GET_OWN_ADDRESS1(hfmpi2c);
+    ownadd2code       = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c);
+
+    /* If 10bits addressing mode is selected */
+    if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+    {
+      if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hfmpi2c->AddrEventCount++;
+        if(hfmpi2c->AddrEventCount == 2)
+        {
+          /* Reset Address Event counter  */
+          hfmpi2c->AddrEventCount = 0;
+
+          /* Clear ADDR flag */
+          __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hfmpi2c);
+
+          /* Call Slave Addr callback */
+          HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hfmpi2c);
+
+        /* Call Slave Addr callback */
+        HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      /* Call Slave Addr callback */
+      HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+  }
+}
+
+/**
+  * @brief  FMPI2C Master sequential complete process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @retval None
+  */
+static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+  /* Reset FMPI2C handle mode */
+  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when FMPI2C_AUTOEND_MODE enable */
+  if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+  {
+    hfmpi2c->State         = HAL_FMPI2C_STATE_READY;
+    hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
+    hfmpi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+  }
+  /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
+  else
+  {
+    hfmpi2c->State         = HAL_FMPI2C_STATE_READY;
+    hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
+    hfmpi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+  }
+}
+
+/**
+  * @brief  FMPI2C Slave sequential complete process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @retval None
+  */
+static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+  /* Reset FMPI2C handle mode */
+  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+  
+  if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
+    hfmpi2c->State         = HAL_FMPI2C_STATE_LISTEN;
+    hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+    HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+  }
+
+  else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */
+    hfmpi2c->State         = HAL_FMPI2C_STATE_LISTEN;
+    hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the Rx complete callback to inform upper layer of the end of receive process */
+    HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+  }
+}
+
+/**
+  * @brief  FMPI2C Master complete process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+  /* Clear STOP Flag */
+  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+  /* Clear Configuration Register 2 */
+  FMPI2C_RESET_CR2(hfmpi2c);
+
+  /* Reset handle parameters */
+  hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+  hfmpi2c->XferISR       = NULL;
+  hfmpi2c->XferOptions   = FMPI2C_NO_OPTION_FRAME;
+
+  if((ITFlags & FMPI2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+  }
+
+  /* Flush TX register */
+  FMPI2C_Flush_TXDR(hfmpi2c);
+  
+  /* Disable Interrupts */
+  FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT| FMPI2C_XFER_RX_IT);
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+  }
+  /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX */
+  else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+    
+    if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
+    {
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+    }
+    else
+    {
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+    }
+  }
+  /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
+  else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+    
+    if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
+    {
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+    }
+    else
+    {
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hfmpi2c);
+
+      HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+    }
+  }
+}
+
+/**
+  * @brief  FMPI2C Slave complete process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+  /* Clear STOP Flag */
+  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+  /* Clear ADDR flag */
+  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+
+  /* Disable all interrupts */
+  FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
+
+  /* Disable Address Acknowledge */
+  hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  FMPI2C_RESET_CR2(hfmpi2c);
+
+  /* Flush TX register */
+  FMPI2C_Flush_TXDR(hfmpi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if(((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) ||
+     ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN))
+  {
+    hfmpi2c->XferCount = FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c);
+  }
+  
+  /* All data are not transferred, so set error code accordingly */
+  if(hfmpi2c->XferCount != 0)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+  }
+  
+  /* Store Last receive data if any */
+  if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+    
+    if((hfmpi2c->XferSize > 0))
+    {
+      hfmpi2c->XferSize--;
+      hfmpi2c->XferCount--;
+      
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+    }
+  }
+  
+  hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+  hfmpi2c->XferISR = NULL;
+  
+  if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
+    {
+      /* Call FMPI2C Listen complete process */
+      FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+    }
+  }
+  else if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+  {
+    hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the Slave Rx Complete callback */
+    HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+  }
+  else
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the Slave Tx Complete callback */
+    HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+  }
+}
+           
+/**
+  * @brief  FMPI2C Listen complete process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
+  hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+  hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+  hfmpi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+    
+    if((hfmpi2c->XferSize > 0))
+    {
+      hfmpi2c->XferSize--;
+      hfmpi2c->XferCount--;
+      
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hfmpi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+  HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+}
+
+/**
+  * @brief  FMPI2C interrupts error process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
+{
+  /* Reset handle parameters */
+  hfmpi2c->Mode          = HAL_FMPI2C_MODE_NONE;
+  hfmpi2c->XferOptions   = FMPI2C_NO_OPTION_FRAME;
+  hfmpi2c->XferCount     = 0;
+
+  /* Set new error code */
+  hfmpi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)         ||
+     (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
+     (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+    
+    /* keep HAL_FMPI2C_STATE_LISTEN if set */
+    hfmpi2c->State         = HAL_FMPI2C_STATE_LISTEN;
+    hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+    hfmpi2c->XferISR       = FMPI2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
+    
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if(hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
+    {
+      /* Set HAL_FMPI2C_STATE_READY */
+      hfmpi2c->State         = HAL_FMPI2C_STATE_READY;
+    }
+    hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+    hfmpi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+  {
+    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+    /* Set the FMPI2C DMA Abort callback : 
+       will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+    hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    if(HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+    {
+      /* Call Directly XferAbortCallback function in case of error */
+      hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+  {
+    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+    /* Set the FMPI2C DMA Abort callback : 
+       will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+    hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    if(HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+    {
+      /* Call Directly XferAbortCallback function in case of error */
+      hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+    }
+  }
+  else if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hfmpi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_ErrorCallback(hfmpi2c);
+  }
+}
+
+/**
+  * @brief  FMPI2C Tx data register flush process.
+  * @param  hfmpi2c FMPI2C handle.
+  * @retval None
+  */
+static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
+  {
+     hfmpi2c->Instance->TXDR = 0x00;
+  }
+
+  /* Flush TX register if not empty */
+  if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
+  {
+    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
+  }
+}
+
 /**
   * @brief  DMA FMPI2C master transmit process complete callback.
   * @param  hdma DMA handle
@@ -3820,372 +4234,92 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
   */
 static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  uint16_t DevAddress;
   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-  if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; 
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */ 
-      if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-      {
-        if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-        }
-        else
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      hfmpi2c->XferCount = 0U;
-
-      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
-      hfmpi2c->XferCount -= hfmpi2c->XferSize;
-      if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hfmpi2c->XferSize = MAX_NBYTE_SIZE;
-      }
-      else
-      {
-        hfmpi2c->XferSize = hfmpi2c->XferCount;
-      }
-
-      DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
-      
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-      if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-      }
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-      }  
-
-      /* Wait until TXIS flag is set */
-      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-        {
-          if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-          }
-          else
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        FMPI2C_RESET_CR2(hfmpi2c);
-
-        hfmpi2c->XferCount = 0U;
-      
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-        HAL_FMPI2C_ErrorCallback(hfmpi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-    {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-      }
-      else
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    FMPI2C_RESET_CR2(hfmpi2c);
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; 
-
-    hfmpi2c->XferCount = 0U;
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-   /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA FMPI2C slave transmit process complete callback. 
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) 
-{
-  FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Wait until STOP flag is set */
-  if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-  {
-    if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-    {
-      /* Normal Use case, a AF is generated by master */
-      /* to inform slave the end of transfer */
-      hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-    }
-    else
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-  }
-
-  /* Clear STOP flag */
-  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
-
-  /* Wait until BUSY flag is reset */ 
-  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
-  {
-    hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-  }
 
   /* Disable DMA Request */
   hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
 
-  hfmpi2c->XferCount = 0U;
-
-  hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-  /* Check if Errors has been detected during transfer */
-  if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+  /* If last transfer, enable STOP interrupt */
+  if(hfmpi2c->XferCount == 0)
   {
-    HAL_FMPI2C_ErrorCallback(hfmpi2c);
+    /* Enable STOP interrupt */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
   }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
   else
   {
-    HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+    /* Update Buffer pointer */
+    hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+    /* Enable TC interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
   }
 }
 
 /**
-  * @brief DMA FMPI2C master receive process complete callback 
+  * @brief  DMA FMPI2C slave transmit process complete callback.
   * @param  hdma DMA handle
   * @retval None
   */
-static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) 
+static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* No specific action, Master fully manage the generation of STOP condition */
+  /* Mean that this generation can arrive at any time, at the end or during DMA process */
+  /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+  * @brief DMA FMPI2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
 {
   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  uint16_t DevAddress;
 
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-  if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
+  /* Disable DMA Request */
+  hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if(hfmpi2c->XferCount == 0)
   {
-    /* Wait until TCR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; 
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */ 
-      if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-      {
-        if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-        }
-        else
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-          
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      hfmpi2c->XferCount = 0U;
-
-      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
-      hfmpi2c->XferCount -= hfmpi2c->XferSize;
-      if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hfmpi2c->XferSize = MAX_NBYTE_SIZE;
-      }
-      else
-      {
-        hfmpi2c->XferSize = hfmpi2c->XferCount;
-      }
-
-      DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
-      
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-      if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-      }
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-      }  
-
-      /* Wait until RXNE flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-
-      /* Check if Errors has been detected during transfer */
-      if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-        {
-          if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-          }
-          else
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        FMPI2C_RESET_CR2(hfmpi2c);
-
-        hfmpi2c->XferCount = 0U;
-
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-        hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-        HAL_FMPI2C_ErrorCallback(hfmpi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
-      }
-    }
+    /* Enable STOP interrupt */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
   }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
   else
   {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
+    /* Update Buffer pointer */
+    hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
     {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-      }
-      else
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    FMPI2C_RESET_CR2(hfmpi2c);
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
-
-    hfmpi2c->XferCount = 0U;
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
+      hfmpi2c->XferSize = MAX_NBYTE_SIZE;
     }
     else
     {
-      HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+      hfmpi2c->XferSize = hfmpi2c->XferCount;
     }
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
+
+    /* Enable TC interrupts */
+    FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
   }
 }
 
@@ -4194,381 +4328,15 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
   * @param  hdma DMA handle
   * @retval None
   */
-static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) 
+static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until STOPF flag is reset */ 
-  if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-  {
-    if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-    }
-    else
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-  }
-
-  /* Clear STOPF flag */
-  __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-  /* Wait until BUSY flag is reset */ 
-  if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
-
-  {
-    hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-  }
-  
-  /* Disable DMA Request */
-  hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; 
-
-  /* Disable Address Acknowledge */
-  hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-
-  hfmpi2c->XferCount = 0U;
-  
-  hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-  /* Check if Errors has been detected during transfer */
-  if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-  {
-    HAL_FMPI2C_ErrorCallback(hfmpi2c);
-  }
-  else
-  {
-    HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
-  }
+  /* No specific action, Master fully manage the generation of STOP condition */
+  /* Mean that this generation can arrive at any time, at the end or during DMA process */
+  /* So STOP condition should be manage through Interrupt treatment */
 }
 
 /**
-  * @brief DMA FMPI2C Memory Write process complete callback 
-  * @param hdma DMA handle
-  * @retval None
-  */
-static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  uint16_t DevAddress;
-  FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-  if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
-    
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */ 
-      if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-      {
-        if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-        }
-        else
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      hfmpi2c->XferCount = 0U;
-
-      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
-      hfmpi2c->XferCount -= hfmpi2c->XferSize;
-      if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hfmpi2c->XferSize = MAX_NBYTE_SIZE;
-      }
-      else
-      {
-        hfmpi2c->XferSize = hfmpi2c->XferCount;
-      }
-
-      DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
-      
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-      if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-      }
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-      }
-
-      /* Wait until TXIS flag is set */
-      if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-        {
-          if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-          }
-          else
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-        /* Clear Configuration Register 2 */
-        FMPI2C_RESET_CR2(hfmpi2c);
-
-        hfmpi2c->XferCount = 0U;
-
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-        hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-        HAL_FMPI2C_ErrorCallback(hfmpi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-    {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-      }
-      else
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    FMPI2C_RESET_CR2(hfmpi2c);
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
-  
-    hfmpi2c->XferCount = 0U;
-  
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA FMPI2C Memory Read process complete callback
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint16_t DevAddress;
-
-  /* Check if last DMA request was done with RELOAD */
-  /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-  if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-  {
-    /* Wait until TCR flag is set */
-    if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
-    {
-      hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-    }
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; 
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-      /* Wait until STOPF flag is reset */ 
-      if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-      {
-        if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-        }
-        else
-        {
-          hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-        }
-      }
-
-      /* Clear STOP Flag */
-      __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-          
-      /* Clear Configuration Register 2 */
-      FMPI2C_RESET_CR2(hfmpi2c);
-
-      hfmpi2c->XferCount = 0U;
-
-      hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
-      hfmpi2c->XferCount -= hfmpi2c->XferSize;
-      if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
-      {
-        hfmpi2c->XferSize = MAX_NBYTE_SIZE;
-      }
-      else
-      {
-        hfmpi2c->XferSize = hfmpi2c->XferCount;
-      }
-
-      DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
-      
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
-      if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
-      }
-      else
-      {
-        FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
-      }
-
-      /* Wait until RXNE flag is set */
-      if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-
-      /* Check if Errors has been detected during transfer */
-      if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-      {
-        /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-        /* Wait until STOPF flag is reset */ 
-        if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-        {
-          if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-          }
-          else
-          {
-            hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-          }
-        }
-
-        /* Clear STOP Flag */
-        __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-            
-        /* Clear Configuration Register 2 */
-        FMPI2C_RESET_CR2(hfmpi2c);
-
-        hfmpi2c->XferCount = 0U;
-
-        hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-        hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-        HAL_FMPI2C_ErrorCallback(hfmpi2c);
-      }
-      else
-      {
-        /* Enable DMA Request */
-        hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
-      }
-    }
-  }
-  else
-  {
-    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
-    /* Wait until STOPF flag is reset */ 
-    if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
-    {
-      if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-      }
-      else
-      {
-        hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
-      }
-    }
-
-    /* Clear STOP Flag */
-    __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
-    /* Clear Configuration Register 2 */
-    FMPI2C_RESET_CR2(hfmpi2c);
-
-    /* Disable DMA Request */
-    hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
-
-    hfmpi2c->XferCount = 0U;
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
-    /* Check if Errors has been detected during transfer */
-    if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
-    {
-      HAL_FMPI2C_ErrorCallback(hfmpi2c);
-    }
-    else
-    {
-      HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
-    }
-  }
-}
-
-/**
-  * @brief  DMA FMPI2C communication error callback. 
+  * @brief  DMA FMPI2C communication error callback.
   * @param hdma DMA handle
   * @retval None
   */
@@ -4579,14 +4347,40 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
   /* Disable Acknowledge */
   hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
 
-  hfmpi2c->XferCount = 0U;
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+}
 
-  hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-  hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+/**
+  * @brief DMA FMPI2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma: DMA handle.
+  * @retval None
+  */
+static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
-  hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+  /* Disable Acknowledge */
+  hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
 
-  HAL_FMPI2C_ErrorCallback(hfmpi2c);
+  /* Reset AbortCpltCallback */
+  hfmpi2c->hdmatx->XferAbortCallback = NULL;
+  hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if come from abort from user */
+  if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+  {
+    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+    
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+  }
+  else
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_FMPI2C_ErrorCallback(hfmpi2c);
+  }
 }
 
 /**
@@ -4596,44 +4390,24 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
   * @param  Flag Specifies the FMPI2C flag to check.
   * @param  Status The new Flag status (SET or RESET).
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = HAL_GetTick();
+  while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
+      {
+        hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+        hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
 
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-        {
-          hfmpi2c->State= HAL_FMPI2C_STATE_READY;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-        {
-          hfmpi2c->State= HAL_FMPI2C_STATE_READY;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hfmpi2c);
-          return HAL_TIMEOUT;
-        }
+        /* Process Unlocked */
+        __HAL_UNLOCK(hfmpi2c);
+        return HAL_TIMEOUT;
       }
     }
   }
@@ -4645,16 +4419,15 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = HAL_GetTick();
-
   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
   {
     /* Check if a NACK is detected */
-    if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+    if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
@@ -4662,10 +4435,11 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
       {
         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
         hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+        hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
 
         /* Process Unlocked */
         __HAL_UNLOCK(hfmpi2c);
@@ -4682,26 +4456,25 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0x00U;
-  tickstart = HAL_GetTick();
-
   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
   {
     /* Check if a NACK is detected */
-    if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
+    if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
     {
       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hfmpi2c);
@@ -4717,15 +4490,19 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0x00U;
-  tickstart = HAL_GetTick();
-
   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
   {
+    /* Check if a NACK is detected */
+    if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
     /* Check if a STOPF is detected */
     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
     {
@@ -4737,6 +4514,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
 
       hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+      hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hfmpi2c);
@@ -4745,7 +4523,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
     {
       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
@@ -4764,27 +4542,13 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
   *                the configuration information for the specified FMPI2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0x00U;
-  tickstart = HAL_GetTick();
-
   if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
   {
-    /* Generate stop if necessary only in case of FMPI2C peripheral in MASTER mode or MEMORY mode */
-     if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
-    {
-      /* No need to generate the STOP condition if AUTOEND mode is enabled */
-      /* Generate the STOP condition only in case of SOFTEND mode is enabled */
-      if((hfmpi2c->Instance->CR2 & FMPI2C_AUTOEND_MODE) != FMPI2C_AUTOEND_MODE)
-      {
-        /* Generate Stop */
-        hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
-      }
-    }
-
     /* Wait until STOP Flag is reset */
     /* AutoEnd should be initiate after AF */
     while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
@@ -4792,9 +4556,11 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
       {
-        if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
         {
           hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+          hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
           /* Process Unlocked */
           __HAL_UNLOCK(hfmpi2c);
           return HAL_TIMEOUT;
@@ -4808,11 +4574,15 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
     /* Clear STOP Flag */
     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
 
+    /* Flush TX register */
+    FMPI2C_Flush_TXDR(hfmpi2c);
+
     /* Clear Configuration Register 2 */
     FMPI2C_RESET_CR2(hfmpi2c);
 
     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
     hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+    hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hfmpi2c);
@@ -4843,7 +4613,7 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
   */
 static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
 {
-  uint32_t tmpreg = 0U;
+  uint32_t tmpreg = 0;
 
   /* Check the parameters */
   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
@@ -4852,14 +4622,14 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAd
 
   /* Get the CR2 register value */
   tmpreg = hfmpi2c->Instance->CR2;
-  
+
   /* clear tmpreg specific bits */
   tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
 
   /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16U) & FMPI2C_CR2_NBYTES) | \
+  tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16 ) & FMPI2C_CR2_NBYTES) | \
             (uint32_t)Mode | (uint32_t)Request);
-  
+
   /* update CR2 register */
   hfmpi2c->Instance->CR2 = tmpreg;
 }
@@ -4873,26 +4643,62 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAd
   */
 static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
 {
-  uint32_t tmpisr = 0U;
+  uint32_t tmpisr = 0;
+
+  if((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \
+     (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA))
+  {
+    if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+    }
+
+    if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
+    }
+
+    if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= FMPI2C_IT_STOPI;
+    }
+    
+    if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= FMPI2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+    }
+
+    if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
+    }
+
+    if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
+    }
+
+    if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= FMPI2C_IT_STOPI;
+    }
+  }
   
-  if((InterruptRequest & FMPI2C_IT_ADDR) == FMPI2C_IT_ADDR)
-  {
-    /* Enable ADDR and STOP interrupt */
-    tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
-  }
-
-  if((InterruptRequest & FMPI2C_IT_TX) == FMPI2C_IT_TX)
-  {
-    /* Enable ERR, TC, STOP, NACK and RXI interrupt */
-    tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
-  }
-
-  if((InterruptRequest & FMPI2C_IT_RX) == FMPI2C_IT_RX)
-  {
-    /* Enable ERR, TC, STOP, NACK and TXI interrupt */
-    tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
-  }
-
   /* Enable interrupts only at the end */
   /* to avoid the risk of FMPI2C interrupt handle execution before */
   /* all interrupts requested done */
@@ -4910,21 +4716,21 @@ static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16
   */
 static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
 {
-  uint32_t tmpisr = 0U;
+  uint32_t tmpisr = 0;
 
-  if((InterruptRequest & FMPI2C_IT_TX) == FMPI2C_IT_TX)
+  if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
   {
     /* Disable TC and TXI interrupts */
     tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI;
-    
+
     if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
     {
       /* Disable NACK and STOP interrupts */
-      tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
+      tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
     }
   }
 
-  if((InterruptRequest & FMPI2C_IT_RX) == FMPI2C_IT_RX)
+  if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
   {
     /* Disable TC and RXI interrupts */
     tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI;
@@ -4932,28 +4738,46 @@ static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint1
     if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
     {
       /* Disable NACK and STOP interrupts */
-      tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
+      tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
     }
   }
 
-  if((InterruptRequest & FMPI2C_IT_ADDR) == FMPI2C_IT_ADDR)
+  if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
   {
     /* Disable ADDR, NACK and STOP interrupts */
-    tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
+    tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
+  }
+
+  if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
+  }
+
+  if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= FMPI2C_IT_STOPI;
+  }
+  
+  if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= FMPI2C_IT_TCI;
   }
 
   /* Disable interrupts only at the end */
   /* to avoid a breaking situation like at "t" time */
   /* all disable interrupts request are not done */
   __HAL_FMPI2C_DISABLE_IT(hfmpi2c, tmpisr);
-  
+
   return HAL_OK;
 }
 
 /**
   * @}
   */
-#endif /* STM32F410xx || STM32F446xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 #endif /* HAL_FMPI2C_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h
index a395ebbd0a..082462bc65 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_fmpi2c.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FMPI2C HAL module.
   ******************************************************************************
   * @attention
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_FMPI2C_H
@@ -43,7 +43,8 @@
  extern "C" {
 #endif
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"  
@@ -56,7 +57,7 @@
   * @{
   */ 
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
   * @{
   */
@@ -75,22 +76,22 @@ typedef struct
                                   This parameter can be a 7-bit or 10-bit address. */
 
   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref FMPI2C_addressing_mode */
+                                  This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */
 
   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref FMPI2C_dual_addressing_mode */
+                                  This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */
 
   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
                                   This parameter can be a 7-bit address. */
 
   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                  This parameter can be a value of @ref FMPI2C_own_address2_masks */
+                                  This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */
 
   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref FMPI2C_general_call_addressing_mode */
+                                  This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */
 
   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref FMPI2C_nostretch_mode */
+                                  This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */
 
 }FMPI2C_InitTypeDef;
 
@@ -99,28 +100,71 @@ typedef struct
   */
 
 /** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition  
+  * @brief  HAL State structure definition
+  * @note  HAL FMPI2C State value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : Abort (Abort user request on going)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)
+  *          b4     (not used)
+  *             x  : Should be set to 0
+  *          b3
+  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             1  : Listen (IP in Address Listen Mode)
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
   * @{
   */ 
-
 typedef enum
 {
   HAL_FMPI2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
   HAL_FMPI2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
   HAL_FMPI2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_FMPI2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_FMPI2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */ 
   HAL_FMPI2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
   HAL_FMPI2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
   HAL_FMPI2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                            */
+                                                 process is ongoing                        */
   HAL_FMPI2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                            */
+                                                 process is ongoing                        */
+  HAL_FMPI2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
   HAL_FMPI2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_FMPI2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+  HAL_FMPI2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */ 
+
 }HAL_FMPI2C_StateTypeDef;
 
 /**
-  * @brief  HAL State structures definition
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL FMPI2C Mode value coding follow below described bitmap :
+  *          b7     (not used)
+  *             x  : Should be set to 0
+  *          b6
+  *             0  : None
+  *             1  : Memory (HAL FMPI2C communication is in Memory Mode)
+  *          b5
+  *             0  : None
+  *             1  : Slave (HAL FMPI2C communication is in Slave Mode)
+  *          b4
+  *             0  : None
+  *             1  : Master (HAL FMPI2C communication is in Master Mode)
+  *          b3-b2-b1-b0  (not used)
+  *             xxxx : Should be set to 0000
+  * @{
   */
 typedef enum
 {
@@ -131,71 +175,62 @@ typedef enum
 
 }HAL_FMPI2C_ModeTypeDef;
 
-/**
+/** 
   * @}
   */
 
 /** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
   * @brief  FMPI2C Error Code definition  
   * @{
-  */  
-#define HAL_FMPI2C_ERROR_NONE              ((uint32_t)0x00000000U)    /*!< No error              */
-#define HAL_FMPI2C_ERROR_BERR              ((uint32_t)0x00000001U)    /*!< BERR error            */
-#define HAL_FMPI2C_ERROR_ARLO              ((uint32_t)0x00000002U)    /*!< ARLO error            */
-#define HAL_FMPI2C_ERROR_AF                ((uint32_t)0x00000004U)    /*!< ACKF error            */
-#define HAL_FMPI2C_ERROR_OVR               ((uint32_t)0x00000008U)    /*!< OVR error             */
-#define HAL_FMPI2C_ERROR_DMA               ((uint32_t)0x00000010U)    /*!< DMA transfer error    */
-#define HAL_FMPI2C_ERROR_TIMEOUT           ((uint32_t)0x00000020U)    /*!< Timeout error         */
-#define HAL_FMPI2C_ERROR_SIZE              ((uint32_t)0x00000040U)    /*!< Size Management error */
+  */
+#define HAL_FMPI2C_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */
+#define HAL_FMPI2C_ERROR_BERR      ((uint32_t)0x00000001U)    /*!< BERR error            */
+#define HAL_FMPI2C_ERROR_ARLO      ((uint32_t)0x00000002U)    /*!< ARLO error            */
+#define HAL_FMPI2C_ERROR_AF        ((uint32_t)0x00000004U)    /*!< ACKF error            */
+#define HAL_FMPI2C_ERROR_OVR       ((uint32_t)0x00000008U)    /*!< OVR error             */
+#define HAL_FMPI2C_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error    */
+#define HAL_FMPI2C_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */
+#define HAL_FMPI2C_ERROR_SIZE      ((uint32_t)0x00000040U)    /*!< Size Management error */
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_XferOptions_definition  FMPI2C XferOptions definition
-  * @{
-  */
-#define FMPI2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000U)
-#define FMPI2C_FIRST_FRAME                 ((uint32_t)FMPI2C_SOFTEND_MODE)
-#define FMPI2C_NEXT_FRAME                  ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
-#define FMPI2C_FIRST_AND_LAST_FRAME        ((uint32_t)FMPI2C_AUTOEND_MODE) 
-#define FMPI2C_LAST_FRAME                  ((uint32_t)FMPI2C_AUTOEND_MODE)
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition 
+/** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
   * @brief  FMPI2C handle Structure definition  
   * @{
   */
-typedef struct
+typedef struct __FMPI2C_HandleTypeDef
 {
-  FMPI2C_TypeDef                *Instance;    /*!< FMPI2C registers base address     */
+  FMPI2C_TypeDef                *Instance;      /*!< FMPI2C registers base address                */
 
-  FMPI2C_InitTypeDef            Init;         /*!< FMPI2C communication parameters   */
+  FMPI2C_InitTypeDef            Init;           /*!< FMPI2C communication parameters              */
 
-  uint8_t                    *pBuffPtr;       /*!< Pointer to FMPI2C transfer buffer */
+  uint8_t                    *pBuffPtr;         /*!< Pointer to FMPI2C transfer buffer            */
 
-  uint16_t                   XferSize;        /*!< FMPI2C transfer size              */
+  uint16_t                   XferSize;          /*!< FMPI2C transfer size                         */
 
-  __IO uint16_t              XferCount;       /*!< FMPI2C transfer counter           */
+  __IO uint16_t              XferCount;         /*!< FMPI2C transfer counter                      */
 
-  __IO uint32_t              XferOptions;     /*!< FMPI2C transfer options           */
+  __IO uint32_t              XferOptions;       /*!< FMPI2C sequantial transfer options, this parameter can
+                                                  be a value of @ref FMPI2C_XFEROPTIONS */
 
-  __IO uint32_t              PreviousState;   /*!< FMPI2C communication Previous state */
+  __IO uint32_t              PreviousState;     /*!< FMPI2C communication Previous state          */
 
-  DMA_HandleTypeDef          *hdmatx;         /*!< FMPI2C Tx DMA handle parameters   */
+  HAL_StatusTypeDef (*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */
 
-  DMA_HandleTypeDef          *hdmarx;         /*!< FMPI2C Rx DMA handle parameters   */
+  DMA_HandleTypeDef          *hdmatx;           /*!< FMPI2C Tx DMA handle parameters              */
 
-  HAL_LockTypeDef            Lock;            /*!< FMPI2C locking object             */
+  DMA_HandleTypeDef          *hdmarx;           /*!< FMPI2C Rx DMA handle parameters              */
 
-  __IO HAL_FMPI2C_StateTypeDef  State;           /*!< FMPI2C communication state     */
+  HAL_LockTypeDef            Lock;              /*!< FMPI2C locking object                        */
 
-  __IO HAL_FMPI2C_ModeTypeDef   Mode;            /*!< FMPI2C communication mode      */
+  __IO HAL_FMPI2C_StateTypeDef  State;          /*!< FMPI2C communication state                   */
 
-  __IO uint32_t              ErrorCode;       /*!< FMPI2C Error code                 */
+  __IO HAL_FMPI2C_ModeTypeDef   Mode;           /*!< FMPI2C communication mode                    */
 
-  __IO uint32_t              AddrEventCount;  /*!< FMPI2C Address Event counter     */
+  __IO uint32_t              ErrorCode;         /*!< FMPI2C Error code                            */
+
+  __IO uint32_t              AddrEventCount;    /*!< FMPI2C Address Event counter                 */
 }FMPI2C_HandleTypeDef;
 /**
   * @}
@@ -210,28 +245,37 @@ typedef struct
   * @{
   */
 
-/** @defgroup FMPI2C_addressing_mode FMPI2C addressing mode
+/** @defgroup FMPI2C_XFEROPTIONS  FMPI2C Sequential Transfer Options
   * @{
   */
-#define FMPI2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U) 
-#define FMPI2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)
-
+#define FMPI2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000U)
+#define FMPI2C_FIRST_FRAME                 ((uint32_t)FMPI2C_SOFTEND_MODE)
+#define FMPI2C_NEXT_FRAME                  ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
+#define FMPI2C_FIRST_AND_LAST_FRAME        ((uint32_t)FMPI2C_AUTOEND_MODE)
+#define FMPI2C_LAST_FRAME                  ((uint32_t)FMPI2C_AUTOEND_MODE)
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_dual_addressing_mode FMPI2C dual addressing mode
+/** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode
   * @{
   */
+#define FMPI2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U)
+#define FMPI2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)
+/**
+  * @}
+  */
 
+/** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode
+  * @{
+  */
 #define FMPI2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)
 #define FMPI2C_DUALADDRESS_ENABLE          FMPI2C_OAR2_OA2EN
-
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_own_address2_masks FMPI2C own address2 masks
+/** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
   * @{
   */
 
@@ -248,27 +292,25 @@ typedef struct
   * @}
   */
 
-/** @defgroup FMPI2C_general_call_addressing_mode FMPI2C general call addressing mode
+/** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode
   * @{
   */
 #define FMPI2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)
 #define FMPI2C_GENERALCALL_ENABLE          FMPI2C_CR1_GCEN
-
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_nostretch_mode FMPI2C nostretch mode
+/** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode
   * @{
   */
 #define FMPI2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)
 #define FMPI2C_NOSTRETCH_ENABLE            FMPI2C_CR1_NOSTRETCH
-
 /**
   * @}
   */
 
-/** @defgroup FMPI2C_Memory_Address_Size FMPI2C Memory Address Size
+/** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size
   * @{
   */
 #define FMPI2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
@@ -277,8 +319,8 @@ typedef struct
 /**
   * @}
   */
-
-/** @defgroup FMPI2C_XferDirection_definition FMPI2C XferDirection definition
+  
+/** @defgroup FMPI2C_XferDirection FMPI2C Transfer Direction
   * @{
   */
 #define FMPI2C_DIRECTION_RECEIVE           ((uint32_t)0x00000000U)
@@ -288,7 +330,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup FMPI2C_ReloadEndMode_definition FMPI2C ReloadEndMode definition
+/** @defgroup FMPI2C_RELOAD_END_MODE FMPI2C Reload End Mode
   * @{
   */
 #define  FMPI2C_RELOAD_MODE                FMPI2C_CR2_RELOAD
@@ -299,7 +341,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup FMPI2C_StartStopMode_definition FMPI2C StartStopMode definition
+/** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode
   * @{
   */
 
@@ -325,18 +367,13 @@ typedef struct
 #define FMPI2C_IT_ADDRI                    FMPI2C_CR1_ADDRIE
 #define FMPI2C_IT_RXI                      FMPI2C_CR1_RXIE
 #define FMPI2C_IT_TXI                      FMPI2C_CR1_TXIE
-#define FMPI2C_IT_TX                       (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)
-#define FMPI2C_IT_RX                       (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI)
-#define FMPI2C_IT_ADDR                     (FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI)
-
 /**
   * @}
   */
 
-
 /** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
   * @{
-  */
+  */ 
 #define FMPI2C_FLAG_TXE                    FMPI2C_ISR_TXE
 #define FMPI2C_FLAG_TXIS                   FMPI2C_ISR_TXIS
 #define FMPI2C_FLAG_RXNE                   FMPI2C_ISR_RXNE
@@ -362,6 +399,7 @@ typedef struct
   */
 
 /* Exported macros -----------------------------------------------------------*/
+  
 /** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
   * @{
   */
@@ -370,12 +408,12 @@ typedef struct
   * @param  __HANDLE__ specifies the FMPI2C Handle.
   * @retval None
   */
-#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
+#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
 
 /** @brief  Enable the specified FMPI2C interrupt.
   * @param  __HANDLE__ specifies the FMPI2C Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
@@ -383,16 +421,15 @@ typedef struct
   *            @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
   *            @arg @ref FMPI2C_IT_RXI   RX interrupt enable
   *            @arg @ref FMPI2C_IT_TXI   TX interrupt enable
-  *   
+  *
   * @retval None
   */
-
-#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
 
 /** @brief  Disable the specified FMPI2C interrupt.
   * @param  __HANDLE__ specifies the FMPI2C Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
@@ -403,12 +440,12 @@ typedef struct
   *   
   * @retval None
   */
-#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
  
 /** @brief  Check whether the specified FMPI2C interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the FMPI2C Handle.
-  * @param  __INTERRUPT__: specifies the FMPI2C interrupt source to check.
-  *         This parameter can be one of the following values:
+  * @param  __INTERRUPT__ specifies the FMPI2C interrupt source to check.
+  *          This parameter can be one of the following values:
   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
@@ -416,15 +453,15 @@ typedef struct
   *            @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
   *            @arg @ref FMPI2C_IT_RXI   RX interrupt enable
   *            @arg @ref FMPI2C_IT_TXI   TX interrupt enable
-  *   
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified FMPI2C flag is set or not.
   * @param  __HANDLE__ specifies the FMPI2C Handle.
   * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
+  *        This parameter can be one of the following values:
   *            @arg @ref FMPI2C_FLAG_TXE     Transmit data register empty
   *            @arg @ref FMPI2C_FLAG_TXIS    Transmit interrupt status
   *            @arg @ref FMPI2C_FLAG_RXNE    Receive data register not empty
@@ -435,17 +472,16 @@ typedef struct
   *            @arg @ref FMPI2C_FLAG_TCR     Transfer complete reload
   *            @arg @ref FMPI2C_FLAG_BERR    Bus error
   *            @arg @ref FMPI2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref FMPI2C_FLAG_OVR     Overrun/Underrun            
+  *            @arg @ref FMPI2C_FLAG_OVR     Overrun/Underrun
   *            @arg @ref FMPI2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
   *            @arg @ref FMPI2C_FLAG_ALERT   SMBus alert
   *            @arg @ref FMPI2C_FLAG_BUSY    Bus busy
   *            @arg @ref FMPI2C_FLAG_DIR     Transfer direction (slave mode)
-  *   
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define FMPI2C_FLAG_MASK  ((uint32_t)0x0001FFFFU)
-#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
+#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 
 /** @brief  Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
   * @param  __HANDLE__ specifies the FMPI2C Handle.
@@ -461,24 +497,29 @@ typedef struct
   *            @arg @ref FMPI2C_FLAG_PECERR  PEC error in reception
   *            @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
   *            @arg @ref FMPI2C_FLAG_ALERT   SMBus alert
-  *   
+  *
   * @retval None
   */
-#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
-                                                                                         ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
+#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ 
 /** @brief  Enable the specified FMPI2C peripheral.
-  * @param  __HANDLE__ specifies the FMPI2C Handle. 
+  * @param  __HANDLE__ specifies the FMPI2C Handle.
   * @retval None
   */
-#define __HAL_FMPI2C_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->CR1,  FMPI2C_CR1_PE))
+#define __HAL_FMPI2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  FMPI2C_CR1_PE))
 
 /** @brief  Disable the specified FMPI2C peripheral.
-  * @param  __HANDLE__ specifies the FMPI2C Handle. 
+  * @param  __HANDLE__ specifies the FMPI2C Handle.
   * @retval None
   */
-#define __HAL_FMPI2C_DISABLE(__HANDLE__)   (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+#define __HAL_FMPI2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
 
+/** @brief  Generate a Non-Acknowledge FMPI2C peripheral in Slave mode.
+  * @param  __HANDLE__: specifies the FMPI2C Handle. 
+  * @retval None
+  */
+#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
 /**
   * @}
   */
@@ -501,7 +542,7 @@ void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
   * @{
@@ -530,7 +571,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
 HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);    
+HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
 
  /******* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@@ -544,9 +585,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
   */
 
 /** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
- /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+ * @{
+ */
+/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -558,26 +599,27 @@ void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
   * @{
   */
-/* Peripheral State, Mode and Errors functions  *********************************/
+/* Peripheral State, Mode and Error functions  *********************************/
 HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c);
 HAL_FMPI2C_ModeTypeDef  HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c);
 uint32_t             HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */ 
-  
+
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
   * @{
@@ -605,54 +647,50 @@ uint32_t             HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
                                           ((MASK) == FMPI2C_OA2_MASK04) || \
                                           ((MASK) == FMPI2C_OA2_MASK05) || \
                                           ((MASK) == FMPI2C_OA2_MASK06) || \
-                                          ((MASK) == FMPI2C_OA2_MASK07))  
+                                          ((MASK) == FMPI2C_OA2_MASK07))
 
 #define IS_FMPI2C_GENERAL_CALL(CALL)       (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
-                                          ((CALL) == FMPI2C_GENERALCALL_ENABLE))
+                                         ((CALL) == FMPI2C_GENERALCALL_ENABLE))
 
 #define IS_FMPI2C_NO_STRETCH(STRETCH)      (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
-                                          ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
+                                         ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
 
 #define IS_FMPI2C_MEMADD_SIZE(SIZE)        (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
-                                          ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
+                                         ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
 
 #define IS_TRANSFER_MODE(MODE)          (((MODE) == FMPI2C_RELOAD_MODE)   || \
-                                          ((MODE) == FMPI2C_AUTOEND_MODE) || \
-                                          ((MODE) == FMPI2C_AUTOEND_MODE |FMPI2C_RELOAD_MODE) || \
-                                          ((MODE) == FMPI2C_SOFTEND_MODE))
+                                         ((MODE) == FMPI2C_AUTOEND_MODE) || \
+                                         ((MODE) == FMPI2C_SOFTEND_MODE))
 
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == FMPI2C_GENERATE_STOP)         || \
-                                          ((REQUEST) == FMPI2C_GENERATE_START_READ)  || \
-                                          ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
-                                          ((REQUEST) == FMPI2C_NO_STARTSTOP))
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == FMPI2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == FMPI2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == FMPI2C_NO_STARTSTOP))
 
-#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == FMPI2C_FIRST_FRAME)              || \
-                                                       ((REQUEST) == FMPI2C_NEXT_FRAME)               || \
-                                                       ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME)     || \
-                                                       ((REQUEST) == FMPI2C_LAST_FRAME))
+#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == FMPI2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == FMPI2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == FMPI2C_LAST_FRAME))
 
-#define FMPI2C_RESET_CR2(__HANDLE__)       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+#define FMPI2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
 
-#define FMPI2C_GET_ADDR_MATCH(__HANDLE__)                (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)
-#define FMPI2C_GET_DIR(__HANDLE__)                       (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
-#define FMPI2C_GET_STOP_MODE(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
-#define FMPI2C_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
-#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
-#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__)              ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
-#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__)              ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
+#define FMPI2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16)
+#define FMPI2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16)
+#define FMPI2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
+#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
+#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
 
+#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FFU)
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
 
-#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FFU)
-#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FFU)
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define FMPI2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
 
-#define FMPI2C_MEM_ADD_MSB(__ADDRESS__)    ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define FMPI2C_MEM_ADD_LSB(__ADDRESS__)    ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__)   (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
 /**
   * @}
-  */
+  */ 
 
 /* Private Functions ---------------------------------------------------------*/
 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
@@ -661,16 +699,16 @@ uint32_t             HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
 /* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */
 /**
   * @}
-  */
+  */ 
+
+/**
+  * @}
+  */ 
 
 /**
   * @}
   */
-
-/**
-  * @}
-  */
-#endif /* STM32F410xx || STM32F446xx */ 
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c
index 83b8bf66e9..52b400e1d8 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_fmpi2c_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FMPI2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of FMPI2C Extended peripheral:
@@ -77,7 +77,8 @@
 
 #ifdef HAL_FMPI2C_MODULE_ENABLED
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) 
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) 
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -201,85 +202,6 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c
   }
 }
 
-/**
-  * @brief  Enable FMPI2C wakeup from stop mode.
-  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified FMPI2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
-  
-  if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hfmpi2c);
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
-
-    /* Disable the selected FMPI2C peripheral */
-    __HAL_FMPI2C_DISABLE(hfmpi2c);  
-
-    /* Enable wakeup from stop mode */
-    hfmpi2c->Instance->CR1 |= FMPI2C_CR1_WUPEN;
-
-    __HAL_FMPI2C_ENABLE(hfmpi2c); 
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Disable FMPI2C wakeup from stop mode.
-  * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified FMPI2Cx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
-{
-  /* Check the parameters */
-  assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
-
-  if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hfmpi2c);
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
-
-    /* Disable the selected FMPI2C peripheral */
-    __HAL_FMPI2C_DISABLE(hfmpi2c);
-
-    /* Enable wakeup from stop mode */
-    hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_WUPEN);
-
-    __HAL_FMPI2C_ENABLE(hfmpi2c); 
-
-    hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmpi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
 /**
   * @brief Enable the FMPI2C fast mode plus driving capability.
   * @param ConfigFastModePlus Selects the pin.
@@ -323,7 +245,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
 /**
   * @}
   */
-#endif /* STM32F410xx || STM32F446xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 #endif /* HAL_FMPI2C_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h
index d458506e56..e5a7e2f023 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_fmpi2c_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FMPI2C HAL Extended module.
   ******************************************************************************
   * @attention
@@ -43,7 +43,8 @@
  extern "C" {
 #endif
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
@@ -100,8 +101,6 @@
 /* Peripheral Control functions  ************************************************/
 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
-HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c);
-HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c);
 void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
 void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 
@@ -153,7 +152,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 /**
   * @}
   */
-#endif /* STM32F410xx || STM32F446xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c
index 31e650805d..77d0d470db 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -163,8 +163,8 @@
   */
 
 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
+  *  @brief    Initialization and Configuration functions
+  *
 @verbatim    
  ===============================================================================
               ##### Initialization and de-initialization functions #####
@@ -373,8 +373,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
   */
 
 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
- *  @brief   GPIO Read and Write
- *
+  *  @brief   GPIO Read and Write
+  *
 @verbatim
  ===============================================================================
                        ##### IO operation functions #####
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h
index a334d2ab90..07cf800225 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h
index 6843c9216f..97135deb59 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
@@ -589,6 +589,113 @@
 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
 #endif /* STM32F401xC || STM32F401xE */
 /*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4/I2S4 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3        ((uint8_t)0x08U)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08U)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08U)  /* CAN1 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */  
+#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1        ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */
+#define GPIO_AF10_FMC           ((uint8_t)0x0AU)  /* FMC Alternate Function mapping    */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*---------------------------------------- STM32F411xx------------------------*/
 #if defined(STM32F411xE) 
 /** 
@@ -1080,7 +1187,7 @@
                                                ((__GPIOx__) == (GPIOE))? 4U : 5U)
 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
 
-#if defined(STM32F446xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
                                                ((__GPIOx__) == (GPIOB))? 1U :\
                                                ((__GPIOx__) == (GPIOC))? 2U :\
@@ -1088,7 +1195,7 @@
                                                ((__GPIOx__) == (GPIOE))? 4U :\
                                                ((__GPIOx__) == (GPIOF))? 5U :\
                                                ((__GPIOx__) == (GPIOG))? 6U : 8U)
-#endif /* STM32F446xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /**
   * @}
@@ -1305,6 +1412,12 @@
 #endif /* STM32F469xx || STM32F479xx */
 /*----------------------------------------------------------------------------*/
 
+/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
 /**
   * @}
   */ 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c
index 2fac77199e..142245ae5f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hash.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   HASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the HASH peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h
index a9bb69bfc2..14b03b8c27 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hash.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c
index d4eb41b8b5..72655e3214 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hash_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   HASH HAL Extension module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of HASH peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h
index db6d600a39..52756ad9cd 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hash_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of HASH HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c
index 07babd0a41..44d6840605 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hcd.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   HCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -87,7 +87,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -1185,12 +1186,8 @@ static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
           USBx_HOST->HFIR = (uint32_t)60000U;
         }
       }
-      HAL_HCD_Connect_Callback(hhcd);
       
-      if(hhcd->Init.speed == HCD_SPEED_HIGH)
-      {
-        USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
-      }
+      HAL_HCD_Connect_Callback(hhcd);
     }
     else
     {
@@ -1216,7 +1213,8 @@ static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #endif /* HAL_HCD_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h
index 7a62cbf59a..4ccfdc52f2 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_hcd.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx)  || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_ll_usb.h"
    
@@ -250,7 +251,8 @@ uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
   * @}
   */ 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c
index 1c0383d833..bec5f0d044 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -239,7 +239,7 @@
   */    
 #define I2C_TIMEOUT_FLAG          ((uint32_t)35U)         /*!< Timeout 35 ms             */
 #define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000U)      /*!< Timeout 10 s              */
-#define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)10000U)      /*!< Timeout 10 s              */
+#define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)25U)         /*!< Timeout 25 ms             */
 #define I2C_NO_OPTION_FRAME       ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
 
 /* Private define for @ref PreviousState usage */
@@ -260,30 +260,33 @@
 /** @addtogroup I2C_Private_Functions
   * @{
   */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+/* Private functions to handle DMA transfer */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
 
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
 
+/* Private functions for I2C transfer IRQ handler */
 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
 
 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
@@ -520,6 +523,10 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
         (++) HAL_I2C_Master_Receive_IT()
         (++) HAL_I2C_Slave_Transmit_IT()
         (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Master_Sequential_Transmit_IT()
+        (++) HAL_I2C_Master_Sequential_Receive_IT()
+        (++) HAL_I2C_Slave_Sequential_Transmit_IT()
+        (++) HAL_I2C_Slave_Sequential_Receive_IT()
         (++) HAL_I2C_Mem_Write_IT()
         (++) HAL_I2C_Mem_Read_IT()
 
@@ -539,6 +546,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
         (++) HAL_I2C_SlaveTxCpltCallback()
         (++) HAL_I2C_SlaveRxCpltCallback()
         (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
 
 @endverbatim
   * @{
@@ -548,7 +556,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
   * @brief  Transmits in master mode an amount of data in blocking mode.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
@@ -556,10 +565,15 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -569,14 +583,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
     
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
+	
     hi2c->State = HAL_I2C_STATE_BUSY_TX;
     hi2c->Mode = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     
     /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
+    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -598,7 +612,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
     while(Size > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -624,7 +638,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
       }
       
       /* Wait until BTF flag is set */
-      if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+      if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -660,7 +674,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
   * @brief  Receives in master mode an amount of data in blocking mode.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  Timeout Timeout duration
@@ -668,10 +683,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -688,7 +708,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     
     /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
+    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -751,7 +771,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
         if(Size == 1U)
         {
           /* Wait until RXNE flag is set */
-          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)      
+          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
           {
             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
             {
@@ -771,7 +791,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
         else if(Size == 2U)
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -791,7 +811,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
         else
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -804,7 +824,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
           Size--;
 
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -824,7 +844,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
       else
       {
         /* Wait until RXNE flag is set */
-        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)      
+        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
         {
           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
           {
@@ -874,6 +894,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+  
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
@@ -882,7 +907,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     }
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -902,7 +927,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     hi2c->Instance->CR1 |= I2C_CR1_ACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -914,7 +939,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
       /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -926,7 +951,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     while(Size > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -953,7 +978,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
     }
 
     /* Wait until AF flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -989,6 +1014,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+  
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
@@ -997,7 +1027,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     }
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -1017,7 +1047,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     hi2c->Instance->CR1 |= I2C_CR1_ACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -1028,7 +1058,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     while(Size > 0U)
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)      
+      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
       {
         /* Disable Address Acknowledge */
         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -1055,7 +1085,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     }
 
     /* Wait until STOP flag is set */
-    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
+    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
       /* Disable Address Acknowledge */
       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -1094,24 +1124,38 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
   * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
 
@@ -1123,29 +1167,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress = DevAddress;
 
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
+    /* Generate Start */
+    hi2c->Instance->CR1 |= I2C_CR1_START;
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    if(hi2c->XferSize > 0U)
-    {
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
@@ -1154,23 +1180,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
               process unlock */
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    else
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-      hi2c->State = HAL_I2C_STATE_READY;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
 
     return HAL_OK;
   }
@@ -1184,20 +1193,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
   * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -1208,85 +1231,28 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
     hi2c->State = HAL_I2C_STATE_BUSY_RX;
     hi2c->Mode = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
     hi2c->pBuffPtr = pData;
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(hi2c->XferCount == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 1U)   
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-      
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 2U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-        
-    if(hi2c->XferCount == 0U)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-
+    hi2c->Devaddress = DevAddress;
+    
+    /* Enable Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    
+    /* Generate Start */
+    hi2c->Instance->CR1 |= I2C_CR1_START;
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
-    if(hi2c->XferCount > 0U)
-    {
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
+    
     return HAL_OK;
   }
   else
@@ -1300,7 +1266,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@@ -1308,6 +1275,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
   */
 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
+  uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+  
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -1317,10 +1287,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
     {
       /* Wait until BUSY flag is reset */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+      do
       {
-        return HAL_BUSY;
+        if(count-- == 0U)
+        {
+          hi2c->PreviousState = I2C_STATE_NONE;
+          hi2c->State= HAL_I2C_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          
+          return HAL_TIMEOUT; 
+        }
       }
+      while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
     }
 
     /* Process Locked */
@@ -1337,57 +1318,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = XferOptions;
-    
-    if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) || (hi2c->PreviousState == I2C_STATE_NONE))
-    {
-      /* Send Slave Address */
-      if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
+    hi2c->Devaddress = DevAddress;
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    Prev_State = hi2c->PreviousState;
+    
+    /* Generate Start */    
+    if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
+    {
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate Start */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
-    if(hi2c->XferSize > 0U)
-    {
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
+    
     /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    else
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      
-      hi2c->State = HAL_I2C_STATE_READY;
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
     
     return HAL_OK;
   }
@@ -1402,7 +1361,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
   * @note   This interface allow to manage repeated start condition when a direction change during transfer
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@@ -1410,6 +1370,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
   */
 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
+  uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+    
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -1419,10 +1382,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
     {
       /* Wait until BUSY flag is reset */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+      do
       {
-        return HAL_BUSY;
+        if(count-- == 0U)
+        {
+          hi2c->PreviousState = I2C_STATE_NONE;
+          hi2c->State= HAL_I2C_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_TIMEOUT; 
+        }
       }
+      while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
     }
 
     /* Process Locked */
@@ -1439,108 +1413,41 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = XferOptions;
-
-    if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
-    {
-      /* Send Slave Address */
-      if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-    }
+    hi2c->Devaddress = DevAddress;
     
-    if(hi2c->XferCount == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-    else if(hi2c->XferCount == 1U)   
-    {
-      /* Prepare next transfer or stop current transfer */
-      if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->PreviousState != I2C_STATE_MASTER_BUSY_RX))
-      {
-        if(hi2c->XferOptions != I2C_NEXT_FRAME)
-        {
-          /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-        }
-        else
-        {
-          /* Enable Acknowledge */
-          hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        }
-        
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      }
-      else
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    Prev_State = hi2c->PreviousState;
 
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      }
-    }
-    else if(hi2c->XferCount == 2U)
+    if((Prev_State == I2C_STATE_MASTER_BUSY_TX) || (Prev_State == I2C_STATE_NONE))
     {
-      if(hi2c->XferOptions != I2C_NEXT_FRAME)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-        /* Enable Pos */
-        hi2c->Instance->CR1 |= I2C_CR1_POS;
-      }
-      else
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
       {
         /* Enable Acknowledge */
         hi2c->Instance->CR1 |= I2C_CR1_ACK;
-      }
         
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+        /* Generate Start */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(Prev_State == I2C_STATE_MASTER_BUSY_TX)
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+        
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
-    if(hi2c->XferCount > 0U)
-    {
     /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
 
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
+
     return HAL_OK;
   }
   else
@@ -1559,18 +1466,31 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-
+    
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -1618,6 +1538,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
@@ -1626,10 +1548,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
     }
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -1846,24 +1779,43 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
   * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0x00U;
+
+  __IO uint32_t count = 0U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
 
@@ -1875,45 +1827,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    
+
     if(hi2c->XferSize > 0U)
     {
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
 
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+      /* Set the DMA error callback */      
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferM1CpltCallback = NULL;
+      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
 
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
       /* Send Slave Address */
-      if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -1932,12 +1865,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+      /* Enable ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+    }
+    else
+    {
+      /* Send Slave Address */
+      if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_ERROR;
+        }
+        else
+        {
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_TIMEOUT;
+        }
       }
 
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
       /* Generate Stop */
       hi2c->Instance->CR1 |= I2C_CR1_STOP;
 
@@ -1959,49 +1914,74 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
   * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  pData Pointer to data buffer
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0x00U;
+  
+  __IO uint32_t count = 0U;
+  
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
     
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
+    
     hi2c->State = HAL_I2C_STATE_BUSY_RX;
     hi2c->Mode = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+    
     hi2c->pBuffPtr = pData;
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
+    
     if(hi2c->XferSize > 0U)
-    {    
+    {
       /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-      
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
       /* Set the DMA error callback */
       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-      
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferM1CpltCallback = NULL;
+      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
       /* Enable the DMA Stream */
       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-      
+
       /* Send Slave Address */
-      if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -2016,7 +1996,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
           return HAL_TIMEOUT;
         }
       }
-      
+
       if(Size == 1U)
       {
         /* Disable Acknowledge */
@@ -2027,17 +2007,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
         /* Enable Last DMA bit */
         hi2c->Instance->CR2 |= I2C_CR2_LAST;
       }
-      
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-      
+
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
     }
     else
     {
       /* Send Slave Address */
-      if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -2055,16 +2044,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
+      
       /* Generate Stop */
       hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
+      
       hi2c->State = HAL_I2C_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
     }
     
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
     return HAL_OK;
   }
   else
@@ -2077,40 +2066,44 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
   * @brief  Abort a master I2C process communication with Interrupt.
   * @note   This abort can be called only if state is ready
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
 {
   /* Abort Master transfer during Receive or Transmit process    */
-  /* Or after an error during during Receive or Transmit process */
-  if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
-     ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) && ((hi2c->PreviousState & ((uint32_t)HAL_I2C_MODE_MASTER)) == HAL_I2C_MODE_MASTER)))
+  if(hi2c->Mode == HAL_I2C_MODE_MASTER)
   {
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    
+
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
     /* Disable Acknowledge */
     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
 
     /* Generate Stop */
     hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    
+
     hi2c->XferCount = 0U;
-    
+
     /* Disable EVT, BUF and ERR interrupt */
     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_READY;
 
     /* Process Unlocked */
-    __HAL_UNLOCK(hi2c); 
+    __HAL_UNLOCK(hi2c);
+
+    if(hi2c->State == HAL_I2C_STATE_ABORT)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Call the Abort Complete callback */
+      HAL_I2C_AbortCpltCallback(hi2c);
+    }
 
-    /* Call Complete Callback */
     return HAL_OK;
   }
   else
@@ -2131,6 +2124,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+  
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
@@ -2139,10 +2134,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     }
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2158,16 +2164,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
 
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+    
     /* Set the DMA error callback */
     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
 
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hi2c->hdmatx->XferM1CpltCallback = NULL;
+    hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+    hi2c->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the DMA Stream */
     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
 
+    /* Enable ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+    
     /* Enable DMA Request */
     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
 
@@ -2175,11 +2190,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     hi2c->Instance->CR1 |= I2C_CR1_ACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_TIMEOUT;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        return HAL_TIMEOUT; 
+      }
     }
-
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
+    
     /* If 7bit addressing mode is selected */
     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
     {
@@ -2192,10 +2218,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
       /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+      count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
+      do
       {
-        return HAL_TIMEOUT;
+        if(count-- == 0U)
+        {
+          hi2c->PreviousState = I2C_STATE_NONE;
+          hi2c->State= HAL_I2C_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          
+          return HAL_TIMEOUT; 
+        }
       }
+      while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -2204,6 +2241,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);      
+
     return HAL_OK;
   }
   else
@@ -2222,6 +2265,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     if((pData == NULL) || (Size == 0U))
@@ -2230,10 +2275,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     }
 
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2251,14 +2307,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     
     /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
 
     /* Set the DMA error callback */
     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+    
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hi2c->hdmarx->XferM1CpltCallback = NULL;
+    hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+    hi2c->hdmarx->XferAbortCallback = NULL;
 
     /* Enable the DMA Stream */
     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
 
+    /* Enable ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
     /* Enable DMA Request */
     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
 
@@ -2266,10 +2331,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     hi2c->Instance->CR1 |= I2C_CR1_ACK;
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_TIMEOUT;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -2277,6 +2353,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
     return HAL_OK;
   }
   else
@@ -2298,13 +2380,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -2321,7 +2408,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -2340,7 +2427,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
     while(Size > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+      if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -2365,9 +2452,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
         Size--;
       }
     }
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+    
+    /* Wait until BTF flag is set */
+    if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -2412,13 +2499,18 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -2435,7 +2527,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -2495,7 +2587,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         if(Size== 1U)
         {
           /* Wait until RXNE flag is set */
-          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)      
+          if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
           {
             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
             {
@@ -2515,7 +2607,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         else if(Size == 2U)
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -2535,7 +2627,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         else
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -2548,7 +2640,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
           Size--;
 
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
             return HAL_TIMEOUT;
           }
@@ -2568,7 +2660,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
       else
       {
         /* Wait until RXNE flag is set */
-        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)      
+        if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)      
         {
           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
           {
@@ -2606,6 +2698,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
     return HAL_BUSY;
   }
 }
+
 /**
   * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2619,16 +2712,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
@@ -2644,52 +2750,24 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress = DevAddress;
+    hi2c->Memaddress = MemAddress;
+    hi2c->MemaddSize = MemAddSize;
+    hi2c->EventCount = 0U;
+
+    /* Generate Start */
+    hi2c->Instance->CR1 |= I2C_CR1_START;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    if(hi2c->XferSize > 0U)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    else
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-      
-      hi2c->State = HAL_I2C_STATE_READY;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
     return HAL_OK;
   }
   else
@@ -2711,20 +2789,33 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
 
@@ -2736,72 +2827,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress = DevAddress;
+    hi2c->Memaddress = MemAddress;
+    hi2c->MemaddSize = MemAddSize;
+    hi2c->EventCount = 0U;
 
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
+    /* Enable Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
 
-    if(hi2c->XferCount == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 1U)   
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    /* Generate Start */
+    hi2c->Instance->CR1 |= I2C_CR1_START;
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 2U)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    
-    if(hi2c->XferCount == 0U)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-    
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
-    if(hi2c->XferCount > 0U)
+    if(hi2c->XferSize > 0U)
     {
       /* Note : The I2C interrupts must be enabled after unlocking current process
       to avoid the risk of I2C interrupt handle execution before current
@@ -2817,6 +2857,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     return HAL_BUSY;
   }
 }
+
 /**
   * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2830,20 +2871,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
 
@@ -2859,38 +2918,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
     if(hi2c->XferSize > 0U)
     {    
       /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
-      
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
       /* Set the DMA error callback */
       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-      
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferM1CpltCallback = NULL;
+      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
       /* Enable the DMA Stream */
       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-      
+
       /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-      {
-        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_ERROR;
-        }
-        else
-        {
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-          return HAL_TIMEOUT;
-        }
-      }
-      
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-    }
-    else
-    {
-      /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -2906,10 +2949,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         }
       }
 
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+      /* Enable ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+    }
+    else
+    {
+      /* Send Slave Address and Memory Address */
+      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_ERROR;
+        }
+        else
+        {
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_TIMEOUT;
+        }
       }
 
       /* Generate Stop */
@@ -2918,7 +2980,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
       hi2c->State = HAL_I2C_STATE_READY;
     }
 
-
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
@@ -2943,20 +3004,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  uint32_t tickstart = 0x00U;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+    do
     {
-      return HAL_BUSY;
+      if(count-- == 0U)
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT; 
+      }
     }
+    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
     /* Disable Pos */
     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
 
@@ -2968,20 +3047,26 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     hi2c->XferSize = Size;
     hi2c->XferCount = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    
+
     if(hi2c->XferSize > 0U)
-    {      
+    {
       /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
-      
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
       /* Set the DMA error callback */
       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-      
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferM1CpltCallback = NULL;
+      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
       /* Enable the DMA Stream */
       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-      
+
       /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -2996,7 +3081,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
           return HAL_TIMEOUT;
         }
       }
-      
+
       if(Size == 1U)
       {
         /* Disable Acknowledge */
@@ -3007,18 +3092,26 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
         /* Enable Last DMA bit */
         hi2c->Instance->CR2 |= I2C_CR2_LAST;
       }
-      
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-      
+
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
       
+     /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
     }
     else
     {
       /* Send Slave Address and Memory Address */
-      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+      if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
       {
         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
         {
@@ -3033,7 +3126,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
           return HAL_TIMEOUT;
         }
       }
-      
+
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
@@ -3041,10 +3134,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
       hi2c->Instance->CR1 |= I2C_CR1_STOP;
 
       hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
     }
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
 
     return HAL_OK;
   }
@@ -3068,10 +3161,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 {
   uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
 
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
   if(hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
@@ -3092,7 +3188,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
       hi2c->Instance->CR1 |= I2C_CR1_START;
 
       /* Wait until SB flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -3130,7 +3226,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
         /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -3151,7 +3247,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
         /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -3179,25 +3275,41 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
   */
 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
 {
-  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+  uint32_t sr2itflags   = READ_REG(hi2c->Instance->SR2);
+  uint32_t sr1itflags   = READ_REG(hi2c->Instance->SR1);
+  uint32_t itsources    = READ_REG(hi2c->Instance->CR2);
+
+  uint32_t CurrentMode  = hi2c->Mode;
+
   /* Master or Memory mode selected */
-  if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
-     (hi2c->Mode == HAL_I2C_MODE_MEM))
+  if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
   {
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
+    /* SB Set ----------------------------------------------------------------*/
+    if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_SB(hi2c);
+    }
+    /* ADD10 Set -------------------------------------------------------------*/
+    else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADD10(hi2c);
+    }
+    /* ADDR Set --------------------------------------------------------------*/
+    else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADDR(hi2c);
+    }
+
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    if((sr2itflags & I2C_FLAG_TRA) != RESET)
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
       /* TXE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
       {
         I2C_MasterTransmit_TXE(hi2c);
       }
       /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
       {
         I2C_MasterTransmit_BTF(hi2c);
       }
@@ -3205,17 +3317,13 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
     /* I2C in mode Receiver --------------------------------------------------*/
     else
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
       /* RXNE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
       {
         I2C_MasterReceive_RXNE(hi2c);
       }
       /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
       {
         I2C_MasterReceive_BTF(hi2c);
       }
@@ -3224,34 +3332,26 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
   /* Slave mode selected */
   else
   {
-    tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-    tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
-    tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
-    tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
     /* ADDR set --------------------------------------------------------------*/
-    if((tmp1 == SET) && (tmp2 == SET))
+    if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
     {
       I2C_Slave_ADDR(hi2c);
     }
     /* STOPF set --------------------------------------------------------------*/
-    else if((tmp3 == SET) && (tmp2 == SET))
+    else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
     {
       I2C_Slave_STOPF(hi2c);
     }
     /* I2C in mode Transmitter -----------------------------------------------*/
-    else if(tmp4 == SET)
+    else if((sr2itflags & I2C_FLAG_TRA) != RESET)
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
       /* TXE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
       {
         I2C_SlaveTransmit_TXE(hi2c);
       }
       /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
       {
         I2C_SlaveTransmit_BTF(hi2c);
       }
@@ -3259,17 +3359,13 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
     /* I2C in mode Receiver --------------------------------------------------*/
     else
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
       /* RXNE set and BTF reset ----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
       {
         I2C_SlaveReceive_RXNE(hi2c);
       }
       /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
       {
         I2C_SlaveReceive_BTF(hi2c);
       }
@@ -3286,11 +3382,11 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
 {
   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
   /* I2C Bus error interrupt occurred ----------------------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
 
@@ -3298,10 +3394,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
   }
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
   /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
 
@@ -3309,10 +3403,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
   }
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
   /* I2C Acknowledge failure error interrupt occurred ------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
   {
     tmp1 = hi2c->Mode;
     tmp2 = hi2c->XferCount;
@@ -3333,51 +3425,22 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
 
       /* Clear AF flag */
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
     }
   }
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
   /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
     /* Clear OVR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
   }
 
+  /* Call the Error Callback in case of Error detected -----------------------*/
   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
   {
-    if((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      /* keep HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-    }
-    else
-    {
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-    }
-    
-    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-    
-    HAL_I2C_ErrorCallback(hi2c);
-    
-    /* STOP Flag is not set after a NACK reception */
-    /* So may inform upper layer that listen phase is stopped */
-    /* during NACK error treatment */
-    if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
-    {
-      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      
-      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-      HAL_I2C_ListenCpltCallback(hi2c);
-    }
+    I2C_ITError(hi2c);
   }
 }
 
@@ -3519,6 +3582,22 @@ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
    */
 }
 
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
 /**
   * @}
   */
@@ -3583,18 +3662,110 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
 {
-  if(hi2c->XferCount == 0U)
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentState       = hi2c->State;
+  uint32_t CurrentMode        = hi2c->Mode;
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+  uint32_t tmp;
+
+  if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
   {
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+    /* Call TxCpltCallback() directly if no stop mode is set */
+    if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+    {
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+      
+      tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+      hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+      
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+    }
+    else /* Generate Stop condition then Call TxCpltCallback() */
+    {
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+      
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+      
+      if(hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        HAL_I2C_MemTxCpltCallback(hi2c);
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+      }
+    }
   }
-  else
+  else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+    ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
   {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
+    if(hi2c->XferCount == 0U)
+    {
+      /* Disable BUF interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+    }
+    else
+    {
+      if(hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        if(hi2c->EventCount == 0)
+        {
+          /* If Memory address size is 8Bit */
+          if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+          {
+            /* Send Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+            
+            hi2c->EventCount += 2;
+          }
+          /* If Memory address size is 16Bit */
+          else
+          {
+            /* Send MSB of Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+            
+            hi2c->EventCount++;
+          }
+        }
+        else if(hi2c->EventCount == 1)
+        {
+          /* Send LSB of Memory Address */
+          hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+          
+          hi2c->EventCount++;
+        }
+        else if(hi2c->EventCount == 2)
+        {
+          if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+          {
+            /* Generate Restart */
+            hi2c->Instance->CR1 |= I2C_CR1_START;
+          }
+          else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+          {
+            /* Write data to DR */
+            hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+            hi2c->XferCount--;
+          }
+        }
+      }
+      else
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+        hi2c->XferCount--;
+      }
+    }
   }
-  
   return HAL_OK;
 }
 
@@ -3606,53 +3777,56 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
 {
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
   uint32_t tmp;
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
 
-  if(hi2c->XferCount != 0U)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  else
-  {
-    /* Call TxCpltCallback() directly if no stop mode is set */
-    if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+  if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {    
+    if(hi2c->XferCount != 0U)
     {
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-      
-      tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-      hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterTxCpltCallback(hi2c);
+      /* Write data to DR */
+      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+      hi2c->XferCount--;
     }
-    else /* Generate Stop condition then Call TxCpltCallback() */
+    else
     {
-      /* Disable EVT, BUF and ERR interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-      if(hi2c->Mode == HAL_I2C_MODE_MEM)
+      /* Call TxCpltCallback() directly if no stop mode is set */
+      if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
       {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+        
+        tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+        hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
         hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        HAL_I2C_MemTxCpltCallback(hi2c);
-      }
-      else
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
         hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
+        
         HAL_I2C_MasterTxCpltCallback(hi2c);
       }
+      else /* Generate Stop condition then Call TxCpltCallback() */
+      {
+        /* Disable EVT, BUF and ERR interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+        
+        /* Generate Stop */
+        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+        
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        
+        if(hi2c->Mode == HAL_I2C_MODE_MEM)
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+          
+          HAL_I2C_MemTxCpltCallback(hi2c);
+        }
+        else
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+          
+          HAL_I2C_MasterTxCpltCallback(hi2c);
+        }
+      }
     }
   }
   return HAL_OK;
@@ -3666,71 +3840,70 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
 {
-  uint32_t tmp = 0U;
-
-  tmp = hi2c->XferCount;
-  if(tmp > 3U)
+  if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
   {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  else if((tmp == 2U) || (tmp == 3U))
-  {
-    if(hi2c->XferOptions != I2C_NEXT_FRAME)
+    uint32_t tmp = 0U;
+    
+    tmp = hi2c->XferCount;
+    if(tmp > 3U)
     {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
+      /* Read data from DR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+      hi2c->XferCount--;
+    }
+    else if((tmp == 2U) || (tmp == 3U))
+    {
+      if(hi2c->XferOptions != I2C_NEXT_FRAME)
+      {
+        /* Disable Acknowledge */
+        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+        
+        /* Enable Pos */
+        hi2c->Instance->CR1 |= I2C_CR1_POS;
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+      }
+      
+      /* Disable BUF interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
     }
     else
     {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-    }
+      if(hi2c->XferOptions != I2C_NEXT_FRAME)
+      {
+        /* Disable Acknowledge */
+        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+      }
 
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-  }
-  else
-  {
-    if(hi2c->XferOptions != I2C_NEXT_FRAME)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
-    }
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+      
+      /* Read data from DR */
+      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+      hi2c->XferCount--;
 
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    if(hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
       hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
 
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-      hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      HAL_I2C_MasterRxCpltCallback(hi2c);
+      if(hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        HAL_I2C_MemRxCpltCallback(hi2c);
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+      }
     }
   }
   return HAL_OK;
@@ -3744,23 +3917,16 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
 {
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
   uint32_t tmp;
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
 
   if(hi2c->XferCount == 3U)
   {
-    if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
+    if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
     {
-      if(hi2c->XferOptions != I2C_NEXT_FRAME)
-      {
-        /* Disable Acknowledge */
-        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        hi2c->Instance->CR1 |= I2C_CR1_ACK;
-      }
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
     }
 
     /* Read data from DR */
@@ -3770,9 +3936,9 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
   else if(hi2c->XferCount == 2U)
   {
     /* Prepare next transfer or stop current transfer */
-    if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+    if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
     {
-      if(hi2c->XferOptions != I2C_NEXT_FRAME)
+      if(CurrentXferOptions != I2C_NEXT_FRAME)
       {
         /* Disable Acknowledge */
         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -3804,16 +3970,16 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
     /* Disable EVT and ERR interrupt */
     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
 
+    hi2c->State = HAL_I2C_STATE_READY;
+    
     if(hi2c->Mode == HAL_I2C_MODE_MEM)
     {
-      hi2c->State = HAL_I2C_STATE_READY;
       hi2c->Mode = HAL_I2C_MODE_NONE;
 
       HAL_I2C_MemRxCpltCallback(hi2c);
     }
     else
     {
-      hi2c->State = HAL_I2C_STATE_READY;
       hi2c->Mode = HAL_I2C_MODE_NONE;
 
       HAL_I2C_MasterRxCpltCallback(hi2c);
@@ -3828,6 +3994,186 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
   return HAL_OK;
 }
 
+/**
+  * @brief  Handle SB flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
+{
+  if(hi2c->Mode == HAL_I2C_MODE_MEM)
+  {
+    if(hi2c->EventCount == 0U)
+    {
+      /* Send slave address */
+      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+    }
+    else
+    {
+      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+    }
+  }
+  else
+  {
+    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+    {
+      /* Send slave 7 Bits address */
+      if(hi2c->State == HAL_I2C_STATE_BUSY_TX) 
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+      }
+      else
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+      }
+    }
+    else
+    {
+      if(hi2c->EventCount == 0U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
+      }
+      else if(hi2c->EventCount == 1U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADD10 flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
+{
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADDR flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentMode        = hi2c->Mode;
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+  uint32_t Prev_State         = hi2c->PreviousState;
+  
+  if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      
+      /* Generate Restart */
+      hi2c->Instance->CR1 |= I2C_CR1_START;
+      
+      hi2c->EventCount++;
+    }
+    else
+    {
+      if(hi2c->XferCount == 0U)
+      {
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+        
+        /* Generate Stop */
+        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      }
+      else if(hi2c->XferCount == 1U)   
+      {
+        /* Prepare next transfer or stop current transfer */
+        if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+          && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
+        {
+          if(hi2c->XferOptions != I2C_NEXT_FRAME)
+          {
+            /* Disable Acknowledge */
+            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+          }
+          else
+          {
+            /* Enable Acknowledge */
+            hi2c->Instance->CR1 |= I2C_CR1_ACK;
+          }
+          
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+        }
+        else
+        {
+          /* Disable Acknowledge */
+          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+          
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+          
+          /* Generate Stop */
+          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+        }
+      }
+      else if(hi2c->XferCount == 2U)
+      {
+        if(hi2c->XferOptions != I2C_NEXT_FRAME)
+        {
+          /* Disable Acknowledge */
+          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+          
+          /* Enable Pos */
+          hi2c->Instance->CR1 |= I2C_CR1_POS;
+        }
+        else
+        {
+          /* Enable Acknowledge */
+          hi2c->Instance->CR1 |= I2C_CR1_ACK;
+        }
+        
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+        
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+      
+      /* Reset Event counter  */
+      hi2c->EventCount = 0;
+    }
+  }
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+  }
+
+  return HAL_OK;
+}
+
 /**
   * @brief  Handle TXE flag for Slave
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3836,8 +4182,9 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
 {
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
   uint32_t tmp;
+  uint32_t CurrentState = hi2c->State;
 
   if(hi2c->XferCount != 0U)
   {
@@ -3845,7 +4192,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
     hi2c->XferCount--;
 
-    if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+    if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
     {
       /* Last Byte is received, disable Interrupt */
       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
@@ -3887,8 +4234,9 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
 {
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
   uint32_t tmp;
+  uint32_t CurrentState = hi2c->State;
 
   if(hi2c->XferCount != 0U)
   {
@@ -3896,7 +4244,7 @@ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
     hi2c->XferCount--;
 
-    if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+    if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
     {
       /* Last Byte is received, disable Interrupt */
       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
@@ -3970,6 +4318,9 @@ static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
 {
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentState = hi2c->State;
+  
   /* Disable EVT, BUF and ERR interrupt */
   __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
@@ -3979,7 +4330,8 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
   /* Disable Acknowledge */
   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
 
-  if((hi2c->State & HAL_I2C_STATE_LISTEN)== HAL_I2C_STATE_LISTEN)
+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
+    (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
   {
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->PreviousState = I2C_STATE_NONE;
@@ -3991,8 +4343,7 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
   }
   else
   {
-    if((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || \
-       (hi2c->State == HAL_I2C_STATE_BUSY_RX))
+    if((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
     {
       hi2c->PreviousState = I2C_STATE_NONE;
       hi2c->State = HAL_I2C_STATE_READY;
@@ -4012,11 +4363,13 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
   */
 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
 {
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentState       = hi2c->State;
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
   uint32_t tmp;
 
-  if(((hi2c->XferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
-          (hi2c->State == HAL_I2C_STATE_LISTEN))
+  if(((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+          (CurrentState == HAL_I2C_STATE_LISTEN))
   {
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
@@ -4036,7 +4389,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
     HAL_I2C_ListenCpltCallback(hi2c);
   }
-  else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
   {
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
@@ -4065,30 +4418,122 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
   return HAL_OK;
 }
 
+/**
+  * @brief  I2C interrupts error process
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentState = hi2c->State;
+
+  if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* keep HAL_I2C_STATE_LISTEN */
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+  }
+  else
+  {
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if(hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+    }
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+  }
+
+  /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+  hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+  /* Abort DMA transfer */
+  if((hi2c->Instance->CR1 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+  {
+    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+    if(hi2c->hdmatx != NULL)
+    {
+      /* Set the DMA Abort callback : 
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else if(hi2c->hdmarx != NULL)
+    {
+      /* Set the DMA Abort callback : 
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+  }
+  else if(hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_AbortCpltCallback(hi2c);
+  }
+  else
+  {
+    /* Call user error callback */
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  /* STOP Flag is not set after a NACK reception */
+  /* So may inform upper layer that listen phase is stopped */
+  /* during NACK error treatment */
+  if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
+  {
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    HAL_I2C_ListenCpltCallback(hi2c);
+  }
+}
+
 /**
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
   /* Generate Start condition if first transfer */
-  if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
+  if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
   {
     /* Generate Start */
     hi2c->Instance->CR1 |= I2C_CR1_START;
   }
   else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
   {
-
     /* Generate ReStart */
     hi2c->Instance->CR1 |= I2C_CR1_START;
   }
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -4104,7 +4549,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
 
     /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -4121,7 +4566,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
   }
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4140,14 +4585,19 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
   * @brief  Master sends target device address for read request.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress Target device address
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
   /* Generate Start condition if first transfer */
-  if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)  || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
+  if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
   {
     /* Enable Acknowledge */
     hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -4165,7 +4615,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
   }
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -4181,7 +4631,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
 
     /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -4197,7 +4647,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -4216,7 +4666,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->CR1 |= I2C_CR1_START;
 
     /* Wait until SB flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -4226,7 +4676,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
   }
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4249,15 +4699,16 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
   * @param  MemAddress Internal memory address
   * @param  MemAddSize Size of internal memory address
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   /* Generate Start */
   hi2c->Instance->CR1 |= I2C_CR1_START;
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -4266,7 +4717,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4282,7 +4733,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4309,7 +4760,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXE flag is set */
-    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -4338,9 +4789,10 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
   * @param  MemAddress Internal memory address
   * @param  MemAddSize Size of internal memory address
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   /* Enable Acknowledge */
   hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -4349,7 +4801,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   hi2c->Instance->CR1 |= I2C_CR1_START;
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -4358,7 +4810,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4374,7 +4826,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4401,7 +4853,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXE flag is set */
-    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+    if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
       {
@@ -4420,7 +4872,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   }
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+  if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4438,7 +4890,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   hi2c->Instance->CR1 |= I2C_CR1_START;
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
     return HAL_TIMEOUT;
   }
@@ -4447,7 +4899,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     {
@@ -4463,238 +4915,67 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
 }
 
 /**
-  * @brief  DMA I2C master transmit process complete callback.
+  * @brief  DMA I2C process complete callback.
   * @param  hdma DMA handle
   * @retval None
   */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
 {
   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
   
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentState = hi2c->State;
+  uint32_t CurrentMode  = hi2c->Mode;
+
+  if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) 
   {
-    HAL_I2C_ErrorCallback(hi2c);
+    /* Disable DMA Request */
+    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+    
+    hi2c->XferCount = 0U;
+    
+    /* Enable EVT and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
   }
   else
   {
-    HAL_I2C_MasterTxCpltCallback(hi2c);
-  }
-}
+    /* Disable Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    
+    /* Generate Stop */
+    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    
+    /* Disable Last DMA */
+    hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+    
+    /* Disable DMA Request */
+    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+    
+    hi2c->XferCount = 0U;
 
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until AF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Clear AF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C master receive process complete callback
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-  
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-  /* Disable Last DMA */
-  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MasterRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until STOPF flag is reset */
-  if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    /* Check if Errors has been detected during transfer */
+    if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
     {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      HAL_I2C_ErrorCallback(hi2c);
     }
     else
     {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      if(hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        HAL_I2C_MemRxCpltCallback(hi2c);
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+      }
     }
   }
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C Memory Write process complete callback
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C Memory Read process complete callback
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-  
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-  /* Disable Last DMA */
-  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0U;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-  
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemRxCpltCallback(hi2c);
-  }
 }
 
 /**
@@ -4713,12 +4994,50 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 
   hi2c->State = HAL_I2C_STATE_READY;
   hi2c->Mode = HAL_I2C_MODE_NONE;
-  
+
   hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
 
   HAL_I2C_ErrorCallback(hi2c);
 }
 
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma: DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  hi2c->XferCount = 0U;
+
+  /* Reset XferAbortCallback */
+  hi2c->hdmatx->XferAbortCallback = NULL;
+  hi2c->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if come from abort from user */
+  if(hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_AbortCpltCallback(hi2c);
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+}
+
 /**
   * @brief  This function handles I2C Communication Timeout.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -4726,56 +5045,30 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
   * @param  Flag specifies the I2C flag to check.
   * @param  Status The new Flag status (SET or RESET).
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0U;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
+  while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) 
   {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State= HAL_I2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->PreviousState = I2C_STATE_NONE;
-          hi2c->State= HAL_I2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_TIMEOUT;
-        }
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State= HAL_I2C_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        
+        return HAL_TIMEOUT;
       }
     }
   }
+  
   return HAL_OK;
 }
 
@@ -4785,15 +5078,11 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
   *         the configuration information for I2C module
   * @param  Flag specifies the I2C flag to check.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0U;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
   {
     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
@@ -4817,7 +5106,7 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
         hi2c->PreviousState = I2C_STATE_NONE;
         hi2c->State= HAL_I2C_STATE_READY;
@@ -4837,12 +5126,11 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)  
-{  
-  uint32_t tickstart = HAL_GetTick();
-  
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{    
   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
   {
     /* Check if a NACK is detected */
@@ -4854,7 +5142,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->PreviousState = I2C_STATE_NONE;
@@ -4875,12 +5163,11 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {  
-  uint32_t tickstart = HAL_GetTick();
-  
   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
   {
     /* Check if a NACK is detected */
@@ -4892,7 +5179,7 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->PreviousState = I2C_STATE_NONE;
@@ -4913,13 +5200,11 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {  
-  uint32_t tickstart = 0x00U;
-  tickstart = HAL_GetTick();
-  
   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
   {
     /* Check if a NACK is detected */
@@ -4929,7 +5214,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+    if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       hi2c->PreviousState = I2C_STATE_NONE;
@@ -4949,13 +5234,12 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {  
-  uint32_t tickstart = 0x00U;
-  tickstart = HAL_GetTick();
-  
+
   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
   {
     /* Check if a STOPF is detected */
@@ -4975,7 +5259,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     }
 
     /* Check for the Timeout */
-    if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+    if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
     {
       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
       hi2c->State= HAL_I2C_STATE_READY;
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h
index b6649eb6a9..e48c242e73 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
@@ -91,7 +91,30 @@ typedef struct
 }I2C_InitTypeDef;
 
 /**
-  * @brief  HAL State structures definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : Abort (Abort user request on going)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
+  *          b4     (not used)
+  *             x  : Should be set to 0
+  *          b3
+  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             1  : Listen (IP in Address Listen Mode)
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
   */
 typedef enum
 {
@@ -105,13 +128,28 @@ typedef enum
                                                  process is ongoing                         */
   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
                                                  process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
 
 }HAL_I2C_StateTypeDef;
 
 /**
-  * @brief  HAL State structures definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :
+  *          b7     (not used)
+  *             x  : Should be set to 0
+  *          b6
+  *             0  : None
+  *             1  : Memory (HAL I2C communication is in Memory Mode)
+  *          b5
+  *             0  : None
+  *             1  : Slave (HAL I2C communication is in Slave Mode)
+  *          b4
+  *             0  : None
+  *             1  : Master (HAL I2C communication is in Master Mode)
+  *          b3-b2-b1-b0  (not used)
+  *             xxxx : Should be set to 0000
   */
 typedef enum
 {
@@ -127,33 +165,41 @@ typedef enum
   */
 typedef struct
 {
-  I2C_TypeDef                *Instance;     /*!< I2C registers base address                */
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
+                                             
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
+                                             
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
+                                             
+  uint16_t                   XferSize;       /*!< I2C transfer size                        */
+                                             
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
+                                             
+  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
+                                             
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
+                                                  context for internal usage               */
+                                             
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
+                                             
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
+                                             
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
+                                             
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
+                                             
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
+                                             
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
 
-  I2C_InitTypeDef            Init;          /*!< I2C communication parameters              */
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
 
-  uint8_t                    *pBuffPtr;     /*!< Pointer to I2C transfer buffer            */
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
 
-  uint16_t                   XferSize;      /*!< I2C transfer size                         */
-
-  __IO uint16_t              XferCount;     /*!< I2C transfer counter                      */
-
-  __IO uint32_t              XferOptions;   /*!< I2C transfer options                      */
-
-  __IO uint32_t              PreviousState; /*!< I2C communication Previous state and mode
-                                                 context for internal usage                */
-
-  DMA_HandleTypeDef          *hdmatx;       /*!< I2C Tx DMA handle parameters              */
-
-  DMA_HandleTypeDef          *hdmarx;       /*!< I2C Rx DMA handle parameters              */
-
-  HAL_LockTypeDef            Lock;          /*!< I2C locking object                        */
-
-  __IO HAL_I2C_StateTypeDef  State;         /*!< I2C communication state                   */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;          /*!< I2C communication mode                    */
-
-  __IO uint32_t              ErrorCode;     /*!< I2C Error code                            */
+  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
 
+  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
+	
 }I2C_HandleTypeDef;
 
 /**
@@ -494,6 +540,7 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c
index ff8949a16b..47c4674015 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   I2C Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2C extension peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h
index ddb0238706..140375c578 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of I2C HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c
index 7e6fe80f6f..a6f7ac6919 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h
index 3f148d2743..ac8e898476 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c
index 8858c33431..c34dd81582 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2s_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2S extension peripheral:
@@ -173,7 +173,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /**
   * @brief Initializes the I2S according to the specified parameters 
   *         in the I2S_InitTypeDef and create the associated handle.
@@ -1188,7 +1189,8 @@ HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
   }
 }
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
-          STM32F411xx || STM32F469xx || STM32F479xx */
+          STM32F411xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx || STM32F412Cx */
 /**
   * @brief DMA I2S transmit process complete callback 
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -1208,8 +1210,10 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
-   /* FullDuplexMode feature enabled */   
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
+    
+    /* FullDuplexMode feature enabled */   
     else
     {
       if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
@@ -1224,8 +1228,7 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
       }
     }
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
-          STM32F469xx || STM32F479xx */
-
+          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
     hi2s->TxXferCount = 0U;
     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
     {
@@ -1261,7 +1264,8 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
    /* FullDuplexMode feature enabled */   
     else
     {
@@ -1277,8 +1281,7 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
       }
     }
 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
-          STM32F469xx || STM32F479xx */
-    
+          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
     hi2s->RxXferCount = 0U;
     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
     {
@@ -1311,7 +1314,8 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
   uint32_t i2ssourceclock = 0U;
 
   /* Configure 12S Clock based on I2S source clock selection */ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
   switch(hi2s->Init.ClockSource)
   {
     case I2S_CLOCK_EXTERNAL :
@@ -1320,7 +1324,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
       i2ssourceclock = EXTERNAL_CLOCK_VALUE;
       break;
     }
-#if defined(STM32F446xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
     case I2S_CLOCK_PLL :
     { 
       /* Configure the PLLI2S division factor */
@@ -1342,7 +1346,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
       i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
       break;
     }
-#endif /* STM32F446xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
     case I2S_CLOCK_PLLR :
     { 
       /* Configure the PLLI2S division factor */
@@ -1385,7 +1389,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
       break;
     }
   }
-#endif /* STM32F410xx || STM32F446xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
@@ -1395,7 +1399,6 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
   in the project configuration or in the stm32f4xx_conf.h file */
   if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
   {
-    __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
     /* Set the I2S clock to the external clock  value */
     i2ssourceclock = EXTERNAL_CLOCK_VALUE;
   }
@@ -1427,7 +1430,6 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
   in the project configuration or in the stm32f4xx_conf.h file */
   if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
   {
-    __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
     /* Set the I2S clock to the external clock  value */
     i2ssourceclock = EXTERNAL_CLOCK_VALUE;
   }
@@ -1453,7 +1455,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
   }
 #endif /* STM32F411xE */
 
-  /* the return result is the value of SAI clock */
+  /* the return result is the value of I2S clock */
   return i2ssourceclock; 
 }
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h
index 9b38c2849f..b9dac3ee58 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_i2s_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
@@ -80,12 +80,12 @@
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
           STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */    
    
-#if defined(STM32F446xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define I2S_CLOCK_PLL                     ((uint32_t)0x00000000U)
 #define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U) 
 #define I2S_CLOCK_PLLR                    ((uint32_t)0x00000002U)
 #define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000003U)
-#endif /* STM32F446xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 #define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000000U)      
@@ -155,12 +155,13 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
           STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
 
-#if defined(STM32F446xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
                                    ((CLOCK) == I2S_CLOCK_PLL)      ||\
                                    ((CLOCK) == I2S_CLOCK_PLLSRC)   ||\
                                    ((CLOCK) == I2S_CLOCK_PLLR))
-#endif /* STM32F446xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
@@ -171,10 +172,12 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Cx) || defined(STM32F410Rx) || \
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \
+    defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || 
+          STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */      
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c
index d087cf8d1a..a5decf54a1 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -161,7 +161,10 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
 /**
   * @}
   */
@@ -239,10 +242,10 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
   IRDA_SetConfig(hirda);
   
   /* In IrDA mode, the following bits must be kept cleared: 
-     - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-     - SCEN and HDSEL bits in the USART_CR3 register.*/
-  hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
-  hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
   
   /* Enable the IRDA peripheral */
   __HAL_IRDA_ENABLE(hirda);
@@ -254,7 +257,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
   
   /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-  hirda->Instance->CR3 |= USART_CR3_IREN;
+  SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
   
   /* Initialize the IRDA state*/
   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -290,13 +293,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
   HAL_IRDA_MspDeInit(hirda);
   
   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
+  
   hirda->gState = HAL_IRDA_STATE_RESET; 
   hirda->RxState = HAL_IRDA_STATE_RESET;
-
+  
   /* Release Lock */
   __HAL_UNLOCK(hirda);
-
+  
   return HAL_OK;
 }
 
@@ -306,13 +309,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_MspInit could be implemented in the user file
-   */ 
+  the HAL_IRDA_MspInit could be implemented in the user file
+  */ 
 }
 
 /**
@@ -321,13 +324,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_MspDeInit could be implemented in the user file
-   */ 
+  the HAL_IRDA_MspDeInit could be implemented in the user file
+  */ 
 }
 
 /**
@@ -396,6 +399,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0;
   
   /* Check that a Tx process is not already ongoing */
   if(hirda->gState == HAL_IRDA_STATE_READY) 
@@ -410,7 +414,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
     
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-       
+    
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+    
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
     while(hirda->TxXferCount > 0U)
@@ -418,7 +425,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
       hirda->TxXferCount--;
       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -435,7 +442,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
       } 
       else
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -443,14 +450,14 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
       }
     }
     
-    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     { 
       return HAL_TIMEOUT;
     }
     
-	/* At end of Tx process, restore hirda->gState to Ready */
+    /* At end of Tx process, restore hirda->gState to Ready */
     hirda->gState = HAL_IRDA_STATE_READY;
-        
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
     
@@ -474,6 +481,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 { 
   uint16_t* tmp;
+  uint32_t tickstart = 0;
   
   /* Check that a Rx process is not already ongoing */
   if(hirda->RxState == HAL_IRDA_STATE_READY) 
@@ -489,6 +497,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
     
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+    
     hirda->RxXferSize = Size;
     hirda->RxXferCount = Size;
     /* Check the remain data to be received */
@@ -497,7 +508,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
       hirda->RxXferCount--;
       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -505,7 +516,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
         if(hirda->Init.Parity == IRDA_PARITY_NONE)
         {
           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
-           pData +=2U;
+          pData +=2U;
         }
         else
         {
@@ -515,7 +526,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
       } 
       else
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -529,10 +540,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
         }
       }
     }
-	
-	/* At end of Rx process, restore hirda->RxState to Ready */
+    
+    /* At end of Rx process, restore hirda->RxState to Ready */
     hirda->RxState = HAL_IRDA_STATE_READY;
-        
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
     
@@ -563,22 +574,19 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
     }
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pTxBuffPtr = pData;
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-        
-   /* Process Unlocked */
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hirda);
 
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
     /* Enable the IRDA Transmit Data Register Empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
-    
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
     return HAL_OK;
   }
   else
@@ -613,18 +621,18 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
     hirda->RxXferCount = Size;
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-        
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-
+    
     /* Enable the IRDA Data Register not empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); 
-
+    SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
+    
     /* Enable the IRDA Parity Error Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    
     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
     
     return HAL_OK;
   }
@@ -645,7 +653,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-	
+  
   /* Check that a Tx process is not already ongoing */
   if(hirda->gState == HAL_IRDA_STATE_READY) 
   {
@@ -656,36 +664,39 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
     
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pTxBuffPtr = pData;
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-        
+
     /* Set the IRDA DMA transfer complete callback */
     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-    
+
     /* Set the IRDA DMA half transfer complete callback */
     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-    
+
     /* Set the DMA error callback */
     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-    
+
+    /* Set the DMA abort callback */
+    hirda->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the IRDA transmit DMA Stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
-    
+
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
     
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    hirda->Instance->CR3 |= USART_CR3_DMAT;
-    
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -714,35 +725,44 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pRxBuffPtr = pData;
     hirda->RxXferSize = Size;   
     hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-        
+
     /* Set the IRDA DMA transfer complete callback */
     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-    
+
     /* Set the IRDA DMA half transfer complete callback */
     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-    
+
     /* Set the DMA error callback */
     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-    
+
+    /* Set the DMA abort callback */
+    hirda->hdmarx->XferAbortCallback = NULL;
+
     /* Enable the DMA Stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    hirda->Instance->CR3 |= USART_CR3_DMAR;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
+    /* Enable the IRDA Parity Error Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+    in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
     return HAL_OK;
   }
   else
@@ -759,20 +779,29 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
   */
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
 {
+  uint32_t dmarequest = 0x00U;
+
   /* Process Locked */
   __HAL_LOCK(hirda);
   
-  if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
   {
-    /* Disable the UART DMA Tx request */
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+    /* Disable the IRDA DMA Tx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
   }
-  if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
   {
-    /* Disable the UART DMA Rx request */
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
     
+    /* Disable the IRDA DMA Rx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+  
   /* Process Unlocked */
   __HAL_UNLOCK(hirda);
   
@@ -782,7 +811,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
 /**
   * @brief Resumes the DMA Transfer.
   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
+  *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
@@ -792,15 +821,20 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
   
   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
   {
-    /* Enable the UART DMA Tx request */
-    hirda->Instance->CR3 |= USART_CR3_DMAT;
+    /* Enable the IRDA DMA Tx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
   }
   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
   {
     /* Clear the Overrun flag before resuming the Rx transfer */
     __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    /* Enable the UART DMA Rx request */
-    hirda->Instance->CR3 |= USART_CR3_DMAR;
+    
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+    
+    /* Enable the IRDA DMA Rx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
   }
   
   /* Process Unlocked */
@@ -812,35 +846,45 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
 /**
   * @brief Stops the DMA Transfer.
   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
+  *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-
-  /* Disable the UART Tx/Rx DMA requests */
-  hirda->Instance->CR3 &= ~USART_CR3_DMAT;
-  hirda->Instance->CR3 &= ~USART_CR3_DMAR;
+  to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
+  when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+  and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+  */
   
-  /* Abort the UART DMA tx Stream */
-  if(hirda->hdmatx != NULL)
+  /* Stop IRDA DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
   {
-    HAL_DMA_Abort(hirda->hdmatx);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+    
+    /* Abort the IRDA DMA Tx channel */
+    if(hirda->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+    IRDA_EndTxTransfer(hirda);
   }
-  /* Abort the UART DMA rx Stream */
-  if(hirda->hdmarx != NULL)
-  {
-    HAL_DMA_Abort(hirda->hdmarx);
-  }
-  
-  hirda->gState = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
 
+  /* Stop IRDA DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+    
+    /* Abort the IRDA DMA Rx channel */
+    if(hirda->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+    IRDA_EndRxTransfer(hirda);
+  }
   return HAL_OK;
 }
 
@@ -852,76 +896,167 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
   */
 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
 {
-  uint32_t  tmp1 = 0U, tmp2 = 0U;
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
-  /* IRDA parity error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_PEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_PE; 
-  }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA frame error interrupt occurred --------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_FEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
-  }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA noise error interrupt occurred --------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_NEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_NE; 
-  }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA Over-Run interrupt occurred -----------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; 
-  }
+   uint32_t isrflags   = READ_REG(hirda->Instance->SR);
+   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
+   uint32_t cr3its     = READ_REG(hirda->Instance->CR3);
+   uint32_t errorflags = 0x00U;
+   uint32_t dmarequest = 0x00U;
 
-  /* Call the Error call Back in case of Errors */
-  if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if(errorflags == RESET)
   {
-    /* Set the IRDA state ready to be able to start again the process */
-    hirda->gState = HAL_IRDA_STATE_READY;
-	hirda->RxState = HAL_IRDA_STATE_READY;
-    HAL_IRDA_ErrorCallback(hirda);
-  }
+    /* IRDA in mode Receiver -----------------------------------------------*/
+    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      IRDA_Receive_IT(hirda);
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+  {
+    /* IRDA parity error interrupt occurred -------------------------------*/
+    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+    }
+
+    /* IRDA noise error interrupt occurred --------------------------------*/
+    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+    }
+
+    /* IRDA frame error interrupt occurred --------------------------------*/
+    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+    }
+
+    /* IRDA Over-Run interrupt occurred -----------------------------------*/
+    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    { 
+      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+    }
+    /* Call IRDA Error Call back function if need be -----------------------*/ 
+    if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+    {
+      /* IRDA in mode Receiver ---------------------------------------------*/
+      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        IRDA_Receive_IT(hirda);
+      }
+
+      dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the IRDA state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        IRDA_EndRxTransfer(hirda);
+
+        /* Disable the IRDA DMA Rx request if enabled */
+        if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the IRDA DMA Rx channel */
+          if(hirda->hdmarx != NULL)
+          {
+            /* Set the IRDA DMA Abort callback : 
+            will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+            if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_IRDA_ErrorCallback(hirda);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_IRDA_ErrorCallback(hirda);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_IRDA_ErrorCallback(hirda);
+        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
 
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
-  /* IRDA in mode Receiver ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    IRDA_Receive_IT(hirda);
-  }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
   /* IRDA in mode Transmitter ------------------------------------------------*/
-  if((tmp1 != RESET) &&(tmp2 != RESET))
+  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     IRDA_Transmit_IT(hirda);
+    return;
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
-  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+
+  /* IRDA in mode Transmitter end --------------------------------------------*/
+  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     IRDA_EndTransmit_IT(hirda);
-  }   
+    return;
+  }
+}
+
+/**
+  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+  * @param  hirda: IRDA handle.
+  * @retval None
+  */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
+  * @param  hirda: IRDA handle.
+  * @retval None
+  */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+/**
+  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hirda->RxXferCount = 0x00U;
+  hirda->TxXferCount = 0x00U;
+
+  HAL_IRDA_ErrorCallback(hirda);
 }
 
 /**
@@ -930,13 +1065,13 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_TxCpltCallback could be implemented in the user file
-   */ 
+  the HAL_IRDA_TxCpltCallback could be implemented in the user file
+  */ 
 }
 
 /**
@@ -945,13 +1080,13 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
-   */
+  the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
+  */
 }
 
 /**
@@ -965,8 +1100,8 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_RxCpltCallback could be implemented in the user file
-   */
+  the HAL_IRDA_RxCpltCallback could be implemented in the user file
+  */
 }
 
 /**
@@ -980,8 +1115,8 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
-   */
+  the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
+  */
 }
 
 /**
@@ -990,13 +1125,13 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hirda);
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_ErrorCallback could be implemented in the user file
-   */ 
+  the HAL_IRDA_ErrorCallback could be implemented in the user file
+  */ 
 }
 
 /**
@@ -1062,13 +1197,13 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
     hirda->TxXferCount = 0U;
-
+    
     /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the IRDA CR3 register */
-    hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
-
+    in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+    
     /* Enable the IRDA Transmit Complete Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
   }
   /* DMA Circular mode */
   else
@@ -1086,7 +1221,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
 {
   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+  
   HAL_IRDA_TxHalfCpltCallback(hirda); 
 }
 
@@ -1102,15 +1237,19 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
     hirda->RxXferCount = 0U;
-
+    
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+    
     /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the IRDA CR3 register */
-    hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
-
-	/* At end of Rx process, restore hirda->RxState to Ready */
+    in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+    
+    /* At end of Rx process, restore hirda->RxState to Ready */
     hirda->RxState = HAL_IRDA_STATE_READY;
   }
-
+  
   HAL_IRDA_RxCpltCallback(hirda);
 }
 
@@ -1123,7 +1262,6 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
 {
   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
   HAL_IRDA_RxHalfCpltCallback(hirda); 
 }
 
@@ -1134,83 +1272,61 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
 {
+  uint32_t dmarequest = 0x00U;
   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
   
-  hirda->RxXferCount = 0U;
-  hirda->TxXferCount = 0U;
+  /* Stop IRDA DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+  {
+    hirda->TxXferCount = 0U;
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+  {
+    hirda->RxXferCount = 0U;
+    IRDA_EndRxTransfer(hirda);
+  }
+  
   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; 
-  hirda->gState= HAL_IRDA_STATE_READY;
-  hirda->RxState= HAL_IRDA_STATE_READY;
   
   HAL_IRDA_ErrorCallback(hirda);
 }
 
 /**
   * @brief  This function handles IRDA Communication Timeout.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
-  * @param  Flag: specifies the IRDA flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  Flag specifies the IRDA flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
   /* Wait until flag is set */
-  if(Status == RESET)
-  {    
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-        
-          hirda->gState= HAL_IRDA_STATE_READY;
-		  hirda->RxState= HAL_IRDA_STATE_READY;
-        
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
-        
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
+  while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-          hirda->gState= HAL_IRDA_STATE_READY;
-		  hirda->RxState= HAL_IRDA_STATE_READY;
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
         
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
+        hirda->gState  = HAL_IRDA_STATE_READY;
+        hirda->RxState = HAL_IRDA_STATE_READY;
         
-          return HAL_TIMEOUT;
-        }
+        /* Process Unlocked */
+        __HAL_UNLOCK(hirda);
+        
+        return HAL_TIMEOUT;
       }
     }
   }
@@ -1251,12 +1367,12 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
     if(--hirda->TxXferCount == 0U)
     {
       /* Disable the IRDA Transmit Data Register Empty Interrupt */
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
       
       /* Enable the IRDA Transmit Complete Interrupt */
-      __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
     }
-
+    
     return HAL_OK;
   }
   else
@@ -1274,14 +1390,14 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
 {
   /* Disable the IRDA Transmit Complete Interrupt */    
-  __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
   
   /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+  
   /* Tx process is ended, restore hirda->gState to Ready */
   hirda->gState = HAL_IRDA_STATE_READY;
-    
+  
   HAL_IRDA_TxCpltCallback(hirda);
   
   return HAL_OK;
@@ -1296,21 +1412,23 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
 {
   uint16_t* tmp;
+  uint16_t  uhdata;
   
   /* Check that a Rx process is ongoing */
   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) 
   {
+    uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
     if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
     {
       tmp = (uint16_t*) hirda->pRxBuffPtr;
       if(hirda->Init.Parity == IRDA_PARITY_NONE)
       {
-        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
+        *tmp = (uint16_t)(uhdata & (uint16_t)0x01FFU);
         hirda->pRxBuffPtr += 2U;
       }
       else
       {
-        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FFU);
+        *tmp = (uint16_t)(uhdata & (uint16_t)0x00FFU);
         hirda->pRxBuffPtr += 1U;
       }
     } 
@@ -1318,26 +1436,26 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
     {
       if(hirda->Init.Parity == IRDA_PARITY_NONE)
       {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FFU);
+        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FFU);
       }
       else
       {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007FU);
+        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007FU);
       }
     }
     
     if(--hirda->RxXferCount == 0U)
     {
-
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+      /* Disable the IRDA Data Register not empty Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
       
       /* Disable the IRDA Parity Error Interrupt */
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-        
-      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
       
-	  /* Rx process is completed, restore hirda->RxState to Ready */
+      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+      
+      /* Rx process is completed, restore hirda->RxState to Ready */
       hirda->RxState = HAL_IRDA_STATE_READY;
       
       HAL_IRDA_RxCpltCallback(hirda);
@@ -1360,8 +1478,6 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
   */
 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
 {
-  uint32_t tmpreg = 0x00U;
-  
   /* Check the parameters */
   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));  
@@ -1371,38 +1487,34 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
   
   /*-------------------------- IRDA CR2 Configuration ------------------------*/
   /* Clear STOP[13:12] bits */
-  hirda->Instance->CR2 &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+  CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
   
   /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = hirda->Instance->CR1;
-  
   /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-    USART_CR1_RE));
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
   
   /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to hirda->Init.WordLength value 
-     Set PCE and PS bits according to hirda->Init.Parity value
-     Set TE and RE bits according to hirda->Init.Mode value */
-  tmpreg |= (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode;
-  
+  Set the M bits according to hirda->Init.WordLength value 
+  Set PCE and PS bits according to hirda->Init.Parity value
+  Set TE and RE bits according to hirda->Init.Mode value */
   /* Write to USART CR1 */
-  hirda->Instance->CR1 = (uint32_t)tmpreg;
+  SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
   
   /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Clear CTSE and RTSE bits */
-  hirda->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
   
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((hirda->Instance == USART1) || (hirda->Instance == USART6))
   {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+    SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
   }
   else
   {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+    SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
   }
 }
+
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h
index 84210b9c2e..f0d71e6af6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
@@ -496,6 +496,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+
 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c
index 7cbcbd0a9d..2781fe5389 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c
@@ -2,81 +2,73 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   IWDG HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Independent Watchdog (IWDG) peripheral:
-  *           + Initialization and Configuration functions
+  *           + Initialization and Start functions
   *           + IO operation functions
-  *           + Peripheral State functions
-  *         
-  @verbatim 
+  *
+  @verbatim
   ==============================================================================
-                    ##### IWDG Specific features #####
+                    ##### IWDG Generic features #####
   ==============================================================================
-    [..] 
+  [..]
     (+) The IWDG can be started by either software or hardware (configurable
-         through option byte).
-    
-    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
-         thus stays active even if the main clock fails.
-         Once the IWDG is started, the LSI is forced ON and cannot be disabled
-         (LSI cannot be disabled too), and the counter starts counting down from 
-         the reset value of 0xFFF. When it reaches the end of count value (0x000)
-         a system reset is generated.
+        through option byte).
+
+    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+        if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both can not be 
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is 
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+        prevented.
 
-    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
-         watchdog generates an MCU reset when the counter reaches 0.          
- 
     (+) The IWDG is implemented in the VDD voltage domain that is still functional
-         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
-         reset occurs.
+        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
 
-    (+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
          The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
          devices provide the capability to measure the LSI frequency (LSI clock
          connected internally to TIM5 CH4 input capture). The measured value
          can be used to have an IWDG timeout with an acceptable accuracy.
 
-
                      ##### How to use this driver #####
   ==============================================================================
-    [..]
-    If Window option is disabled
-      (+) Use IWDG using HAL_IWDG_Init() function to :
-         (++) Enable write access to IWDG_PR, IWDG_RLR.
-         (++) Configure the IWDG prescaler, counter reload value.
-              This reload value will be loaded in the IWDG counter each time the counter
-              is reloaded, then the IWDG will start counting down from this value.
-    [..]
-      (+) Use IWDG using HAL_IWDG_Start() function to:
-          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
-          (++) Start the IWDG, when the IWDG is used in software mode (no need 
-               to enable the LSI, it will be enabled by hardware).
-      (+) Then the application program must refresh the IWDG counter at regular
-          intervals during normal operation to prevent an MCU reset, using
-          HAL_IWDG_Refresh() function.
-    [..] 
-    if Window option is enabled:
-      
-      (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
-      (+) Use IWDG using HAL_IWDG_Init() function to :
-         (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-         (++) Configure the IWDG prescaler, reload value and window value.
-      (+) Then the application program must refresh the IWDG counter at regular
-          intervals during normal operation to prevent an MCU reset, using
-          HAL_IWDG_Refresh() function.  
-     
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts downcounting.
+      (+) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
+      (+) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (+) wait for status flags to be reset"
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
      *** IWDG HAL driver macros list ***
      ====================================
      [..]
-       Below the list of most used macros in IWDG HAL driver.
-       
+       Below the list of most used macros in IWDG HAL driver:
       (+) __HAL_IWDG_START: Enable the IWDG peripheral
-      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register    
-      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
 
   @endverbatim
   ******************************************************************************
@@ -90,7 +82,7 @@
   *      this list of conditions and the following disclaimer.
   *   2. Redistributions in binary form must reproduce the above copyright notice,
   *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
+  *      and/or other materials provided with the distribution
   *   3. Neither the name of STMicroelectronics nor the names of its contributors
   *      may be used to endorse or promote products derived from this software
   *      without specific prior written permission.
@@ -107,7 +99,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -116,57 +108,63 @@
   * @{
   */
 
-/** @defgroup IWDG IWDG
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
   * @brief IWDG HAL module driver.
   * @{
   */
 
-#ifdef HAL_IWDG_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
- /** @addtogroup IWDG_Private_Constants
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-#define IWDG_TIMEOUT_FLAG          ((uint32_t)1000U)     /* 1 s */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
+   higher prescaler (256), and according to HSI variation, we need to wait at
+   least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT            48U
 /**
   * @}
   */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+
+/** @addtogroup IWDG_Exported_Functions
   * @{
   */
 
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
+/** @addtogroup IWDG_Exported_Functions_Group1
+  *  @brief    Initialization and Start functions.
+  *
+@verbatim
  ===============================================================================
-          ##### Initialization and de-initialization functions #####
+          ##### Initialization and Start functions #####
  ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the IWDG according to the specified parameters 
-          in the IWDG_InitTypeDef and create the associated handle
-      (+) Initialize the IWDG MSP
-      (+) DeInitialize IWDG MSP 
- 
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the IWDG according to the specified
-  *         parameters in the IWDG_InitTypeDef and creates the associated handle.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  * @brief  Initialize the IWDG according to the specified parameters in the
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
   *                the configuration information for the specified IWDG module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
 {
+  uint32_t tickstart;
+
   /* Check the IWDG handle allocation */
   if(hiwdg == NULL)
   {
@@ -176,61 +174,49 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
   /* Check the parameters */
   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
-  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); 
-  
-  if(hiwdg->State == HAL_IWDG_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hiwdg->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_IWDG_MspInit(hiwdg);
-  }
-  
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;  
-  
-  /* Enable write access to IWDG_PR and IWDG_RLR registers */  
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+
+  /* Enable IWDG. LSI is turned on automaticaly */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-  
-  /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
-  MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
-  MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
- 
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_READY;
-  
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while(hiwdg->Instance->SR != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
   /* Return function status */
   return HAL_OK;
 }
 
-/**
-  * @brief  Initializes the IWDG MSP.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval None
-  */
-__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hiwdg);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IWDG_MspInit could be implemented in the user file
-   */
-}
-
 /**
   * @}
   */
 
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions  
- *  @brief   IO operation functions  
- *
-@verbatim   
+/** @addtogroup IWDG_Exported_Functions_Group2
+  *  @brief   IO operation functions
+  *
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start the IWDG.
+ ===============================================================================
+ [..]  This section provides functions allowing to:
       (+) Refresh the IWDG.
 
 @endverbatim
@@ -238,111 +224,20 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
   */
 
 /**
-  * @brief  Starts the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hiwdg); 
-  
-    /* Change IWDG peripheral state */  
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
-
-  /* Start the IWDG peripheral */
-  __HAL_IWDG_START(hiwdg);
-  
-    /* Reload IWDG counter with value defined in the RLR register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-  
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Refreshes the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
   *                the configuration information for the specified IWDG module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
 {
-  uint32_t tickstart = 0U;
-
-  /* Process Locked */
-  __HAL_LOCK(hiwdg);
-
-    /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
-
-  tickstart = HAL_GetTick();
-
-  /* Wait until RVU flag is RESET */
-  while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG)
-    {
-      /* Set IWDG state */
-      hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
-
-       /* Process unlocked */
-      __HAL_UNLOCK(hiwdg);
-
-      return HAL_TIMEOUT;
-    }
-  }
-  
   /* Reload IWDG counter with value defined in the reload register */
   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-    
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the IWDG state.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL state
-  */
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
-{
-  return hiwdg->State;
-}
-
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h
index 095fab6052..94950820ef 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_IWDG_H
@@ -52,49 +52,35 @@
 
 /** @addtogroup IWDG
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup IWDG_Exported_Types IWDG Exported Types
   * @{
   */
-   
-/** 
-  * @brief  IWDG HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_IWDG_STATE_RESET     = 0x00U,  /*!< IWDG not yet initialized or disabled */
-  HAL_IWDG_STATE_READY     = 0x01U,  /*!< IWDG initialized and ready for use   */
-  HAL_IWDG_STATE_BUSY      = 0x02U,  /*!< IWDG internal process is ongoing     */
-  HAL_IWDG_STATE_TIMEOUT   = 0x03U,  /*!< IWDG timeout state                   */
-  HAL_IWDG_STATE_ERROR     = 0x04U   /*!< IWDG error state                     */
-}HAL_IWDG_StateTypeDef;
 
 /** 
-  * @brief  IWDG Init structure definition  
-  */ 
+  * @brief  IWDG Init structure definition
+  */
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
                             This parameter can be a value of @ref IWDG_Prescaler */
-  
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
-}IWDG_InitTypeDef;
 
-/** 
-  * @brief  IWDG Handle Structure definition  
-  */ 
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+  * @brief  IWDG Handle Structure definition
+  */
 typedef struct
 {
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
-  
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< IWDG Locking object      */
-  
-  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
+
 }IWDG_HandleTypeDef;
 
 /**
@@ -106,42 +92,23 @@ typedef struct
   * @{
   */
 
-/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
-  * @brief IWDG registers bit mask
-  * @{
-  */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define IWDG_KEY_RELOAD                            ((uint32_t)0xAAAAU)  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                            ((uint32_t)0xCCCCU)  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE               ((uint32_t)0x5555U)  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE              ((uint32_t)0x0000U)  /*!< IWDG KR Write Access Disable */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag_definition IWDG Flag definition
-  * @{
-  */ 
-#define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
-/**
-  * @}
-  */
-
 /** @defgroup IWDG_Prescaler IWDG Prescaler
   * @{
-  */ 
-#define IWDG_PRESCALER_4     ((uint8_t)0x00U)  /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
+  */
+#define IWDG_PRESCALER_4                0x00000000U                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
 /**
   * @}
-  */ 
+  */
+
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -152,133 +119,121 @@ typedef struct
   * @{
   */
 
-/** @brief Reset IWDG handle state
-  * @param  __HANDLE__: IWDG handle.
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
 
 /**
-  * @brief  Enables the IWDG peripheral.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR & IWDG_RLR registers disabled).
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
-  * @brief  Gets the selected IWDG's flag status.
-  * @param  __HANDLE__: IWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
-  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup IWDG_Exported_Functions
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
   * @{
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group1
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
   * @{
   */
-/* Initialization/de-initialization functions  ********************************/
+/* Initialization/Start functions  ********************************************/
 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group2
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
   * @{
   */
 /* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group3
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
   * @{
   */
-/* Peripheral State functions  ************************************************/
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAU  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCU  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555U  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000U  /*!< IWDG KR Write Access Disable */
 
 /**
   * @}
   */
 
-/**
-  * @}
-  */ 
-
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
 /** @defgroup IWDG_Private_Macros IWDG Private Macros
   * @{
   */
 
 /**
-  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
 
 /**
-  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
 
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
 
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
 
 /**
   * @}
   */
 
-/* Private define ------------------------------------------------------------*/
- /** @defgroup IWDG_Private_Constants IWDG Private Constants
-  * @{
-  */
-
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
+
 
-/**
-  * @}
-  */ 
-  
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c
index 001aa7f56d..8fcbadc7ce 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_lptim.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   LPTIM HAL module driver. 
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Low Power Timer (LPTIM) peripheral:
@@ -33,7 +33,7 @@
          (##) The instance: LPTIM1.
          (##) Clock: the counter clock.
              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
-                              the internal clock; (APB, LSE, LSI or MSI).
+                              the internal clock; (APB, LSE or LSI).
              (+++) Prescaler: select the clock divider.
          (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
                as counter clock source.
@@ -1160,6 +1160,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
   /* Set the LPTIM state */
   hlptim->State= HAL_LPTIM_STATE_BUSY;
  
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); 
+  
+  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+ 
   /* Set TIMOUT bit to enable the timeout function */
   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
   
@@ -1198,6 +1204,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Set the LPTIM state */
   hlptim->State= HAL_LPTIM_STATE_BUSY;
   
+  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ 
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+  
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); 
+  
   /* Disable the Peripheral */
   __HAL_LPTIM_DISABLE(hlptim);
   
@@ -1293,6 +1305,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
                
   /* Set the LPTIM state */
   hlptim->State= HAL_LPTIM_STATE_BUSY;
+
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); 
+  
+  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  
   
   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
@@ -1338,6 +1356,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Set the LPTIM state */
   hlptim->State= HAL_LPTIM_STATE_BUSY;
   
+  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ 
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+  
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); 
+  
   /* Disable the Peripheral */
   __HAL_LPTIM_DISABLE(hlptim);
   
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h
index 8ffceb7a88..c2b76568ce 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_lptim.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of LPTIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c
index ad46c8670e..45f2db82a1 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_ltdc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   LTDC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the LTDC peripheral:
@@ -43,6 +43,19 @@
          for foreground or/and background layer using respectively the following 
          functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
          HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
+
+     (#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload.
+         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) 
+         then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Relaod”
+
+         After calling the “_NoReload” functions to set different color/format/layer settings, 
+         the program can call the function  “HAL_LTDC_Relaod” To apply(Reload) these settings. 
+         Function “HAL_LTDC_Relaod” can be called with the parameter  “ReloadType” 
+         set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
+         Function “HAL_LTDC_Relaod” can be called with the parameter  “ReloadType” 
+         set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, 
+         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
+           
                      
      (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()               
 
@@ -379,6 +392,27 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
       HAL_LTDC_LineEventCallback(hltdc);
     }
   }
+  /* Register reload Interrupt management ***************************************/
+  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)
+  {
+    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)
+    {
+      /* Disable the register reload interrupt */
+      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
+      
+      /* Clear the register reload flag */
+      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
+      
+      /* Change LTDC state */
+      hltdc->State = HAL_LTDC_STATE_READY;
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hltdc);
+      
+      /* Register reload interrupt Callback */
+      HAL_LTDC_ReloadEventCallback(hltdc);
+    }
+  }  
 }
 
 /**
@@ -406,11 +440,28 @@ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hltdc);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_LTDC_LineEventCallback could be implemented in the user file
    */
 }
 
+/**
+  * @brief  Reload Event callback.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+  
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
+   */
+}
+
 /**
   * @}
   */
@@ -1131,6 +1182,592 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
   return HAL_OK;
 }
 
+/**
+  * @brief  LTDC configuration relaod  .
+  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  ReloadType:       This parameter can be one of the following values :
+  *                           LTDC_RELOAD_IMMEDIATE : Immediate Reload
+  *                           LTDC_SRCR_VBR  : Reload in the next Vertical Blanking
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef  HAL_LTDC_Relaod(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
+{
+  assert_param(IS_LTDC_RELAOD(ReloadType));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;  
+  
+  /* Enable the Reload interrupt */  
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
+       
+  /* Apply Reload type */
+  hltdc->Instance->SRCR = ReloadType;        
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified without reloading
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload
+  * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    0 or 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{   
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+  
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  
+
+  /* Configure the LTDC Layer */  
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Do not Sets the Reload  */
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window size without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize:    LTDC Pixel per line
+  * @param  YSize:    LTDC Line number
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) 
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY; 
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = 0;
+  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+  /* update vertical start/stop */  
+  pLayerCfg->WindowY0 = 0;
+  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  pLayerCfg->ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  pLayerCfg->ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0:       LTDC window X offset
+  * @param  Y0:       LTDC window Y offset
+  * @param  LayerIdx:  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+  
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = X0;
+  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+  /* update vertical start/stop */
+  pLayerCfg->WindowY0 = Y0;
+  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format without reloading.
+  *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload
+  * @param  hltdc:       pointer to a LTDC_HandleTypeDfef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat: new pixel format value.
+  * @param  LayerIdx:    LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      0 or 1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  
+
+  /* Reconfigure the pixel format */
+  pLayerCfg->PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value without reloading.
+  *         Variant of the function HAL_LTDC_SetAlpha without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha:    new alpha value.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Alpha value */
+  pLayerCfg->Alpha = Alpha;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the frame buffer Address without reloading.
+  *         Variant of the function HAL_LTDC_SetAddress without immediate reload   
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address:  new address value.
+  * @param  LayerIdx: LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Address */
+  pLayerCfg->FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
+  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we 
+  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels 
+  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
+  *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+  *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  *         Variant of the function HAL_LTDC_SetPitch without immediate reload    
+  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+  * @param  LayerIdx:          LTDC layer index concerned by the modification of line pitch.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+  uint32_t tmp = 0;
+  uint32_t pitchUpdate = 0;
+  uint32_t pixelFormat = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+  
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+  
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  
+  /* get LayerIdx used pixel format */
+  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+  
+  if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4;
+  }
+  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3;
+  }
+  else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+          (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+          (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+         (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2;
+  }
+  else
+  {
+    tmp = 1;
+  }
+  
+  pitchUpdate = ((LinePitchInPixels * tmp) << 16);
+  
+  /* Clear previously set standard pitch */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+  
+  /* Set new line pitch value */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+  
+  /* Do not Sets the Reload  */
+  
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Configure the color keying without reloading.
+  *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  RGBValue: the color key value
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Configures the default color values */
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{  
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1   
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ 
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Do not Sets the Reload  */
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h
index a5149455af..ceb642d173 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_ltdc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of LTDC HAL module.
   ******************************************************************************
   * @attention
@@ -135,10 +135,10 @@ typedef struct
                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
 
   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
-                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
 
   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
-                                            This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
+                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
 
   uint32_t PixelFormat;                /*!< Specifies the pixel format. 
                                             This parameter can be one of value of @ref LTDC_Pixelformat */
@@ -344,6 +344,15 @@ typedef struct
   * @}
   */
 
+/** @defgroup LTDC_Reload_Type LTDC Reload Type
+  * @{
+  */
+#define LTDC_RELOAD_IMMEDIATE            LTDC_SRCR_IMR       /*!< Immediate Reload */
+#define LTDC_RELOAD_VERTICAL_BLANKING    LTDC_SRCR_VBR       /*!< Vertical Blanking Reload */
+/**
+  * @}
+  */
+
 /**
   * @}
   */  
@@ -484,6 +493,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
 void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
 void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
 void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
 /**
   * @}
   */
@@ -517,6 +527,20 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer
 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_Relaod(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+
 /**
   * @}
   */
@@ -603,6 +627,7 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
 #define IS_LTDC_CFBLL(CFBLL)                      ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
 #define IS_LTDC_CFBLNBR(CFBLNBR)                  ((CFBLNBR) <= LTDC_LINE_NUMBER)
 #define IS_LTDC_LIPOS(LIPOS)                      ((LIPOS) <= 0x7FFU)
+#define IS_LTDC_RELAOD(RELOADTYPE)                (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))
 /**
   * @}
   */ 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c
index 452fc5ca0a..25f36bd972 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_ltdc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   LTDC Extension HAL module driver.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h
index bbf1bc0ed9..b70e7f5c1c 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_ltdc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of LTDC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c
index 0ce13db031..4def84b0c6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_nand.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   NAND HAL module driver.
   *          This file provides a generic firmware to drive NAND memories mounted 
   *          as external device.
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h
index e710e14111..2d24354ea9 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c
index a4ab0ff0bf..12a3e3f878 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.
@@ -96,7 +96,8 @@
 #ifdef HAL_NOR_MODULE_ENABLED
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
       
@@ -139,6 +140,16 @@
       
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Variables NOR Private Variables
+  * @{
+  */
+
+static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
+
+/**
+  * @}
+  */
+
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup NOR_Exported_Functions NOR Exported Functions
@@ -194,6 +205,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
 
   /* Enable the NORSRAM device */
   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+  
+    /* Initialize NOR Memory Data Width*/
+  if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_8B;
+  }
+  else
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_16B;
+  }
 
   /* Check the NOR controller state */
   hnor->State = HAL_NOR_STATE_READY; 
@@ -304,7 +325,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
   /* Check the NOR controller state */
   if(hnor->State == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+     return HAL_BUSY;                                    
   }
   
   /* Select the NOR device address */
@@ -329,15 +350,15 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send read ID command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
 
   /* Read the NOR IDs */
-  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
-  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
-  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
-  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
+  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
   
   /* Check the NOR controller state */
   hnor->State = HAL_NOR_STATE_READY;
@@ -437,8 +458,8 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
 
   /* Read the data */
@@ -495,9 +516,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send program data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
 
   /* Write the data */
   NOR_WRITE(pAddress, *pData);
@@ -555,8 +576,8 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
   NOR_WRITE(uwAddress, 0x00F0U);
   
   /* Read buffer */
@@ -627,12 +648,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
   lastloadedaddress = (uint32_t)(uwAddress);
 
   /* Issue unlock command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); 
 
   /* Write Buffer Load Command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1U)); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); 
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U)); 
 
   /* Load Data into NOR Buffer */
   while(p_currentaddress <= p_endaddress)
@@ -699,11 +720,11 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send block erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
 
   /* Check the NOR memory status and update the controller state */
@@ -757,12 +778,12 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
   hnor->State = HAL_NOR_STATE_BUSY;  
     
   /* Send NOR chip erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
   
   /* Check the NOR memory status and update the controller state */
   hnor->State = HAL_NOR_STATE_READY;
@@ -814,13 +835,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
   hnor->State = HAL_NOR_STATE_BUSY;
   
   /* Send read CFI query command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
 
   /* read the NOR CFI information */
-  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
-  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
-  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
-  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
+  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
 
   /* Check the NOR controller state */
   hnor->State = HAL_NOR_STATE_READY;
@@ -1001,7 +1022,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
           STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
-          STM32F479xx */
+          STM32F479xx || STM32F412Zx || STM32F412Vx */
 #endif /* HAL_NOR_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h
index 1630a2706a..d0a47dbdf9 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
@@ -44,9 +44,10 @@
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx)
   #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -63,7 +64,8 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx)
 
 /* Exported typedef ----------------------------------------------------------*/
 /** @defgroup NOR_Exported_Types NOR Exported Types
@@ -268,7 +270,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   * @param  ADDRESS: NOR memory address 
   * @retval NOR shifted address value
   */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS)    (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS)    (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
                                                                                  ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
  
 /**
@@ -284,7 +286,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
-          STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx */
 /**
   * @}
   */ 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c
index f43472342f..c071bc8e9b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pccard.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   PCCARD HAL module driver.
   *          This file provides a generic firmware to drive PCCARD memories mounted 
   *          as external device.
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h
index 0d57074fe2..062adf654e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pccard.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of PCCARD HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c
index 30e0eff308..60d09d8d0b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -88,7 +88,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -328,6 +329,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
   uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
   uint32_t fifoemptymsk = 0U, temp = 0U;
   USB_OTG_EPTypeDef *ep;
+  uint32_t hclk = 180000000;
   
   /* ensure that we are in device mode */
   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -570,7 +572,71 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
       {
         hpcd->Init.speed            = USB_OTG_SPEED_FULL;
         hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  
-        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
+        
+        /* The USBTRD is configured according to the tables below, depending on AHB frequency 
+        used by application. In the low AHB frequency range it is used to stretch enough the USB response 
+        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access 
+        latency to the Data FIFO */
+        
+        if((hclk >= 14200000)&&(hclk < 15000000))
+        {
+          /* hclk Clock Range between 14.2-15 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 15000000)&&(hclk < 16000000))
+        {
+          /* hclk Clock Range between 15-16 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 16000000)&&(hclk < 17200000))
+        {
+          /* hclk Clock Range between 16-17.2 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 17200000)&&(hclk < 18500000))
+        {
+          /* hclk Clock Range between 17.2-18.5 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 18500000)&&(hclk < 20000000))
+        {
+          /* hclk Clock Range between 18.5-20 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 20000000)&&(hclk < 21800000))
+        {
+          /* hclk Clock Range between 20-21.8 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 21800000)&&(hclk < 24000000))
+        {
+          /* hclk Clock Range between 21.8-24 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 24000000)&&(hclk < 27700000))
+        {
+          /* hclk Clock Range between 24-27.7 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else if((hclk >= 27700000)&&(hclk < 32000000))
+        {
+          /* hclk Clock Range between 27.7-32 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
+        }
+        
+        else /* if(hclk >= 32000000) */
+        {
+          /* hclk Clock Range between 32-180 MHz */
+          hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
+        }  
       }
       
       HAL_PCD_ResetCallback(hpcd);
@@ -1249,7 +1315,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #endif /* HAL_PCD_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h
index 2b5d3bdbc3..3b1f6e52b7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_ll_usb.h"
    
@@ -330,7 +331,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
   * @}
   */ 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c
index 8ff1b800d9..678e3bb92a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -54,7 +54,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -136,7 +137,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
   return HAL_OK;
 }
 
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Activate LPM feature
   * @param  hpcd: PCD handle
@@ -182,7 +184,122 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m
   UNUSED(hpcd);
   UNUSED(msg);
 }
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/**
+  * @brief  HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Start BCD When device is connected */
+  if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
+  {
+    /* Enable DCD : Data Contact Detect */
+    USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+    
+    /* Wait Detect flag or a timeout is happen*/
+    while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > 1000U)
+      {
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+        return;
+      }
+    }
+    
+    /* Right response got */
+    HAL_Delay(100U); 
+    
+    /* Check Detect flag*/
+    if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
+    {
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+    }
+    
+    /*Primary detection: checks if connected to Standard Downstream Port  
+    (without charging capability) */
+    USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
+    USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+    HAL_Delay(100U); 
+    
+    if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
+    {
+      /* Case of Standard Downstream Port */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+    }
+    else  
+    {
+      /* start secondary detection to check connection to Charging Downstream 
+      Port or Dedicated Charging Port */
+      USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
+      USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+      HAL_Delay(100U); 
+      
+      if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
+      { 
+        /* case Dedicated Charging Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+      }
+      else
+      {
+        /* case Charging Downstream Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+      }
+    }
+    /* Battery Charging capability discovery finished */
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+  }
+}
+
+/**
+  * @brief  HAL_PCDEx_ActivateBCD : active BatteryCharging feature
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+
+  hpcd->battery_charging_active = ENABLE; 
+  USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  hpcd->battery_charging_active = DISABLE; 
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+  return HAL_OK;  
+}
+
+/**
+  * @brief  HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+}
+
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
 /**
   * @}
@@ -193,7 +310,8 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m
   */
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #endif /* HAL_PCD_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h
index db1f7635b4..af0ba32f29 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
    
@@ -57,13 +58,26 @@
   * @{
   */
 /* Exported types ------------------------------------------------------------*/
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 typedef enum  
 {
   PCD_LPM_L0_ACTIVE = 0x00U, /* on */
   PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
 }PCD_LPM_MsgTypeDef;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+typedef enum  
+{
+  PCD_BCD_ERROR                     = 0xFFU,
+  PCD_BCD_CONTACT_DETECTION         = 0xFEU,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFDU,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFCU,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFBU,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00U
+}PCD_BCD_MsgTypeDef;
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
 /* Exported constants --------------------------------------------------------*/
 /* Exported macros -----------------------------------------------------------*/
@@ -76,11 +90,20 @@ typedef enum
   */
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
+#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
 /**
   * @}
@@ -98,7 +121,8 @@ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c
index 988cdc8057..3c8e2f1cb6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Power Controller (PWR) peripheral:
@@ -167,8 +167,8 @@ void HAL_PWR_DisableBkUpAccess(void)
       (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
           forced in input pull-down configuration and is active on rising edges.
       (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
-         (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
-         (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
+	   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+           (++) For STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
 
     *** Low Power modes configuration ***
     =====================================
@@ -329,8 +329,8 @@ void HAL_PWR_DisablePVD(void)
   * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
   *         This parameter can be one of the following values:
   *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx devices
   * @retval None
   */
 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
@@ -347,8 +347,8 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
   *         This parameter can be one of the following values:
   *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
   * @retval None
   */
 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h
index 29728896f0..ea4c8b2f3b 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c
index 985381ff8f..1161134905 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of PWR extension peripheral:           
@@ -277,7 +277,8 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
 #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
       defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
       defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
-      defined(STM32F479xx)
+      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+      defined(STM32F412Cx)
 /**
   * @brief Configures the main internal regulator output voltage.
   * @param  VoltageScaling: specifies the regulator output voltage to achieve
@@ -387,10 +388,10 @@ void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
 #endif /* STM32F469xx || STM32F479xx */
 
 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE)
+    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief Enables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
   * @retval None
   */
 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
@@ -400,7 +401,7 @@ void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
 
 /**
   * @brief Disables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. 
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices. 
   * @retval None
   */
 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
@@ -410,7 +411,7 @@ void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
 
 /**
   * @brief Enables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
   * @retval None
   */
 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
@@ -420,7 +421,7 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
 
 /**
   * @brief Disables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices.   
   * @retval None
   */
 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
@@ -428,7 +429,7 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
   *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
 }
 
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h
index 236c4649a4..d3c6d56939 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
@@ -98,18 +98,21 @@
 /**
   * @}
   */
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
   * @{
   */
 #define PWR_WAKEUP_PIN2                 ((uint32_t)0x00000080U)
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) 
 #define PWR_WAKEUP_PIN3                 ((uint32_t)0x00000040U)
-#endif /* STM32F410xx */
+#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */   
-#endif /* STM32F410xx || STM32F446xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /**
   * @}
@@ -229,12 +232,14 @@ void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
 #endif /* STM32F469xx || STM32F479xx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
-    defined(STM32F401xE) || defined(STM32F411xE)
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
-#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
     defined(STM32F469xx) || defined(STM32F479xx)
@@ -332,7 +337,8 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
 
 #if defined(STM32F446xx)
 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
-#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+      defined(STM32F412Rx) || defined(STM32F412Cx)
 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
                                 ((PIN) == PWR_WAKEUP_PIN3))
 #else
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c
index 5ea83504a0..d70e47a4ca 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_qspi.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   QSPI HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the QuadSPI interface (QSPI).
@@ -15,6 +15,7 @@
   *           + DMA channel configuration for indirect functional mode
   *           + Errors management and abort functionality
   *
+  *
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -24,13 +25,13 @@
     ======================
     [..]
       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
-        (##) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
-        (##) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
-        (##) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
-        (##) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
-        (##) If interrupt mode is used, enable and configure QuadSPI global
+        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure QuadSPI global
             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
-        (##) If DMA mode is used, enable the clocks for the QuadSPI DMA channel 
+        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel 
             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), 
             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure 
             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
@@ -42,31 +43,31 @@
     [..]
       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() 
           functions :
-         (##) Instruction phase : the mode used and if present the instruction opcode.
-         (##) Address phase : the mode used and if present the size and the address value.
-         (##) Alternate-bytes phase : the mode used and if present the size and the alternate 
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
              bytes values.
-         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (##) Data phase : the mode used and if present the number of bytes.
-         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used and if present the number of bytes.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
              if activated.
-         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
       (#) If no data is required for the command, it is sent directly to the memory :
-         (##) In polling mode, the output of the function is done when the transfer is complete.
-         (##) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or 
           HAL_QSPI_Transmit_IT() after the command configuration :
-         (##) In polling mode, the output of the function is done when the transfer is complete.
-         (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
-         (##) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and 
+         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and 
              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or 
           HAL_QSPI_Receive_IT() after the command configuration :
-         (##) In polling mode, the output of the function is done when the transfer is complete.
-         (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold 
              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-         (##) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and 
+         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and 
              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
 
     *** Auto-polling functional mode ***
@@ -74,53 +75,65 @@
     [..]
       (#) Configure the command sequence and the auto-polling functional mode using the 
           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
-         (##) Instruction phase : the mode used and if present the instruction opcode.
-         (##) Address phase : the mode used and if present the size and the address value.
-         (##) Alternate-bytes phase : the mode used and if present the size and the alternate 
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
              bytes values.
-         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (##) Data phase : the mode used.
-         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
              if activated.
-         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (##) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
              the polling interval and the automatic stop activation.
       (#) After the configuration :
-         (##) In polling mode, the output of the function is done when the status match is reached. The
+         (++) In polling mode, the output of the function is done when the status match is reached. The
              automatic stop is activated to avoid an infinite loop.
-         (##) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
 
     *** Memory-mapped functional mode ***
     =====================================
     [..]
       (#) Configure the command sequence and the memory-mapped functional mode using the 
           HAL_QSPI_MemoryMapped() functions :
-         (##) Instruction phase : the mode used and if present the instruction opcode.
-         (##) Address phase : the mode used and the size.
-         (##) Alternate-bytes phase : the mode used and if present the size and the alternate 
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and the size.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate 
              bytes values.
-         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
-         (##) Data phase : the mode used.
-         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay 
              if activated.
-         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
-         (##) The timeout activation and the timeout period.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The timeout activation and the timeout period.
       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on 
           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
 
     *** Errors management and abort functionality ***
     ==================================================
     [..]
-      (#) HAL_QSPI_GetError() function gives the error rised during the last operation.
-      (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
+      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
+      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and 
+          flushes the fifo :
+         (++) In polling mode, the output of the function is done when the transfer 
+              complete bit is set and the busy bit cleared.
+         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when 
+              the transfer complete bi is set.
+
+    *** Control functions ***
+    =========================
+    [..]
       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
+      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
+      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold 
 
     *** Workarounds linked to Silicon Limitation ***
     ====================================================
     [..]
       (#) Workarounds Implemented inside HAL Driver
          (++) Extra data written in the FIFO at the end of a read transfer
-         
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -160,12 +173,13 @@
   */
 
 /** @defgroup QSPI QSPI
-  * @brief HAL QSPI module driver
+  * @brief QSPI HAL module driver
   * @{
   */
 #ifdef HAL_QSPI_MODULE_ENABLED
 
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx)
     
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -202,7 +216,8 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void QSPI_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
 /**
   * @}
@@ -239,6 +254,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
   
   /* Check the QSPI handle allocation */
   if(hqspi == NULL)
@@ -277,20 +293,20 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
   }
   
   /* Configure QSPI FIFO Threshold */
-  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
 
   /* Wait till BUSY flag reset */
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-  
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
   if(status == HAL_OK)
   {
                 
     /* Configure QSPI Clock Prescaler and Sample Shift */
-    MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
+    MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
         
     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), 
-               ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+               ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
     
     /* Enable the QSPI peripheral */
     __HAL_QSPI_ENABLE(hqspi);
@@ -348,10 +364,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
   * @param hqspi: QSPI handle
   * @retval None
   */
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_QSPI_MspInit can be implemented in the user file
    */ 
@@ -362,10 +379,11 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
   * @param hqspi: QSPI handle
   * @retval None
   */
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_QSPI_MspDeInit can be implemented in the user file
    */ 
@@ -403,22 +421,20 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
 {
   __IO uint32_t *data_reg;
-  uint32_t flag = 0U, itsource = 0U;
+  uint32_t flag = READ_REG(hqspi->Instance->SR);
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);
 
-  /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
-  
-  if((flag != RESET) && (itsource != RESET))
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+  if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
   {
     data_reg = &hqspi->Instance->DR;
 
     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
     {
       /* Transmission process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
       {
-        if (hqspi->TxXferCount > 0U)
+        if (hqspi->TxXferCount > 0)
         {
           /* Fill the FIFO until it is full */
           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
@@ -427,6 +443,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
         else
         {
           /* No more data available for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
           break;
         }
       }
@@ -434,9 +452,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
     {
       /* Receiving Process */
-      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
       {
-        if (hqspi->RxXferCount > 0U)
+        if (hqspi->RxXferCount > 0)
         {
           /* Read the FIFO until it is empty */
           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
@@ -445,6 +463,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
         else
         {
           /* All data have been received for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
           break;
         }
       }
@@ -455,13 +475,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
   }
 
   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
-  
-  if((flag != RESET) && (itsource != RESET))
+  else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
   {
     /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
 
     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
@@ -469,60 +486,102 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
     /* Transfer complete callback */
     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
     {
-      /* Clear Busy bit */
-      HAL_QSPI_Abort(hqspi);
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+
+/* Clear Busy bit */
+      HAL_QSPI_Abort_IT(hqspi);
       
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
       /* TX Complete callback */
       HAL_QSPI_TxCpltCallback(hqspi);
     }
     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
     {
-      data_reg = &hqspi->Instance->DR;
-      while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
       {
-        if (hqspi->RxXferCount > 0U)
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+      else
+      {
+        data_reg = &hqspi->Instance->DR;
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
         {
-          /* Read the last data received in the FIFO until it is empty */
-          *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
-          hqspi->RxXferCount--;
-        }
-        else
-        {
-          /* All data have been received for the transfer */
-          break;
+          if (hqspi->RxXferCount > 0)
+          {
+            /* Read the last data received in the FIFO until it is empty */
+            *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+            hqspi->RxXferCount--;
+          }
+          else
+          {
+            /* All data have been received for the transfer */
+            break;
+          }
         }
       }
-
       /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-      HAL_QSPI_Abort(hqspi);
+      HAL_QSPI_Abort_IT(hqspi);
       
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
       /* RX Complete callback */
       HAL_QSPI_RxCpltCallback(hqspi);
     }
     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
     {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
       /* Command Complete callback */
       HAL_QSPI_CmdCpltCallback(hqspi);
     }
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
 
-    /* Change state of QSPI */
-    hqspi->State = HAL_QSPI_STATE_READY;
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+      {
+        /* Abort called by the user */
+
+        /* Abort Complete callback */
+        HAL_QSPI_AbortCpltCallback(hqspi);
+      }
+      else 
+      {
+        /* Abort due to an error (eg :  DMA error) */
+
+        /* Error callback */
+        HAL_QSPI_ErrorCallback(hqspi);
+      }
+    }
   }
 
   /* QSPI Status Match interrupt occurred ------------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
-  
-  if((flag != RESET) && (itsource != RESET))
+  else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
   {
     /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
    
     /* Check if the automatic poll mode stop is activated */
-    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
     {
-      /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
-      __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
 
       /* Change state of QSPI */
       hqspi->State = HAL_QSPI_STATE_READY;
@@ -533,13 +592,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
   }
 
   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
-  
-  if((flag != RESET) && (itsource != RESET))
+  else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
   {
     /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
     
     /* Disable all the QSPI Interrupts */
     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
@@ -547,21 +603,30 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
     /* Set error code */
     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
     
-    /* Change state of QSPI */
-    hqspi->State = HAL_QSPI_STATE_ERROR;
-
-    /* Error callback */
-    HAL_QSPI_ErrorCallback(hqspi);
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Disable the DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      HAL_DMA_Abort_IT(hqspi->hdma);
+    }
+    else
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+      
+      /* Error callback */
+      HAL_QSPI_ErrorCallback(hqspi);
+    }
   }
 
-  /* QSPI Time out interrupt occurred -----------------------------------------*/
-  flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
-  itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
-  
-  if((flag != RESET) && (itsource != RESET))
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/
+  else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
   {
     /* Clear interrupt */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
     
     /* Time out callback */
     HAL_QSPI_TimeOutCallback(hqspi);
@@ -579,6 +644,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
   
   /* Check the parameters */
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
@@ -608,8 +674,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
   
   /* Process locked */
   __HAL_LOCK(hqspi);
-  
- if(hqspi->State == HAL_QSPI_STATE_READY)
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
   {
     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
@@ -617,7 +683,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
     hqspi->State = HAL_QSPI_STATE_BUSY;   
     
     /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
     
     if (status == HAL_OK)
     {
@@ -628,11 +694,9 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
       {
         /* When there is no data phase, the transfer start as soon as the configuration is done 
         so wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
         {
           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
           
@@ -669,7 +733,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
   */
 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
 {
-  HAL_StatusTypeDef status = HAL_ERROR;
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
   
   /* Check the parameters */
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
@@ -700,7 +765,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
   /* Process locked */
   __HAL_LOCK(hqspi);
 
-   if(hqspi->State == HAL_QSPI_STATE_READY)
+  if(hqspi->State == HAL_QSPI_STATE_READY)
   {
     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
@@ -708,36 +773,62 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
     hqspi->State = HAL_QSPI_STATE_BUSY;   
     
     /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-    
+   count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
+   do 
+   {
+     if (count-- == 0)
+     { 
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+        status = HAL_TIMEOUT;
+     }
+   } 
+   while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
+   
     if (status == HAL_OK)
     {
       if (cmd->DataMode == QSPI_DATA_NONE)
       {
-        /* When there is no data phase, the transfer start as soon as the configuration is done 
-        so activate TC and TE interrupts */
-        /* Enable the QSPI Transfer Error Interrupt */
-        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
       }
       
       /* Call the configuration function */
       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
       
-      if (cmd->DataMode != QSPI_DATA_NONE)
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done 
+        so activate TC and TE interrupts */
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+
+        /* Enable the QSPI Transfer Error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+      }
+      else
       {
         /* Update QSPI state */
         hqspi->State = HAL_QSPI_STATE_READY;   
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
       }
     }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
   }
   else
   {
     status = HAL_BUSY;   
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
   }
   
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
   /* Return function status */
   return status;
 }
@@ -752,35 +843,37 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
   */
 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
 {
-  HAL_StatusTypeDef status = HAL_OK;
+   HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
   __IO uint32_t *data_reg = &hqspi->Instance->DR;
 
   /* Process locked */
   __HAL_LOCK(hqspi);
-  
+
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
     if(pData != NULL )
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
       
       /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
       hqspi->pTxBuffPtr = pData;
     
       /* Configure QSPI: CCR register with functional as indirect write */
       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
 
-      while(hqspi->TxXferCount > 0U)
+      while(hqspi->TxXferCount > 0)
       {
         /* Wait until FT flag is set to send data */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
         { 
-          status = HAL_TIMEOUT;
           break;
         }
 
@@ -791,11 +884,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
       if (status == HAL_OK)
       {
         /* Wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
         {
           /* Clear Transfer Complete bit */
           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@@ -810,6 +901,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
     }
     else
     {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
       status = HAL_ERROR;
     }
   }
@@ -836,6 +928,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
 {
   HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
   __IO uint32_t *data_reg = &hqspi->Instance->DR;
 
@@ -844,16 +937,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
   
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     if(pData != NULL )
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
     
       /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
       hqspi->pRxBuffPtr = pData;
 
       /* Configure QSPI: CCR register with functional as indirect read */
@@ -862,12 +954,13 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
       /* Start the transfer by re-writing the address in AR register */
       WRITE_REG(hqspi->Instance->AR, addr_reg);
       
-      while(hqspi->RxXferCount > 0U)
+      while(hqspi->RxXferCount > 0)
       {
         /* Wait until FT or TC flag is set to read received data */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
+
+        if  (status != HAL_OK)
         { 
-          status = HAL_TIMEOUT;
           break;
         }
 
@@ -878,17 +971,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
       if (status == HAL_OK)
       {
         /* Wait until TC flag is set to go back in idle state */
-        if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
-        { 
-          status = HAL_TIMEOUT;
-        }
-        else
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if  (status == HAL_OK)
         {
           /* Clear Transfer Complete bit */
           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
           
-          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-          status = HAL_QSPI_Abort(hqspi);
+         /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+         status = HAL_QSPI_Abort(hqspi);
         }
       }
 
@@ -897,6 +988,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
     }
     else
     {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
       status = HAL_ERROR;
     }
   }
@@ -927,37 +1019,46 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
 
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     if(pData != NULL )
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
 
       /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
       hqspi->pTxBuffPtr = pData;
     
       /* Configure QSPI: CCR register with functional as indirect write */
       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
     
-      /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+      
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
       
     }
     else
     {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
       status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
     }
   }
   else
   {
     status = HAL_BUSY;
-  }
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
 
   return status;
 }
@@ -979,16 +1080,16 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
 
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
     if(pData != NULL )
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
     
       /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
       hqspi->pRxBuffPtr = pData;
 
       /* Configure QSPI: CCR register with functional as indirect read */
@@ -997,21 +1098,31 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
       /* Start the transfer by re-writing the address in AR register */
       WRITE_REG(hqspi->Instance->AR, addr_reg);
 
-      /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
     }
     else
     {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
       status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
     }
   }
   else
   {
     status = HAL_BUSY;   
-  }
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
 
   return status;
 }
@@ -1021,28 +1132,79 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
   * @param  hqspi: QSPI handle
   * @param  pData: pointer to data buffer
   * @note   This function is used only in Indirect Write Mode
+  * @note   If DMA peripheral access is configured as halfword, the number 
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number 
+  *         of data and the fifo threshold should be aligned on word
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
 {
   HAL_StatusTypeDef status = HAL_OK;
   uint32_t *tmp;
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
   
   /* Process locked */
   __HAL_LOCK(hqspi);
   
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    /* Clear the error code */                
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
     if(pData != NULL ) 
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->TxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword 
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 1);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on word 
+          => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 2);
+        }
+      }
+      
+      if (status == HAL_OK)
+      {
 
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
 
-      /* Configure counters and size of the handle */
-      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+      /* Configure size and pointer of the handle */
+      hqspi->TxXferSize = hqspi->TxXferCount;
       hqspi->pTxBuffPtr = pData;
     
       /* Configure QSPI: CCR register with functional mode as indirect write */
@@ -1057,6 +1219,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
       /* Set the DMA error callback */
       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
       
+      /* Clear the DMA abort callback */      
+      hqspi->hdma->XferAbortCallback = NULL;
+
       /* Configure the direction of the DMA */
       hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
@@ -1064,22 +1229,34 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
       /* Enable the QSPI transmit DMA Channel */
       tmp = (uint32_t*)&pData;
       HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
-    
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
     }
+    }
     else
     {
-      status = HAL_OK;
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
     }
   }
   else
   {
     status = HAL_BUSY;   
-  }
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
 
   return status;
 }
@@ -1089,6 +1266,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
   * @param  hqspi: QSPI handle
   * @param  pData: pointer to data buffer.
   * @note   This function is used only in Indirect Read Mode
+  * @note   If DMA peripheral access is configured as halfword, the number 
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number 
+  *         of data and the fifo threshold should be aligned on word
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
@@ -1096,63 +1277,123 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
   HAL_StatusTypeDef status = HAL_OK;
   uint32_t *tmp;
   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
   
   /* Process locked */
   __HAL_LOCK(hqspi);
   
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+    
     if(pData != NULL ) 
     {
-      hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-    
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-    
-      /* Configure counters and size of the handle */
-      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
-      hqspi->pRxBuffPtr = pData;
-
-      /* Set the QSPI DMA transfer complete callback */
-      hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
-    
-      /* Set the QSPI DMA Half transfer complete callback */
-      hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
-    
-      /* Set the DMA error callback */
-      hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->RxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword 
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 1);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
+        {
+          /* The number of data or the fifo threshold is not aligned on word 
+          => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 2);
+        }
+      }
       
-      /* Configure the direction of the DMA */
-      hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-      MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
-      /* Enable the DMA Channel */
-      tmp = (uint32_t*)&pData;
-      HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
-    
-      /* Configure QSPI: CCR register with functional as indirect read */
-      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-      /* Start the transfer by re-writing the address in AR register */
-      WRITE_REG(hqspi->Instance->AR, addr_reg);
-
-      /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      if (status == HAL_OK)
+      {
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+        
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+        
+        /* Configure size and pointer of the handle */
+        hqspi->RxXferSize = hqspi->RxXferCount;
+        hqspi->pRxBuffPtr = pData;
+        
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+        
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+        
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+        
+        /* Clear the DMA abort callback */      
+        hqspi->hdma->XferAbortCallback = NULL;
+        
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+        
+        /* Enable the DMA Channel */
+        tmp = (uint32_t*)&pData;
+        HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+        
+        /* Configure QSPI: CCR register with functional as indirect read */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+        
+        /* Start the transfer by re-writing the address in AR register */
+        WRITE_REG(hqspi->Instance->AR, addr_reg);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+        
+        /* Enable the QSPI transfer error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+        
+        /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      }
     }
     else
     {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
       status = HAL_ERROR;
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
     }
   }
   else
   {
     status = HAL_BUSY; 
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
   }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
-
+  
   return status;
 }
 
@@ -1168,33 +1409,34 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
   
   /* Check the parameters */
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
   {
-  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
   }
-
+  
   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
   {
     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
   }
-
+  
   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
   {
     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
   }
-
+  
   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+  
   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+  
   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
@@ -1204,49 +1446,47 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
   
   if(hqspi->State == HAL_QSPI_STATE_READY)
   {
-  
-  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
-  /* Update state */
-  hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
-  /* Wait till BUSY flag reset */
-  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
-  
-  if (status == HAL_OK)
-  {
-    /* Configure QSPI: PSMAR register with the status match value */
-    WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
-    /* Configure QSPI: PSMKR register with the status mask value */
-    WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
     
-    /* Configure QSPI: PIR register with the interval value */
-    WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
     
-    /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
-       (otherwise there will be an infinite loop in blocking mode) */
-    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
-               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
-    /* Call the configuration function */
-    cmd->NbData = cfg->StatusBytesSize;
-    QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
-    /* Wait until SM flag is set to go back in idle state */
-    if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
-    { 
-      status = HAL_TIMEOUT;
-    }
-    else
+    if (status == HAL_OK)
     {
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+      
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+      
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+      
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled 
+      (otherwise there will be an infinite loop in blocking mode) */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
+               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+      
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+      
+      /* Wait until SM flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
 
-      /* Update state */
-      hqspi->State = HAL_QSPI_STATE_READY;
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
     }
   }
-  }
   else
   {
     status = HAL_BUSY;   
@@ -1268,7 +1508,8 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
   */
 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
 {
-  HAL_StatusTypeDef status = HAL_ERROR;
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
   
   /* Check the parameters */
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
@@ -1276,26 +1517,26 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
   {
     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
   }
-
+  
   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
   {
     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
   }
-
+  
   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
   {
     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
   }
-
+  
   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+  
   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+  
   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
@@ -1304,49 +1545,68 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
   /* Process locked */
   __HAL_LOCK(hqspi);
   
-if(hqspi->State == HAL_QSPI_STATE_READY)
+  if(hqspi->State == HAL_QSPI_STATE_READY)
   {
     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
     
     /* Update state */
     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-    
+
     /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+    count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
+    do 
+    {
+      if (count-- == 0)
+      { 
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+        status = HAL_TIMEOUT;
+      }
+    } 
+    while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
     
     if (status == HAL_OK)
     {
       /* Configure QSPI: PSMAR register with the status match value */
       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-    
+      
       /* Configure QSPI: PSMKR register with the status mask value */
       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-    
+      
       /* Configure QSPI: PIR register with the interval value */
       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-    
+      
       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), 
                (cfg->MatchMode | cfg->AutomaticStop));
-            
+      
       /* Clear interrupt */
       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
-      /* Enable the QSPI Transfer Error and status match Interrupt */
-      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-    
+      
       /* Call the configuration function */
       cmd->NbData = cfg->StatusBytesSize;
       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+  
+      /* Enable the QSPI Transfer Error and status match Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
     }
   }
   else
   {
-    status = HAL_BUSY; 
-  }
+    status = HAL_BUSY;   
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hqspi);
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
   
   /* Return function status */
   return status;  
@@ -1363,6 +1623,7 @@ if(hqspi->State == HAL_QSPI_STATE_READY)
 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t tickstart = HAL_GetTick();
   
   /* Check the parameters */
   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
@@ -1403,33 +1664,34 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
     
     /* Wait till BUSY flag reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
-  
-  if (status == HAL_OK)
-  {
-    /* Configure QSPI: CR register with time out counter enable */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: CR register with timeout counter enable */
     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
 
     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
-    {
-      assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+      {
+        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+        
+        /* Configure QSPI: LPTR register with the low-power timeout value */
+        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+        
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
 
-      /* Configure QSPI: LPTR register with the low-power time out value */
-      WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
-      /* Enable the QSPI TimeOut Interrupt */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
-    }
-
-    /* Call the configuration function */
-    QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
-    
+        /* Enable the QSPI TimeOut Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+      }
+      
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
     }
   }
   else
   {
-    status = HAL_BUSY; 
-    
+    status = HAL_BUSY;   
   }
 
   /* Process unlocked */
@@ -1448,13 +1710,29 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_ErrorCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Command completed callbacks.
+  * @brief  Abort completed callback.
+  * @param  hqspi: QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Command completed callback.
   * @param  hqspi: QSPI handle
   * @retval None
   */
@@ -1462,6 +1740,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
    */
@@ -1476,6 +1755,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_RxCpltCallback could be implemented in the user file
    */
@@ -1486,10 +1766,11 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
   * @param  hqspi: QSPI handle
   * @retval None
   */
-__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_TxCpltCallback could be implemented in the user file
    */ 
@@ -1504,6 +1785,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
    */
@@ -1514,10 +1796,11 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
   * @param  hqspi: QSPI handle
   * @retval None
   */
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
    */ 
@@ -1532,6 +1815,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
    */
@@ -1546,6 +1830,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+    
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
    */
@@ -1560,6 +1845,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hqspi);
+  
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_QSPI_TimeOutCallback could be implemented in the user file
    */
@@ -1581,18 +1867,19 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
       (+) Check in run-time the state of the driver. 
       (+) Check the error code set during last operation.
       (+) Abort any operation.
-.....   
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Return the QSPI state.
+  * @brief  Return the QSPI handle state.
   * @param  hqspi: QSPI handle
   * @retval HAL state
   */
 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
 {
+  /* Return QSPI handle state */
   return hqspi->State;
 }
 
@@ -1613,25 +1900,93 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
 */
 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
 {
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Configure QSPI: CR register with Abort request */
-  SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
-  /* Wait until TC flag is set to go back in idle state */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  { 
-    status = HAL_TIMEOUT;
-  }
-  else
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Check if the state is in one of the busy states */
+  if ((hqspi->State & 0x2) != 0)
   {
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-    
-    /* Wait until BUSY flag is reset */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
 
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Abort DMA channel */
+      status = HAL_DMA_Abort(hqspi->hdma);
+      if(status != HAL_OK)
+      {
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+      }
+    }  
+    
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+    
+    /* Wait until TC flag is set to go back in idle state */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+
+    if(status == HAL_OK)
+    {
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+      
+      /* Wait until BUSY flag is reset */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+    }
+    
+    if (status == HAL_OK)
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+* @brief  Abort the current transmission (non-blocking function)
+* @param  hqspi: QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check if the state is in one of the busy states */
+  if ((hqspi->State & 0x2) != 0)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+    
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_ABORT;   
+    
+    /* Disable all interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
+    
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+      
+      /* Abort DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      HAL_DMA_Abort_IT(hqspi->hdma);
+    }  
+    else
+    {
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+      
+      /* Enable the QSPI Transfer Complete Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+      
+      /* Configure QSPI: CR register with Abort request */
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+    }
   }
 
   return status;
@@ -1647,9 +2002,51 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
   hqspi->Timeout = Timeout;
 }
 
+/** @brief Set QSPI Fifo threshold.
+  * @param  hqspi: QSPI handle.
+  * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FIFO threshold value */
+    hqspi->Init.FifoThreshold = Threshold;
+    
+    /* Configure QSPI FIFO Threshold */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, 
+               ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
+  }
+  else
+  {
+    status = HAL_BUSY;   
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/** @brief Get QSPI Fifo threshold.
+  * @param  hqspi: QSPI handle.
+  * @retval Fifo threshold (value between 1 and 16)
+  */
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+{
+  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
+}
+
 /**
-* @}
-*/
+  * @}
+  */
 
 /* Private functions ---------------------------------------------------------*/
  
@@ -1661,33 +2058,10 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)  
 {
   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hqspi->RxXferCount = 0U;
+  hqspi->RxXferCount = 0;
   
-  /* Wait for QSPI TC Flag */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  {
-    /* Time out Occurred */ 
-    HAL_QSPI_ErrorCallback(hqspi);
-  }
-  else
-  {
-    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
-    /* Disable the DMA channel */
-    HAL_DMA_Abort(hdma);
-
-    /* Clear Transfer Complete bit */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-    /* Workaround - Extra data written in the FIFO at the end of a read transfer */
-    HAL_QSPI_Abort(hqspi);
-    
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-    
-    HAL_QSPI_RxCpltCallback(hqspi);
-  }
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
 }
 
 /**
@@ -1698,33 +2072,10 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)     
 {
   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hqspi->TxXferCount = 0U;
+  hqspi->TxXferCount = 0;
   
-  /* Wait for QSPI TC Flag */
-  if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
-  {
-    /* Time out Occurred */ 
-    HAL_QSPI_ErrorCallback(hqspi);
-  }
-  else
-  {
-    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
-    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-  
-    /* Disable the DMA channel */
-    HAL_DMA_Abort(hdma);
-
-    /* Clear Transfer Complete bit */
-    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-    
-    /* Clear Busy bit */
-    HAL_QSPI_Abort(hqspi);
-
-    /* Update state */
-    hqspi->State = HAL_QSPI_STATE_READY;
-    
-    HAL_QSPI_TxCpltCallback(hqspi);
-  }
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
 }
 
 /**
@@ -1759,40 +2110,80 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)   
 {
   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hqspi->RxXferCount = 0U;
-  hqspi->TxXferCount = 0U;
-  hqspi->State       = HAL_QSPI_STATE_ERROR;
-  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
-
-  HAL_QSPI_ErrorCallback(hqspi);
+  
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+    hqspi->RxXferCount = 0;
+    hqspi->TxXferCount = 0;
+    hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
+    
+    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+    
+    /* Abort the QSPI */
+    HAL_QSPI_Abort_IT(hqspi);
+  }
 }
 
 /**
-  * @brief  This function wait a flag state until time out.
+  * @brief  DMA QSPI abort complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)   
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hqspi->RxXferCount = 0;
+  hqspi->TxXferCount = 0;
+
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)
+  {
+    /* DMA Abort called by QSPI abort */
+    /* Clear interrupt */
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+    
+    /* Enable the QSPI Transfer Complete Interrupt */
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+    
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+  }
+  else
+  {
+    /* DMA Abort called due to a transfer error interrupt */
+    /* Change state of QSPI */
+    hqspi->State = HAL_QSPI_STATE_READY;
+    
+    /* Error callback */
+    HAL_QSPI_ErrorCallback(hqspi);
+  }
+}
+/**
+  * @brief  Wait for a flag state until timeout.
   * @param  hqspi: QSPI handle
   * @param  Flag: Flag checked
   * @param  State: Value of the flag expected
   * @param  Timeout: Duration of the time out
+  * @param  tickstart: tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
-                                                        FlagStatus State, uint32_t Timeout)
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, 
+                                                        FlagStatus State, uint32_t tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = HAL_GetTick();
-  
   /* Wait until flag is in expected state */    
   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
   {
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hqspi->State     = HAL_QSPI_STATE_ERROR;
         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
         
-        return HAL_TIMEOUT;
+        return HAL_ERROR;
       }
     }
   }
@@ -1800,7 +2191,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
 }
 
 /**
-  * @brief  This function configures the communication registers
+  * @brief  Configure the communication registers.
   * @param  hqspi: QSPI handle
   * @param  cmd: structure that contains the command configuration information
   * @param  FunctionalMode: functional mode to configured
@@ -1808,7 +2199,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
-  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode  
+  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
   * @retval None
   */
 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
@@ -1818,7 +2209,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
   {
     /* Configure QSPI: DLR register with the number of data to read or write */
-    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
+    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
   }
       
   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -1833,7 +2224,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with instruction, address and alternate bytes ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
 
@@ -1848,7 +2239,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with instruction and alternate bytes ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | 
                                          cmd->Instruction | FunctionalMode));
       }
@@ -1860,7 +2251,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with instruction and address ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | 
                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | 
                                          cmd->Instruction | FunctionalMode));
 
@@ -1875,7 +2266,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with only instruction ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | 
                                          cmd->AddressMode | cmd->InstructionMode | cmd->Instruction  | 
                                          FunctionalMode));
       }
@@ -1893,7 +2284,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with address and alternate bytes ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
                                          cmd->InstructionMode | FunctionalMode));
 
@@ -1908,7 +2299,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with only alternate bytes ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | 
                                          FunctionalMode));
       }
@@ -1920,7 +2311,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         /*---- Command with only address ----*/
         /* Configure QSPI: CCR register with all communications parameters */
         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                         cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | 
+                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | 
                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | 
                                          FunctionalMode));
 
@@ -1937,22 +2328,17 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
         {
           /* Configure QSPI: CCR register with all communications parameters */
           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
-                                           cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | 
+                                           cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | 
                                            cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
         }
       }
     }
   }
 }
-
 /**
   * @}
   */
-
-/**
-  * @}
-  */
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx */
 
 #endif /* HAL_QSPI_MODULE_ENABLED */
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h
index 5b24072141..be5fa154fd 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_qspi.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of QSPI HAL module.
   ******************************************************************************
   * @attention
@@ -43,7 +43,8 @@
  extern "C" {
 #endif
 
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
 
@@ -108,6 +109,7 @@ typedef enum
   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
 }HAL_QSPI_StateTypeDef;
 
@@ -212,6 +214,7 @@ typedef struct
 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */
 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */
 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008U) /*!< Invalid parameters error */
 /**
   * @}
   */ 
@@ -566,6 +569,7 @@ HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_Comm
   */  
 /* Callback functions in non-blocking modes ***********************************/
 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
 
 /* QSPI indirect mode */
@@ -588,25 +592,13 @@ void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
   * @{
   */  
 /* Peripheral Control and State functions  ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
-uint32_t              HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef     HAL_QSPI_Abort   (QSPI_HandleTypeDef *hqspi);
-void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup QSPI_Private_Constants QSPI Private Constants
-  * @{
-  */
-
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
 /**
   * @}
   */
@@ -777,7 +769,11 @@ void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti
 /**
   * @}
   */
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+  
+/**
+  * @}
+  */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx */
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c
index 922bf686f0..23a2bbe187 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -235,7 +235,6 @@ __weak void HAL_RCC_DeInit(void)
   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
   *         supported by this API. User should request a transition to HSE Off
   *         first and then HSE On or HSE Bypass.
-  
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
@@ -701,6 +700,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
   }
 
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+
   /* Configure the source of time base considering new system clocks settings*/
   HAL_InitTick (TICK_INT_PRIORITY);
   
@@ -923,7 +925,6 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
   return SystemCoreClock;
 }
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h
index 1307ccec68..0718a34bc6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
@@ -230,7 +230,7 @@ typedef struct
 #define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
 #define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))   /*!< PLLR used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */
 /**
   * @}
   */
@@ -1337,6 +1337,39 @@ void HAL_RCC_CSSCallback(void);
                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
  
 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c
index 8eef6157c9..3543fa9d8d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Extension RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
@@ -91,7 +91,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Resets the RCC clock configuration to the default reset state.
   * @note   The default reset state of the clock configuration is given below:
@@ -128,10 +129,14 @@ void HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
   
   /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR); 
+  CLEAR_REG(RCC->CIR);
+  
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
 }
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /**
@@ -166,7 +171,10 @@ void HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
   
   /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR); 
+  CLEAR_REG(RCC->CIR);
+  
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
 }
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
@@ -278,6 +286,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*----------------------------- RTC configuration --------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
     
@@ -292,11 +303,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
-      }      
+      }
     }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
-    { 
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -304,9 +316,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-      
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
@@ -320,8 +332,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
   /*--------------------------------------------------------------------------*/
     
@@ -355,17 +367,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
   /*--------------------------------------------------------------------------*/
     
-  /*------------------------------ CK48 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
+  /*----------------------------- CLK48 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
   {
     /* Check the parameters */
-    assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
     
-    /* Configure the CK48 clock source */
+    /* Configure the CLK48 clock source */
     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
 
-    /* Enable the PLLSAI when it's used as clock source for CK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
+    /* Enable the PLLSAI when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
     {
       pllsaiused = 1U; 
     }
@@ -504,7 +516,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*--------------------------------------------------------------------------*/
     
   /*----------------------------- PLLSAI Configuration -----------------------*/
-  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
+  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
   if(pllsaiused == 1U)
   {
     /* Disable PLLSAI Clock */
@@ -545,9 +557,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
     }           
 
-    /*------ In Case of PLLSAI is selected as source clock for CK48 ----------*/   
-    /* In Case of PLLI2S is selected as source clock for CK48 */ 
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
+    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/   
+    /* In Case of PLLI2S is selected as source clock for CLK48 */ 
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
     {
       /* check for Parameters */
       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
@@ -592,7 +604,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
-                                        RCC_PERIPHCLK_CK48     | RCC_PERIPHCLK_SDIO     |\
+                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\
                                         RCC_PERIPHCLK_SPDIFRX;
   
   /* Get the PLLI2S Clock configuration --------------------------------------*/
@@ -632,7 +644,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   /* Get the FMPI2C1 clock configuration -------------------------------------*/
   PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
   
-  /* Get the CK48 clock configuration ----------------------------------------*/
+  /* Get the CLK48 clock configuration ----------------------------------------*/
   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
   
   /* Get the SDIO clock configuration ----------------------------------------*/
@@ -805,10 +817,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
                                   
   /*--------------------------- CLK48 Configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
   {
     /* Check the parameters */
-    assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
     
     /* Configure the CLK48 clock source */
     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
@@ -917,8 +929,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
      factor is common parameters for these peripherals */ 
   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 
      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             || 
-     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)            &&
-      (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)))
+     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&
+      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
   {
     /* Check the PLLSAI division factors */
     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
@@ -977,8 +989,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     
     /*---------------------------- CLK48 configuration ------------------------*/
     /* Configure the PLLSAI when it is used as clock source for CLK48 */
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) &&        
-       (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&        
+       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
     {
       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
       
@@ -1012,6 +1024,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*---------------------------- RTC configuration ---------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
     
@@ -1026,10 +1041,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
-      }      
+      }
     }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
     {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -1038,14 +1054,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+   
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
         
-        /* Wait till LSE is ready */
+        /* Wait till LSE is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -1054,8 +1070,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
   /*--------------------------------------------------------------------------*/
 
@@ -1082,7 +1098,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
                                         RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
                                         RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
-                                        RCC_PERIPHCLK_CK48       | RCC_PERIPHCLK_SDIO;
+                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;
   
   /* Get the PLLI2S Clock configuration --------------------------------------*/
   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
@@ -1100,7 +1116,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
   
-    /* Get the CK48 clock configuration --------------------------------------*/
+    /* Get the CLK48 clock configuration -------------------------------------*/
   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
   
   /* Get the SDIO clock configuration ----------------------------------------*/
@@ -1117,6 +1133,314 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 }
 #endif /* STM32F469xx || STM32F479xx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, LTDC RTC and TIM).
+  *         
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
+  *         the RTC clock source; in this case the Backup domain will be reset in  
+  *         order to modify the RTC Clock source, as consequence RTC registers (including 
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+  uint32_t plli2sq = 0U;
+  uint32_t plli2sused = 0U;
+
+  /* Check the peripheral clock selection parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+    
+  /*----------------------------------- I2S APB1 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+    
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U; 
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*----------------------------------- I2S APB2 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+    
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U; 
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*------------------------------------ RTC configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+    
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+    
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+        
+        /* Wait till LSE is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*------------------------------------ TIM configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*------------------------------------- FMPI2C1 Configuration --------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+    
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*------------------------------------- CLK48 Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+    
+    /* Configure the SDIO clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
+    {
+      plli2sused = 1U; 
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*------------------------------------- SDIO Configuration -----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+    
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+    
+  /*-------------------------------------- PLLI2S Configuration --------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
+     I2S on APB2*/
+  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+    /*-------------------- Set the PLL I2S clock -----------------------------*/
+    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
+    
+    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ 
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  ------------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 Audio clock source configuration -------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+    /* Configure the DFSDM1 Audio interface clock source */
+    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+  
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48     |\
+                                        RCC_PERIPHCLK_SDIO;
+  
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+
+  /* Get the I2S APB1 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+  
+  /* Get the I2S APB2 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+  
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the CLK48 clock configuration ----------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+  
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /**
   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
@@ -1141,6 +1465,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*---------------------------- RTC configuration ---------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
     
@@ -1155,11 +1482,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
-      }      
+      }
     }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
-    { 
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -1167,14 +1495,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-      
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
         
-        /* Wait till LSE is ready */
+        /* Wait till LSE is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -1183,8 +1511,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
   /*--------------------------------------------------------------------------*/
 
@@ -1436,6 +1764,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*---------------------------- RTC configuration ---------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
       
@@ -1452,11 +1783,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
         return HAL_TIMEOUT;
       }
     }
-      
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
     {
-      
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -1464,14 +1794,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-      
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
         
-        /* Wait till LSE is ready */
+        /* Wait till LSE is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -1480,8 +1810,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
   /*--------------------------------------------------------------------------*/
 
@@ -1610,15 +1940,18 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   /*---------------------------- RTC configuration ---------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
-      
+    
     /* Enable write access to Backup domain */
     PWR->CR |= PWR_CR_DBP;
-      
+    
     /* Get tick */
     tickstart = HAL_GetTick();
-      
+    
     while((PWR->CR & PWR_CR_DBP) == RESET)
     {
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -1626,9 +1959,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
         return HAL_TIMEOUT;
       }
     }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
-    { 
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -1636,9 +1970,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-      
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
@@ -1652,10 +1986,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
-
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
   return HAL_OK;
 }
 
@@ -1682,19 +2022,37 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   /* Get the RTC Clock configuration -----------------------------------------*/
   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-  
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */  
 }
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
   *         RCC_OscInitTypeDef.
   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
   *         contains the configuration information for the RCC Oscillators.
   * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
   * @note   This function add the PLL/PLLR factor management during PLL configuration this feature 
-  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices 
+  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices 
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
@@ -1725,21 +2083,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till HSE is disabled */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      }
-      
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
       
@@ -1907,24 +2250,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
-      }      
+      }
     }
     
-    /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-    
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-    
-    /* Wait till LSE is ready */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }    
-    } 
-    
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
     /* Check the LSE State */
@@ -1939,7 +2267,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
-        }       
+        }
       }
     }
     else
@@ -2044,7 +2372,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   * RCC configuration registers.
   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
   *
-  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
   * @note   This function add the PLL/PLLR factor management
   * @retval None
   */
@@ -2119,13 +2447,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
 }
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Select LSE mode
   *   
-  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.
   *     
   * @param  Mode: specifies the LSE mode.
   *          This parameter can be one of the following values:
@@ -2147,7 +2476,7 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
   }
 }
 
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F446xx)
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h
index 6b2c5ad077..ad3c5553d5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
@@ -83,11 +83,12 @@ typedef struct
   uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
                             This parameter must be a number between Min_Data = 4 and Max_Data = 15    */
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
   uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
-                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx devices. 
+                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
+                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. 
                             This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ 
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 
 }RCC_PLLInitTypeDef;
 
 #if defined(STM32F446xx)
@@ -182,8 +183,8 @@ typedef struct
   uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. 
                                       This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
 
-  uint32_t Clk48ClockSelection;     /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
   
   uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
@@ -209,12 +210,77 @@ typedef struct
                                       This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
   
   uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
   uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
 }RCC_PeriphCLKInitTypeDef;
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+                           
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+                                      
+  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+  
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
+
+  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
+
+  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /** 
   * @brief  PLLI2S Clock structure definition  
@@ -289,8 +355,8 @@ typedef struct
   uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
 #if defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t Clk48ClockSelection;  /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
+  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
 
   uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. 
                                       This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  
@@ -335,7 +401,10 @@ typedef struct
 
   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
 }RCC_PeriphCLKInitTypeDef;
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
 /**
@@ -350,6 +419,21 @@ typedef struct
 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
   * @{
   */
+/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define RCC_PERIPHCLK_I2S_APB1        ((uint32_t)0x00000001U)
+#define RCC_PERIPHCLK_I2S_APB2        ((uint32_t)0x00000002U)
+#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000004U)
+#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000008U)
+#define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000010U)
+#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00000020U)
+#define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000040U)
+#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000080U)
+#define RCC_PERIPHCLK_DFSDM1          ((uint32_t)0x00000100U)
+#define RCC_PERIPHCLK_DFSDM1_AUDIO    ((uint32_t)0x00000200U)
+#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
@@ -370,7 +454,7 @@ typedef struct
 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
 #define RCC_PERIPHCLK_CEC             ((uint32_t)0x00000040U)
 #define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000080U)
-#define RCC_PERIPHCLK_CK48            ((uint32_t)0x00000100U)
+#define RCC_PERIPHCLK_CLK48            ((uint32_t)0x00000100U)
 #define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000200U)
 #define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x00000400U)
 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000800U)
@@ -386,7 +470,7 @@ typedef struct
 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000040U)
-#define RCC_PERIPHCLK_CK48            ((uint32_t)0x00000080U)
+#define RCC_PERIPHCLK_CLK48            ((uint32_t)0x00000080U)
 #define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000100U)
 #endif /* STM32F469xx || STM32F479xx */
 /*----------------------------------------------------------------------------*/
@@ -410,6 +494,9 @@ typedef struct
 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000002U)
 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000004U)
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define RCC_PERIPHCLK_TIM            ((uint32_t)0x00000008U)
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      
 /*----------------------------------------------------------------------------*/
 /**
   * @}
@@ -417,7 +504,8 @@ typedef struct
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
   * @{
   */
@@ -427,7 +515,8 @@ typedef struct
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 
 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
   * @{
@@ -446,12 +535,13 @@ typedef struct
 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
   * @{
   */
-#if defined(STM32F446xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 #define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000002U)
 #define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000004U)
 #define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000006U)
 #define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000008U)
-#endif /* STM32F446xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */
@@ -492,11 +582,11 @@ typedef struct
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
       
 #if defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_CK48_Clock_Source  RCC CK48 Clock Source
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
   * @{
   */
-#define RCC_CK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
-#define RCC_CK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
+#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
 /**
   * @}
   */
@@ -504,7 +594,7 @@ typedef struct
 /** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
   * @{
   */
-#define RCC_SDIOCLKSOURCE_CK48              ((uint32_t)0x00000000U)
+#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
 #define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
 /**
   * @}
@@ -584,11 +674,11 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCCEx_CK48_Clock_Source  RCC CK48 Clock Source
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
   * @{
   */
-#define RCC_CK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
-#define RCC_CK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
 /**
   * @}
   */
@@ -596,7 +686,7 @@ typedef struct
 /** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
   * @{
   */
-#define RCC_SDIOCLKSOURCE_CK48              ((uint32_t)0x00000000U)
+#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
 #define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
 /**
   * @}
@@ -612,6 +702,85 @@ typedef struct
   */
 #endif /* STM32F446xx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
+  * @{
+  */
+#define RCC_PLLI2SCLKSOURCE_PLLSRC         ((uint32_t)0x00000000U)
+#define RCC_PLLI2SCLKSOURCE_EXT            ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source
+  * @{
+  */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1         ((uint32_t)0x00000000U)
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2         ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM1CLKSOURCE_APB2         ((uint32_t)0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYSCLK       ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
+#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
+#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
+#define RCC_CLK48CLKSOURCE_PLLI2SQ           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             ((uint32_t)0x00000000U)
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
   * @{
@@ -640,23 +809,16 @@ typedef struct
 #define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
 #define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
 #define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
-  * @{
-  */
-#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00U)
-#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01U)
 /**
   * @}
   */
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
   * @{
   */
@@ -666,10 +828,12 @@ typedef struct
   * @}
   */
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
   * @{
   */
@@ -678,12 +842,14 @@ typedef struct
 /**
   * @}
   */
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx)  
 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
   * @{
   */
@@ -695,7 +861,8 @@ typedef struct
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
@@ -748,14 +915,14 @@ typedef struct
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
@@ -1794,20 +1961,20 @@ typedef struct
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()	do { \
+                                      } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
@@ -1946,7 +2113,7 @@ typedef struct
 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
 #define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
                                                __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-											                         __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
 /**
   * @brief  Disable ETHERNET clock.
   */
@@ -1956,7 +2123,7 @@ typedef struct
 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
 #define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
                                                 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-											                          __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
 #endif /* STM32F407xx || STM32F417xx */
 /**
   * @}
@@ -2025,7 +2192,7 @@ typedef struct
   *         using it.
   * @{
   */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)                                      
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 
 
 #define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
@@ -2641,28 +2808,28 @@ typedef struct
   *         using it.   
   * @{
   */
-#define __HAL_RCC_GPIOD_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
                                       } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
                                       } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE()  	do { \
+#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         UNUSED(tmpreg); \
                                       } while(0)
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE()	do { \
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
@@ -2731,7 +2898,7 @@ typedef struct
   *         using it.
   * @{
   */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)                                       
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
 /**
   * @}
@@ -2810,7 +2977,7 @@ typedef struct
   * @}
   */ 
   
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable                                      
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
@@ -3311,14 +3478,14 @@ typedef struct
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
@@ -3373,7 +3540,7 @@ typedef struct
 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
                                               }while(0)
-                                        
+
 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
 /**
   * @}
@@ -3386,8 +3553,8 @@ typedef struct
   *         using it.
   * @{
   */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)                                    
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)   
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
 /**
   * @}
   */  
@@ -3482,21 +3649,21 @@ typedef struct
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
@@ -3704,20 +3871,20 @@ typedef struct
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()	do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()	do { \
+                                      } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
                                       __IO uint32_t tmpreg = 0x00U; \
                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
@@ -3832,7 +3999,7 @@ typedef struct
 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
 
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)                                        
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
 
 #define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
@@ -3996,35 +4163,35 @@ typedef struct
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
@@ -4146,21 +4313,21 @@ typedef struct
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
                                         __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         UNUSED(tmpreg); \
-					} while(0)
+                                      } while(0)
 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
@@ -4477,9 +4644,751 @@ typedef struct
 
 #endif /* STM32F446xx */
 /*----------------------------------------------------------------------------*/
+
+/*----------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx----------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+          
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   
+/**
+  * @}
+  */  
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx)
+#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F412Zx || STM32F412Vx */ 
+#if defined(STM32F412Rx)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F412Rx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
+
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx */ 
+#if defined(STM32F412Rx)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F412Rx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+/**
+  * @}
+  */  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#if defined(STM32F412Zx) || defined(STM32F412Vx)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F412Zx || STM32F412Vx */ 
+#if defined(STM32F412Cx)
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+
+#define __HAL_RCC_FSMC_FORCE_RESET()
+#define __HAL_RCC_QSPI_FORCE_RESET()
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()
+#define __HAL_RCC_QSPI_RELEASE_RESET()
+#endif /* STM32F412Cx */
+#if defined(STM32F412Rx)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F412Rx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx)
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F412Zx || STM32F412Vx */ 
+
+#if defined(STM32F412Rx)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F412Rx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
 /*------------------------------- PLL Configuration --------------------------*/
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
   * @note   This function must be used only when the main PLL is disabled.
   * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
@@ -4509,7 +5418,8 @@ typedef struct
   *     
   * @param  __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   This parameter is only available in STM32F446xx/STM32F469xx and STM32F479xx devices.
+  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
+            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
   *      
   */
 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
@@ -4553,14 +5463,15 @@ typedef struct
                             ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
                             ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \
                             ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
- #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+ #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /*----------------------------------------------------------------------------*/
                              
 /*----------------------------PLLI2S Configuration ---------------------------*/
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 
 /** @brief Macros to enable or disable the PLLI2S. 
   * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
@@ -4569,7 +5480,8 @@ typedef struct
 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
+          STM32F412Rx || STM32F412Cx */
 #if defined(STM32F446xx)
 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
   * @note   This macro must be used only when the PLLI2S is disabled.
@@ -4604,6 +5516,35 @@ typedef struct
                                ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
                                ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))             |\
                                ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  *
+  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SR__: specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *
+  * @param  __PLLI2SQ__: specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
+                               ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
+                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))             |\
+                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
 #else
 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
   * @note   This macro must be used only when the PLLI2S is disabled.
@@ -4967,31 +5908,31 @@ typedef struct
 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
 
 /** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__: specifies the CK48 clock source.
+  * @param  __SOURCE__: specifies the CLK48 clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. 
-  *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
   */
 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
 
 /** @brief  Macro to Get the CLK48 clock.
   * @retval The clock source can be one of the following values:
-  *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. 
-  *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
   */
 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
 
 /** @brief  Macro to configure the SDIO clock.
   * @param  __SOURCE__: specifies the SDIO clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
   */
 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
 
 /** @brief  Macro to Get the SDIO clock.
   * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
   */
 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
@@ -5015,31 +5956,31 @@ typedef struct
 #if defined(STM32F469xx) || defined(STM32F479xx)
       
 /** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__: specifies the CK48 clock source.
+  * @param  __SOURCE__: specifies the CLK48 clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. 
-  *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
   */
 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
 
 /** @brief  Macro to Get the CLK48 clock.
   * @retval The clock source can be one of the following values:
-  *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. 
-  *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
   */
 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
 
 /** @brief  Macro to configure the SDIO clock.
   * @param  __SOURCE__: specifies the SDIO clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
   */
 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
 
 /** @brief  Macro to Get the SDIO clock.
   * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
   */
 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  
@@ -5061,6 +6002,137 @@ typedef struct
       
 #endif /* STM32F469xx || STM32F479xx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+ /** @brief  Macro to configure the DFSDM1 clock.
+  * @param  __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
+  */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief  Macro to configure DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
+  * @param  __SOURCE__: specifies the DFSDM1 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
+  */
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
+
+/** @brief  Macro to Get DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
+  */
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
+
+/** @brief  Macro to configure I2S APB1 clock source selection.
+  * @param  __SOURCE__: specifies the I2S APB1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB1 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief  Macro to configure I2S APB2 clock source selection.
+  * @param  __SOURCE__: specifies the I2S APB2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB2 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).
+  * @note   This macro must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__: specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
+      
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__: specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__: specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__: specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /** @brief  Macro to configure I2S clock source selection.
   * @param  __SOURCE__: specifies the I2S clock source.
@@ -5119,7 +6191,8 @@ typedef struct
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /** @brief  Macro to configure the Timers clocks prescalers 
   * @note   This feature is only available with STM32F429x/439x Devices.  
   * @param  __PRESC__ : specifies the Timers clocks prescalers selection
@@ -5136,7 +6209,7 @@ typedef struct
 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
 
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
-          STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /*----------------------------------------------------------------------------*/
 
@@ -5198,9 +6271,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 #endif /* STM32F446xx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 /**
   * @}
   */ 
@@ -5232,22 +6306,28 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Alias word address of PLLI2SON bit */
 #define RCC_PLLI2SON_BIT_NUMBER    0x1A
 #define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 
 /* --- DCKCFGR Register ---*/
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 /* Alias word address of TIMPRE bit */
 #define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8C)
 #define RCC_TIMPRE_BIT_NUMBER          0x18
 #define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
+          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /* --- CFGR Register ---*/
 #define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
@@ -5262,6 +6342,16 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #define PLLI2S_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms  */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+      
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+/* --- PLLI2SCFGR Register ---*/
+#define RCC_PLLI2SCFGR_OFFSET            (RCC_OFFSET + 0x84U)
+/* Alias word address of PLLI2SSRC bit */
+#define RCC_PLLI2SSRC_BIT_NUMBER      0x16
+#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32) + (RCC_PLLI2SSRC_BIT_NUMBER * 4))
+      
+#define PLLI2S_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 /* Alias word address of MCO1EN bit */
@@ -5294,7 +6384,8 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))      
 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
          STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx || 
-         STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx */
+         STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx || 
+         STM32F412Vx || STM32F412Zx */
 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
 #endif  /* STM32F411xE */    
@@ -5303,10 +6394,13 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 
 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
@@ -5320,6 +6414,10 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
 #endif /* STM32F469xx || STM32F479xx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
@@ -5342,12 +6440,13 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
                                          ((VALUE) == RCC_PLLSAIDIVR_16))
 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
 
-#if defined(STM32F411xE) || defined(STM32F446xx)
+#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 #define IS_RCC_PLLI2SM_VALUE(VALUE)     ((VALUE) <= 63U)
  
 #define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
                                          ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F411xE || STM32F446xx */
+#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
@@ -5411,10 +6510,10 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
 #define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
                                            ((SOURCE) == RCC_CECCLKSOURCE_LSE))
 
-#define IS_RCC_CK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
-                                           ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
 
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
                                            ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
 
 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
@@ -5429,10 +6528,10 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
                                              ((VALUE) == RCC_PLLSAIP_DIV6) ||\
                                              ((VALUE) == RCC_PLLSAIP_DIV8))
  
-#define IS_RCC_CK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
-                                             ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
 
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
                                              ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
 
 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
@@ -5442,17 +6541,54 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
                                              ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
 #endif /* STM32F469xx || STM32F479xx */
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
+                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
+ 
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+                                              
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_APB2) || \
+                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || \
+                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
+
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx)
+      
 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx */
 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      
 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c
index c17f7f53c1..17fa2277b3 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rng.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   RNG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Random Number Generator (RNG) peripheral:
@@ -72,7 +72,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
 
 
 /* Private types -------------------------------------------------------------*/
@@ -512,7 +513,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
   */
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
+          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #endif /* HAL_RNG_MODULE_ENABLED */
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h
index c81ffae0b1..90c69f42be 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rng.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
@@ -46,7 +46,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx)
       
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
@@ -355,7 +356,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
   */ 
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
+          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c
index 7d74de96af..237f02e2e7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) peripheral:
@@ -960,8 +960,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
   */
 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
 {
-  uint32_t tickstart = 0U;
   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+  __IO uint32_t count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U) ;
   
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
@@ -1057,26 +1057,24 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     /* Clear flag alarm A */
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if (count-- == 0)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }  
-    }
-    
+      }
+    } 
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
+
     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
     /* Configure the Alarm A Sub Second register */
     hrtc->Instance->ALRMASSR = subsecondtmpreg;
@@ -1093,26 +1091,24 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     /* Clear flag alarm B */
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if (count-- == 0)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }  
-    }
 
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+    } 
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
+    
     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
     /* Configure the Alarm B Sub Second register */
     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h
index 37372fb2de..57b0b364f1 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c
index fb70cbd32a..9e3aa17de5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -241,7 +241,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
   
   hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
   hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
-  
+
+  /* Clear RTC Timestamp flag */
+  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
   
   /* Enable IT timestamp */ 
@@ -452,7 +455,18 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
   
   /* Configure the Tamper Interrupt in the RTC_TAFCR */
   hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-  
+
+  if(sTamper->Tamper == RTC_TAMPER_1)
+  {
+    /* Clear RTC Tamper 1 flag */
+    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+  }
+  else
+  {
+    /* Clear RTC Tamper 2 flag */
+    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);    
+  }
+
   /* RTC Tamper Interrupt Configuration: EXTI configuration */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
   
@@ -828,64 +842,64 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
   */
 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
 {
-  uint32_t tickstart = 0U;
-  
+  __IO uint32_t count;
+
   /* Check the parameters */
   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-  
+
   /* Process Locked */ 
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+  /* Check RTC WUTWF flag is reset only when wake up timer enabled */
   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
   {
-    tickstart = HAL_GetTick();
- 
     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+    count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if(count-- == 0U)
       {
-       /* Enable the write protection for RTC registers */
-       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-       hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-       /* Process Unlocked */ 
-       __HAL_UNLOCK(hrtc);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
 
-       return HAL_TIMEOUT;
+        return HAL_TIMEOUT;
       }
     }
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET);
   }
 
   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
 
-  tickstart = HAL_GetTick();
-
   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
+  do
   {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    if(count-- == 0U)
     {
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-      /* Process Unlocked */ 
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
 
       return HAL_TIMEOUT;
     }
   }
-  
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET);
+        
   /* Configure the Wake-up Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
 
@@ -894,26 +908,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
 
   /* Configure the clock source */
   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
+
   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-  
+
   EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
   
+  /* Clear RTC Wake Up timer Flag */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+  
   /* Configure the Interrupt in the RTC_CR register */
   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-  
+
   /* Enable the Wake-up Timer */
   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-    
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
   /* Process Unlocked */ 
   __HAL_UNLOCK(hrtc);
- 
+
   return HAL_OK;
 }
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h
index d8ce539d18..bb0e43b90c 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c
index 2a7ee49cbd..43e5a01c3a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c
@@ -2,27 +2,27 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sai.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SAI HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Serial Audio Interface (SAI) peripheral:
   *           + Initialization/de-initialization functions
   *           + I/O operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                   ##### How to use this driver #####
   ==============================================================================
-           
+
   [..]
     The SAI HAL driver can be used as follows:
-    
-    (#) Declare a SAI_HandleTypeDef handle structure.
+
+    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
-        (##) Enable the SAI interface clock.                      
+        (##) Enable the SAI interface clock.
         (##) SAI pins configuration:
             (+++) Enable the clock for the SAI GPIOs.
             (+++) Configure these SAI pins as alternate function pull-up.
@@ -38,15 +38,17 @@
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx Stream.
             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                 DMA Tx/Rx Stream.
 
-   (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_SAI_Init() function.
-   
-   -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
-       will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
-       inside the transmit and receive process.   
+    (#) The initialization can be done by two ways
+        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+  [..]
+    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+        inside the transmit and receive process.
 
   [..]
    (@) SAI Clock Source configuration is managed differently depending on the selected
@@ -58,75 +60,86 @@
             ClockSource field of SAI_InitTypeDef structure.
   [..]
    (@) Make sure that either:
-       (+@) I2S PLL is configured or 
-       (+@) SAI PLL is configured or 
-       (+@) External clock source is configured after setting correctly 
-            the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. 
-
+       (+@) I2S PLL is configured or
+       (+@) SAI PLL is configured or
+       (+@) External clock source is configured after setting correctly
+            the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
   [..]
-    (@) In master Tx mode: enabling the audio block immediately generates the bit clock 
-        for the external slaves even if there is no data in the FIFO, However FS signal 
+    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+        for the external slaves even if there is no data in the FIFO, However FS signal
         generation is conditioned by the presence of data in the FIFO.
 
   [..]
-    (@) In master Rx mode: enabling the audio block immediately generates the bit clock 
-        and FS signal for the external slaves. 
+    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+        and FS signal for the external slaves.
 
   [..]
-    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: 
-        (+@)  First bit Offset <= (SLOT size - Data size)
-        (+@)  Data size <= SLOT size
-        (+@)  Number of SLOT x SLOT size = Frame length
-        (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+        (+@) First bit Offset <= (SLOT size - Data size)
+        (+@) Data size <= SLOT size
+        (+@) Number of SLOT x SLOT size = Frame length
+        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
 
   [..]
-     Three operation modes are available within this driver:
+    Three operation modes are available within this driver :
 
-   *** Polling mode IO operation ***
-   =================================
-   [..]    
-     (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() 
-     (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
 
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]    
-     (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT() 
-     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT() 
-     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
-     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_ErrorCallback
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can 
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
 
-   *** DMA mode IO operation ***
-   ==============================
-   [..] 
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA() 
-     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA() 
-     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
-     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_SAI_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
-     (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
-     (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+    *** DMA mode IO operation ***
+    =============================
+    [..]
+      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
 
-   *** SAI HAL driver macros list ***
-   =============================================
-   [..]
-     Below the list of most used macros in USART HAL driver :
-       
-      (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
-      (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
-      (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
-      (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
-      (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is
+    *** SAI HAL driver additional function list ***
+    ===============================================
+    [..]
+      Below the list the others API available SAI HAL driver :
+
+      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+      (+) HAL_SAI_Abort(): Abort the current transfer
+
+    *** SAI HAL driver macros list ***
+    ==================================
+    [..]
+      Below the list of most used macros in SAI HAL driver :
+
+      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
           enabled or disabled
-      (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
+      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
 
   @endverbatim
   ******************************************************************************
@@ -176,7 +189,6 @@
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 
-/* Private typedef -----------------------------------------------------------*/
 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
   * @{
   */
@@ -187,26 +199,26 @@ typedef enum {
 /**
   * @}
   */
+
 /* Private define ------------------------------------------------------------*/
+
 /** @defgroup SAI_Private_Constants  SAI Private Constants
   * @{
   */
-#define SAI_FIFO_SIZE       8U
-#define SAI_DEFAULT_TIMEOUT 4U
+#define SAI_FIFO_SIZE         8U
+#define SAI_DEFAULT_TIMEOUT   4U /* 4ms */
 #define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
 /**
   * @}
   */
 
-/* SAI registers Masks */
-#define CR1_CLEAR_MASK            ((uint32_t)0xFF04C010U)
-#define FRCR_CLEAR_MASK           ((uint32_t)0xFFF88000U)
-#define SLOTR_CLEAR_MASK          ((uint32_t)0x0000F020U)
-
-#define SAI_TIMEOUT_VALUE         10U
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions  SAI Private Functions
+  * @{
+  */
 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
@@ -225,30 +237,34 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
 
 /* Exported functions ---------------------------------------------------------*/
 
-/** @defgroup SAI_Exported_Functions  SAI Exported Functions
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
   * @{
   */
 
-/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
  ===============================================================================
-              ##### Initialization and de-initialization functions #####
+            ##### Initialization and de-initialization functions #####
  ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
-          de-initialize the SAIx peripheral:
+  [..]  This subsection provides a set of functions allowing to initialize and
+        de-initialize the SAIx peripheral:
 
-      (+) User must implement HAL_SAI_MspInit() function in which he configures 
+      (+) User must implement HAL_SAI_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 
-      (+) Call the function HAL_SAI_Init() to configure the selected device with 
+      (+) Call the function HAL_SAI_Init() to configure the selected device with
           the selected configuration:
         (++) Mode (Master/slave TX/RX)
-        (++) Protocol 
+        (++) Protocol
         (++) Data Size
         (++) MCLK Output
         (++) Audio frequency
@@ -256,40 +272,40 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma);
         (++) Frame Config
         (++) Slot Config
 
-      (+) Call the function HAL_SAI_DeInit() to restore the default configuration 
-          of the selected SAI peripheral.     
+      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+          of the selected SAI peripheral.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the structure FrameInit, SlotInit and the low part of 
+  * @brief  Initialize the structure FrameInit, SlotInit and the low part of
   *         Init according to the specified parameters and call the function
   *         HAL_SAI_Init to initialize the SAI block.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains 
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
   *               the configuration information for SAI module.
-  * @param  protocol : one of the supported protocol @ref SAI_Protocol
-  * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
-  *                the configuration information for SAI module.
-  * @param  nbslot   : Number of slot.
+  * @param  protocol: one of the supported protocol @ref SAI_Protocol
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+  *                   the configuration information for SAI module.
+  * @param  nbslot: Number of slot.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Check the parameters */
   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
-  
+
   switch(protocol)
   {
   case SAI_I2S_STANDARD :
   case SAI_I2S_MSBJUSTIFIED :
   case SAI_I2S_LSBJUSTIFIED :
     status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
-    break;  
+    break;
   case SAI_PCM_LONG :
   case SAI_PCM_SHORT :
     status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
@@ -308,33 +324,35 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco
 }
 
 /**
-  * @brief  Initializes the SAI according to the specified parameters 
-  *         in the SAI_InitTypeDef and create the associated handle.
+  * @brief  Initialize the SAI according to the specified parameters.
+  *         in the SAI_InitTypeDef structure and initialize the associated handle.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
 { 
-  uint32_t tmpclock = 0U;
+  uint32_t tmpregisterGCR = 0U;
 
   /* This variable used to store the SAI_CK_x (value in Hz) */
   uint32_t freq = 0U;
-  
+
   /* This variable is used to compute CKSTR bits of SAI CR1 according to
      ClockStrobing and AudioMode fields */
   uint32_t ckstr_bits = 0U;
-  
   uint32_t syncen_bits = 0U;
-  
+
   /* Check the SAI handle allocation */
   if(hsai == NULL)
   {
     return HAL_ERROR;
   }
-  
+
+  /* check the instance */
+  assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+
   /* Check the SAI Block parameters */
-  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));  
+  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
@@ -348,53 +366,53 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
-  
+
   /* Check the SAI Block Frame parameters */
   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
-  
+
   /* Check the SAI Block Slot parameters */
   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
-  
+
   if(hsai->State == HAL_SAI_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hsai->Lock = HAL_UNLOCKED;
-    
+
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_SAI_MspInit(hsai);
   }
-  
+
   hsai->State = HAL_SAI_STATE_BUSY;
-  
+
   /* Disable the selected SAI peripheral */
   SAI_Disable(hsai);
-  
+
   /* SAI Block Synchro Configuration -----------------------------------------*/
   SAI_BlockSynchroConfig(hsai);
-    
+
   /* Configure Master Clock using the following formula :
      MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
      FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
      MCKDIV[3:0] = SAI_CK_x / FS * 512 */
   if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
   { 
-  /* Get SAI clock source based on Source clock selection from RCC */
-  freq = SAI_GetInputClock(hsai);
+    /* Get SAI clock source based on Source clock selection from RCC */
+    freq = SAI_GetInputClock(hsai);
 
     /* (saiclocksource x 10) to keep Significant digits */
-    tmpclock = (((freq * 10U) / ((hsai->Init.AudioFrequency) * 512U)));
-    
-    hsai->Init.Mckdiv = tmpclock / 10U;
-    
-        /* Round result to the nearest integer */
-    if((tmpclock % 10U) > 8U) 
+    tmpregisterGCR = (((freq * 10U) / ((hsai->Init.AudioFrequency) * 512U)));
+
+    hsai->Init.Mckdiv = tmpregisterGCR / 10U;
+
+    /* Round result to the nearest integer */
+    if((tmpregisterGCR % 10U) > 8U) 
     {
       hsai->Init.Mckdiv+= 1U;
     }
@@ -409,7 +427,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
   {
     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR: 0U;
   }
-  
+
   /* SAI Block Configuration -------------------------------------------------*/
   switch(hsai->Init.Synchro)
   {
@@ -430,9 +448,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
     }
     break;
   default:
-    syncen_bits = 0U;
     break;
-  }  
+  }
   /* SAI CR1 Configuration */
   hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
@@ -443,20 +460,20 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
                           ckstr_bits | syncen_bits |                             \
                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
-                          hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20U));  
+                          hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20U));
 
   /* SAI CR2 Configuration */
   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
   hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
 
   /* SAI Frame Configuration -----------------------------------------*/
-  hsai->Instance->FRCR &= ~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
-                           SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF);
-  hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U)  | \
-                            hsai->FrameInit.FSOffset |          \
-                            hsai->FrameInit.FSDefinition |      \
-                            hsai->FrameInit.FSPolarity   |      \
-                            ((hsai->FrameInit.ActiveFrameLength - 1U) << 8U));
+  hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+                           SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+  hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1U) |
+                          hsai->FrameInit.FSOffset     |
+                          hsai->FrameInit.FSDefinition |
+                          hsai->FrameInit.FSPolarity   |
+                          ((hsai->FrameInit.ActiveFrameLength - 1U) << 8U));
 
   /* SAI Block_x SLOT Configuration ------------------------------------------*/
   /* This register has no meaning in AC 97 and SPDIF audio protocol */
@@ -464,7 +481,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN );
 
   hsai->Instance->SLOTR |=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize  | \
-                           (hsai->SlotInit.SlotActive << 16U) | ((hsai->SlotInit.SlotNumber - 1U) <<  8U);
+                            (hsai->SlotInit.SlotActive << 16U) | ((hsai->SlotInit.SlotNumber - 1U) <<  8U);
 
   /* Initialize the error code */
   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
@@ -479,9 +496,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  DeInitializes the SAI peripheral.
+  * @brief  DeInitialize the SAI peripheral.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
@@ -497,19 +514,19 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
   /* Disabled All interrupt and clear all the flag */
   hsai->Instance->IMR = 0U;
   hsai->Instance->CLRFR = 0xFFFFFFFFU;
-  
+
   /* Disable the SAI */
   SAI_Disable(hsai);
 
   /* Flush the fifo */
   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
-  
+
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
   HAL_SAI_MspDeInit(hsai);
 
   /* Initialize the error code */
   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-  
+
   /* Initialize the SAI state */
   hsai->State = HAL_SAI_STATE_RESET;
 
@@ -520,90 +537,90 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief SAI MSP Init.
+  * @brief Initialize the SAI MSP.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
+
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief SAI MSP DeInit.
+  * @brief DeInitialize the SAI MSP.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
+
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup SAI_Exported_Functions_Group2 IO operation functions 
- *  @brief   Data transfers functions 
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+ *  @brief    Data transfers functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                       ##### IO operation functions #####
   ==============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the SAI data 
+  [..]
+    This subsection provides a set of functions allowing to manage the SAI data
     transfers.
 
     (+) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
-            The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode : The communication is performed using Interrupts 
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
+      (++) Blocking mode : The communication is performed in the polling mode.
+           The status of all data processing is returned by the same function
+           after finishing transfer.
+      (++) No-Blocking mode : The communication is performed using Interrupts
+           or DMA. These functions return the status of the transfer startup.
+           The end of the data processing will be indicated through the
+           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
 
     (+) Blocking mode functions are :
-        (++) HAL_SAI_Transmit()
-        (++) HAL_SAI_Receive()
-        (++) HAL_SAI_TransmitReceive()
-        
+      (++) HAL_SAI_Transmit()
+      (++) HAL_SAI_Receive()
+      (++) HAL_SAI_TransmitReceive()
+
     (+) Non Blocking mode functions with Interrupt are :
-        (++) HAL_SAI_Transmit_IT()
-        (++) HAL_SAI_Receive_IT()
-        (++) HAL_SAI_TransmitReceive_IT()
+      (++) HAL_SAI_Transmit_IT()
+      (++) HAL_SAI_Receive_IT()
+      (++) HAL_SAI_TransmitReceive_IT()
 
     (+) Non Blocking mode functions with DMA are :
-        (++) HAL_SAI_Transmit_DMA()
-        (++) HAL_SAI_Receive_DMA()
-        (++) HAL_SAI_TransmitReceive_DMA()
+      (++) HAL_SAI_Transmit_DMA()
+      (++) HAL_SAI_Receive_DMA()
+      (++) HAL_SAI_TransmitReceive_DMA()
 
     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_SAI_TxCpltCallback()
-        (++) HAL_SAI_RxCpltCallback()
-        (++) HAL_SAI_ErrorCallback()
+      (++) HAL_SAI_TxCpltCallback()
+      (++) HAL_SAI_RxCpltCallback()
+      (++) HAL_SAI_ErrorCallback()
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Transmits an amount of data in blocking mode.
+  * @brief  Transmit an amount of data in blocking mode.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be sent
   * @param  Timeout: Timeout duration
@@ -629,7 +646,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
     hsai->State = HAL_SAI_STATE_BUSY_TX;
     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
 
-    /* Check if the SAI is already enabled */ 
+    /* Check if the SAI is already enabled */
     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* fill the fifo with data before to enabled the SAI */
@@ -644,7 +661,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
       {
         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
-        {      
+        {
           hsai->Instance->DR = (*hsai->pBuffPtr++);
         }
         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
@@ -656,20 +673,33 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
         {
           hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
           hsai->pBuffPtr+= 4U;
-        }       
-        hsai->XferCount--; 
+        }
+        hsai->XferCount--;
       }
       else
       {
         /* Check for the Timeout */
-        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)))
+        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart) > Timeout)))
         {
           /* Update error code */
           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
           /* Change the SAI state */
-          hsai->State = HAL_SAI_STATE_TIMEOUT;
-          
-          return HAL_TIMEOUT;
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
         }
       }
     }
@@ -688,9 +718,9 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint
 }
 
 /**
-  * @brief  Receives an amount of data in blocking mode. 
+  * @brief  Receive an amount of data in blocking mode.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be received
   * @param  Timeout: Timeout duration
@@ -716,7 +746,7 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
     hsai->State = HAL_SAI_STATE_BUSY_RX;
     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
 
-    /* Check if the SAI is already enabled */ 
+    /* Check if the SAI is already enabled */
     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */
@@ -751,19 +781,32 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
         {
           /* Update error code */
           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
           /* Change the SAI state */
-          hsai->State = HAL_SAI_STATE_TIMEOUT;
-          
-          return HAL_TIMEOUT;
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
         }
       }
     }
 
-    hsai->State = HAL_SAI_STATE_READY; 
-    
+    hsai->State = HAL_SAI_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hsai);
-    
+
     return HAL_OK;
   }
   else
@@ -773,9 +816,9 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
 }
 
 /**
-  * @brief  Transmits an amount of data in no-blocking mode with Interrupt.
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be sent
   * @retval HAL status
@@ -817,7 +860,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u
     /* Enable FRQ and OVRUDR interrupts */
     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
 
-    /* Check if the SAI is already enabled */ 
+    /* Check if the SAI is already enabled */
     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */
@@ -835,9 +878,9 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u
 }
 
 /**
-  * @brief  Receives an amount of data in no-blocking mode with Interrupt.
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be received
   * @retval HAL status
@@ -895,9 +938,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui
 }
 
 /**
-  * @brief Pauses the audio stream playing from the Media.
+  * @brief Pause the audio stream playing from the Media.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
@@ -911,13 +954,13 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
   /* Process Unlocked */
   __HAL_UNLOCK(hsai);
 
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
-  * @brief Resumes the audio stream playing from the Media.
+  * @brief Resume the audio stream playing from the Media.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
@@ -942,9 +985,9 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief Stops the audio stream playing from the Media.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  * @brief Stop the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
@@ -954,8 +997,8 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
 
   /* Disable the SAI DMA request */
   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-  
-  /* Abort the SAI DMA Tx Stream */
+
+  /* Abort the SAI DMA Streams */
   if(hsai->hdmatx != NULL)
   {
     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
@@ -963,9 +1006,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
       return HAL_ERROR;
     }
   }
-  /* Abort the SAI DMA Rx Stream */
+
   if(hsai->hdmarx != NULL)
-  {  
+  {
     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
     {
       return HAL_ERROR;
@@ -984,30 +1027,37 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief Abort the current transfer and disbaled the SAI.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  * @brief Abort the current transfer and disable the SAI.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
 {
-  /* Disable the SAI DMA request */
-  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+  /* Process Locked */
+  __HAL_LOCK(hsai);
 
-  /* Abort the SAI DMA Tx Stream */
-  if(hsai->hdmatx != NULL)
+  /* Check SAI DMA is enabled or not */
+  if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
   {
-    if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+    
+    /* Abort the SAI DMA Streams */
+    if(hsai->hdmatx != NULL)
     {
-      return HAL_ERROR;
+      if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
     }
-  }
-  /* Abort the SAI DMA Rx Stream */
-  if(hsai->hdmarx != NULL)
-  {
-    if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    
+    if(hsai->hdmarx != NULL)
     {
-      return HAL_ERROR;
+      if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
     }
   }
 
@@ -1030,17 +1080,15 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Transmits an amount of data in no-blocking mode with DMA.
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
 {
-  uint32_t *tmp;
-
   if((pData == NULL) || (Size == 0U)) 
   {
     return  HAL_ERROR;
@@ -1066,11 +1114,17 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData,
     /* Set the DMA error callback */
     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
 
-    /* Enable the Tx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
+    /* Set the DMA Tx abort callback */
+    hsai->hdmatx->XferAbortCallback = NULL;
 
-    /* Check if the SAI is already enabled */ 
+    /* Enable the Tx DMA Stream */
+    if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+
+    /* Check if the SAI is already enabled */
     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
     {
       /* Enable SAI peripheral */
@@ -1095,18 +1149,16 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData,
 }
 
 /**
-  * @brief  Receives an amount of data in no-blocking mode with DMA. 
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @param  pData: Pointer to data buffer
   * @param  Size: Amount of data to be received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
 {
-  uint32_t *tmp;
-
-  if((pData == NULL) || (Size == 0U))
+  if((pData == NULL) || (Size == 0))
   {
     return  HAL_ERROR;
   }
@@ -1131,9 +1183,15 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
     /* Set the DMA error callback */
     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
 
+    /* Set the DMA Rx abort callback */
+    hsai->hdmarx->XferAbortCallback = NULL;
+
     /* Enable the Rx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
+    if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
 
     /* Check if the SAI is already enabled */
     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
@@ -1160,10 +1218,10 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
 }
 
 /**
-  * @brief  Enable the tx mute mode.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @param  val :  value sent during the mute @ref SAI_Block_Mute_Value
+  * @brief  Enable the Tx mute mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  val:  value sent during the mute @ref SAI_Block_Mute_Value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
@@ -1180,9 +1238,9 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val
 }
 
 /**
-  * @brief  Disable the tx mute mode.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  * @brief  Disable the Tx mute mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
@@ -1196,17 +1254,17 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Enable the rx mute detection.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @param  callback : function called when the mute is detected
-  * @param  counter : number a data before mute detection max 63.
+  * @brief  Enable the Rx mute detection.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  callback: function called when the mute is detected.
+  * @param  counter: number a data before mute detection max 63.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
 {
   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
-  
+
   if(hsai->State != HAL_SAI_STATE_RESET)
   {
     /* set the mute counter */
@@ -1221,9 +1279,9 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback
 }
 
 /**
-  * @brief  Disable the rx mute detection.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  * @brief  Disable the Rx mute detection.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
@@ -1240,166 +1298,264 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  This function handles SAI interrupt request.
+  * @brief  Handle SAI interrupt request.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval HAL status
+  *               the configuration information for SAI module.
+  * @retval None
   */
 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
 {
   if(hsai->State != HAL_SAI_STATE_RESET)
   {
-    uint32_t tmpFlag = hsai->Instance->SR;
-    uint32_t tmpItSource = hsai->Instance->IMR; 
-    
-    if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))
+    uint32_t itflags = hsai->Instance->SR;
+    uint32_t itsources = hsai->Instance->IMR;
+    uint32_t cr1config = hsai->Instance->CR1;
+    uint32_t tmperror;
+
+    /* SAI Fifo request interrupt occured ------------------------------------*/
+    if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
     {
       hsai->InterruptServiceRoutine(hsai);
     }
-    
-    /* check the flag only if one of them is set */
-    if(tmpFlag != 0x00000000U)
+    /* SAI Overrun error interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
     {
-      /* SAI Overrun error interrupt occurred --------------------------------*/
-      if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+      /* Clear the SAI Overrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+      /* Get the SAI error code */
+      tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= tmperror;
+
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+      HAL_SAI_ErrorCallback(hsai);
+    }
+    /* SAI mutedet interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+    {
+      /* Clear the SAI mutedet flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+
+      /* call the call back function */
+      if(hsai->mutecallback != (SAIcallback)NULL)
       {
-        /* Clear the SAI Overrun flag */
-        __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
-        /* Change the SAI error code */
-        hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
-        /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
-        HAL_SAI_ErrorCallback(hsai);
+        /* inform the user that an RX mute event has been detected */
+        hsai->mutecallback();
       }
-      
-      /* SAI mutedet interrupt occurred --------------------------------------*/
-      if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+    }
+    /* SAI AFSDET interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
       {
-        /* Clear the SAI mutedet flag */
-        __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
-        /* call the call back function */
-        if(hsai->mutecallback != (SAIcallback)NULL)
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
         {
-          /* inform the user that an RX mute event has been detected */
-          hsai->mutecallback();
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
         }
       }
-      
-      /* SAI AFSDET interrupt occurred ---------------------------------------*/
-      if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+      else
       {
-        /* Change the SAI error code */
-        hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;
+        /* Abort SAI */ 
         HAL_SAI_Abort(hsai);
-        HAL_SAI_ErrorCallback(hsai);
-      }
-      
-      /* SAI LFSDET interrupt occurred ---------------------------------------*/
-      if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))
-      {
-        /* Change the SAI error code */
-        hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;
-        HAL_SAI_Abort(hsai);
-        HAL_SAI_ErrorCallback(hsai);
-      }
 
-      /* SAI WCKCFG interrupt occurred ---------------------------------------*/
-      if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+        /* Set error callback */
+        HAL_SAI_ErrorCallback(hsai);
+      }
+    }
+    /* SAI LFSDET interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
       {
-        /* Change the SAI error code */
-        hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* Abort SAI */
         HAL_SAI_Abort(hsai);
+
+        /* Set error callback */
         HAL_SAI_ErrorCallback(hsai);
       }
-      /* SAI CNRDY interrupt occurred ----------------------------------------*/
-      if(((tmpFlag & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((tmpItSource & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+    }
+    /* SAI WCKCFG interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+
+      /* Check SAI DMA is enabled or not */
+      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
       {
-        /* Clear the SAI CNRDY flag */
-        __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
-        /* Change the SAI error code */
-        hsai->ErrorCode = HAL_SAI_ERROR_CNREADY;
-        /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+        /* Abort the SAI DMA Streams */
+        if(hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if(hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* If WCKCFG occurs, SAI audio block is automatically disabled */
+        /* Disable all interrupts and clear all flags */
+        hsai->Instance->IMR = 0U;
+        hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+        /* Set the SAI state to ready to be able to start again the process */
+        hsai->State = HAL_SAI_STATE_READY;
+
+        /* Initialize XferCount */
+        hsai->XferCount = 0U;
+
+        /* SAI error Callback */
         HAL_SAI_ErrorCallback(hsai);
       }
     }
+    /* SAI CNRDY interrupt occurred ----------------------------------*/
+    else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+    {
+      /* Clear the SAI CNRDY flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+      HAL_SAI_ErrorCallback(hsai);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
   }
 }
 
 /**
-  * @brief Tx Transfer completed callbacks.
+  * @brief Tx Transfer completed callback.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
   *                the configuration information for SAI module.
   * @retval None
   */
- __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_TxCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief Tx Transfer Half completed callbacks
+  * @brief Tx Transfer Half completed callback.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
  __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief Rx Transfer completed callbacks.
+  * @brief Rx Transfer completed callback.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_RxCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief Rx Transfer half completed callbacks
+  * @brief Rx Transfer half completed callback.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SAI_RxCpltCallback could be implemented in the user file
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief SAI error callbacks.
+  * @brief SAI error callback.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval None
   */
 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsai);
-  
-  /* NOTE : This function Should not be modified, when the callback is needed,
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SAI_ErrorCallback could be implemented in the user file
    */
 }
@@ -1408,15 +1564,16 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
   * @}
   */
 
-/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions 
-  *  @brief   Peripheral State functions 
-  *
-@verbatim   
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+ *  @brief   Peripheral State functions
+ *
+@verbatim
  ===============================================================================
                 ##### Peripheral State and Errors functions #####
  ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -1424,9 +1581,9 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
   */
 
 /**
-  * @brief  Returns the SAI state.
+  * @brief  Return the SAI handle state.
   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
+  *               the configuration information for SAI module.
   * @retval HAL state
   */
 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
@@ -1435,11 +1592,11 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Return the SAI error code
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *              the configuration information for the specified SAI Block.
-  * @retval SAI Error Code
-  */
+* @brief  Return the SAI error code.
+* @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *             the configuration information for the specified SAI Block.
+* @retval SAI Error Code
+*/
 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
 {
   return hsai->ErrorCode;
@@ -1449,23 +1606,28 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
   */
 
 /**
-  * @brief  Initializes the SAI I2S protocol according to the specified parameters 
+  * @}
+  */
+
+/** @addtogroup SAI_Private_Functions
+ *  @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SAI I2S protocol according to the specified parameters
   *         in the SAI_InitTypeDef and create the associated handle.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol: one of the supported protocol.
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
   *                the configuration information for SAI module.
-  * @param  protocol : one of the supported protocol
-  * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
-  *                the configuration information for SAI module.
-  * @param  nbslot : number of slot minimum value is 2 and max is 16. 
+  * @param  nbslot: number of slot minimum value is 2 and max is 16.
   *                    the value must be a multiple of 2.
   * @retval HAL status
   */
 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
 {
-  /* Check the parameters */
-  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
-  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
-
   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
   /* Compute ClockStrobing according AudioMode */
@@ -1511,27 +1673,27 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
     hsai->FrameInit.FrameLength = 32U*(nbslot/2U);
     hsai->FrameInit.ActiveFrameLength = 16U*(nbslot/2U);
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
-    break; 
+    break;
   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
     hsai->Init.DataSize = SAI_DATASIZE_16;
     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
-    break; 
+    break;
   case SAI_PROTOCOL_DATASIZE_24BIT:
     hsai->Init.DataSize = SAI_DATASIZE_24;
     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
     break;
-  case SAI_PROTOCOL_DATASIZE_32BIT: 
+  case SAI_PROTOCOL_DATASIZE_32BIT:
     hsai->Init.DataSize = SAI_DATASIZE_32;
     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
     break;
   default :
-    return HAL_ERROR;  
+    return HAL_ERROR;
   }
   if(protocol == SAI_I2S_LSBJUSTIFIED)
   {
@@ -1548,21 +1710,17 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
 }
 
 /**
-  * @brief  Initializes the SAI PCM protocol according to the specified parameters 
+  * @brief  Initialize the SAI PCM protocol according to the specified parameters
   *         in the SAI_InitTypeDef and create the associated handle.
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @param  protocol : one of the supported protocol
-  * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
-  * @param  nbslot : number of slot minimum value is 1 and the max is 16.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol: one of the supported protocol
+  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+  * @param  nbslot: number of slot minimum value is 1 and the max is 16.
   * @retval HAL status
   */
 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
 {
-  /* Check the parameters */
-  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
-  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
-
   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
   /* Compute ClockStrobing according AudioMode */
@@ -1610,7 +1768,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol,
     hsai->FrameInit.FrameLength = 32U * nbslot;
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
     break;
-  case SAI_PROTOCOL_DATASIZE_32BIT: 
+  case SAI_PROTOCOL_DATASIZE_32BIT:
     hsai->Init.DataSize = SAI_DATASIZE_32;
     hsai->FrameInit.FrameLength = 32U * nbslot;
     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
@@ -1623,10 +1781,10 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol,
 }
 
 /**
-  * @brief  Fill the fifo 
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Fill the fifo.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
 {
@@ -1652,27 +1810,27 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  return the interrupt flag to set according the SAI setup 
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @param  mode : SAI_MODE_DMA or SAI_MODE_IT
+  * @brief  Return the interrupt flag to set according the SAI setup.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  mode: SAI_MODE_DMA or SAI_MODE_IT
   * @retval the list of the IT flag to enable
  */
 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
 {
-  uint32_t tmpIT = SAI_IT_OVRUDR; 
-  
+  uint32_t tmpIT = SAI_IT_OVRUDR;
+
   if(mode == SAI_MODE_IT)
   {
     tmpIT|= SAI_IT_FREQ;
   }
 
-  if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && 
+  if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
     ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
   {
     tmpIT|= SAI_IT_CNRDY;
   }
-  
+
   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
   {
     tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
@@ -1686,36 +1844,39 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
 }
 
 /**
-  * @brief  disable the SAI and wait the disabling
+  * @brief  Disable the SAI and wait for the disabling.
   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
 {
-  uint32_t tickstart = HAL_GetTick();
+  register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000);
   HAL_StatusTypeDef status = HAL_OK;
-  
+
+  /* Disable the SAI instance */
   __HAL_SAI_DISABLE(hsai);
-  while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
+
+  do
   {
     /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
+    if (count-- == 0)
     {         
       /* Update error code */
       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-      
-      return HAL_TIMEOUT;
+      status = HAL_TIMEOUT;
+      break;
     }
-  }
+  } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
+
   return status;
 }
 
 /**
-  * @brief  Tx Handler for Transmit in Interrupt mode 8Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
 {
@@ -1732,14 +1893,14 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
     /* Write data on DR register */
     hsai->Instance->DR = (*hsai->pBuffPtr++);
     hsai->XferCount--;
-  }  
+  }
 }
 
 /**
-  * @brief  Tx Handler for Transmit in Interrupt mode for 16Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
 {
@@ -1747,7 +1908,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
   {
     /* Handle the end of the transmission */
     /* Disable FREQ and OVRUDR interrupts */
-    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); 
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
     hsai->State = HAL_SAI_STATE_READY;
     HAL_SAI_TxCpltCallback(hsai);
   }
@@ -1757,14 +1918,14 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
     hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
     hsai->pBuffPtr+=2U;
     hsai->XferCount--;
-  }  
+  }
 }
 
 /**
-  * @brief  Tx Handler for Transmit in Interrupt mode for 32Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
 {
@@ -1772,7 +1933,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
   {
     /* Handle the end of the transmission */
     /* Disable FREQ and OVRUDR interrupts */
-    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); 
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
     hsai->State = HAL_SAI_STATE_READY;
     HAL_SAI_TxCpltCallback(hsai);
   }
@@ -1786,17 +1947,17 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Rx Handler for Receive in Interrupt mode 8Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
 {
   /* Receive data */
   (*hsai->pBuffPtr++) = hsai->Instance->DR;
   hsai->XferCount--;
-  
+
   /* Check end of the transfer */
   if(hsai->XferCount == 0U)
   {
@@ -1812,14 +1973,14 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Rx Handler for Receive in Interrupt mode for 16Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
 {
-  /* Receive data */    
+  /* Receive data */
   *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
   hsai->pBuffPtr+=2U;
   hsai->XferCount--;
@@ -1839,10 +2000,10 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
 }
 
 /**
-  * @brief  Rx Handler for Receive in Interrupt mode for 32Bit transfer
-  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
-  *                the configuration information for SAI module.
-  * @retval None.
+  * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
   */
 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
 {
@@ -1861,14 +2022,14 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
 
     hsai->State = HAL_SAI_STATE_READY;
-    HAL_SAI_RxCpltCallback(hsai); 
+    HAL_SAI_RxCpltCallback(hsai);
   }
 }
 
 /**
   * @brief DMA SAI transmit process complete callback.
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -1879,7 +2040,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
   {
     hsai->XferCount = 0U;
 
-    /* Disable SAI Tx DMA Request */  
+    /* Disable SAI Tx DMA Request */
     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
 
     /* Stop the interrupts error handling */
@@ -1891,9 +2052,9 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief DMA SAI transmit process half complete callback 
+  * @brief DMA SAI transmit process half complete callback.
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1906,7 +2067,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 /**
   * @brief DMA SAI receive process complete callback.
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -1923,13 +2084,13 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
 
     hsai->State = HAL_SAI_STATE_READY;
   }
-  HAL_SAI_RxCpltCallback(hsai); 
+  HAL_SAI_RxCpltCallback(hsai);
 }
 
 /**
   * @brief DMA SAI receive process half complete callback 
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1940,23 +2101,69 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief DMA SAI communication error callback. 
+  * @brief DMA SAI communication error callback.
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
 {
   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
-  /* Stop the DMA transfer */
-  HAL_SAI_DMAStop(hsai);
+  /* Set SAI error code */
+  hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
 
-  /* Set the SAI state ready to be able to start again the process */
-  hsai->State= HAL_SAI_STATE_READY;
+  if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))
+  {
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+    /* Disable SAI peripheral */
+    SAI_Disable(hsai);
+    
+    /* Set the SAI state ready to be able to start again the process */
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Initialize XferCount */
+    hsai->XferCount = 0U;
+  }
+  /* SAI error Callback */ 
   HAL_SAI_ErrorCallback(hsai);
+}
 
-  hsai->XferCount = 0U;
+/**
+  * @brief DMA SAI Abort callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)   
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Disable DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable all interrupts and clear all flags */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+  {
+    /* Disable SAI peripheral */
+    SAI_Disable(hsai);
+
+    /* Flush the fifo */
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  }
+  /* Set the SAI state to ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+  
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;  
+
+  /* SAI error Callback */ 
+  HAL_SAI_ErrorCallback(hsai);
 }
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h
index fff9016659..4d7c47396e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sai.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SAI HAL module.
   ******************************************************************************
   * @attention
@@ -33,7 +33,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_SAI_H
@@ -55,13 +55,13 @@
 /** @addtogroup SAI
   * @{
   */
-  
+
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup SAI_Exported_Types SAI Exported Types
   * @{
   */
- 
-/** 
+
+/**
   * @brief  HAL State structures definition
   */
 typedef enum
@@ -75,63 +75,66 @@ typedef enum
   HAL_SAI_STATE_ERROR      = 0x04U   /*!< SAI error state                                    */
 }HAL_SAI_StateTypeDef;
 
-/** 
-  * @brief  SAI Callback prototype 
+/**
+  * @brief  SAI Callback prototype
   */
 typedef void (*SAIcallback)(void);
 
-/** 
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
   * @brief  SAI Init Structure definition
+  * @{
   */
 typedef struct
 {
-  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode. 
+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
                                      This parameter can be a value of @ref SAI_Block_Mode                      */
 
   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
                                      This parameter can be a value of @ref SAI_Block_Synchronization           */
  
-  uint32_t SynchroExt;          /*!< Specifies SAI Block synchronization, this setup is common 
-                                     for BLOCKA and BLOCKB
-                                     This parameter can be a value of @ref SAI_Block_SyncExt                   */
+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
+                                     for BlockA and BlockB
+                                     This parameter can be a value of @ref SAI_Block_SyncExt
+                                     @note: If both audio blocks of same SAI are used, this parameter has
+                                            to be set to the same value for each audio block                   */
 
   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
                                      This parameter can be a value of @ref SAI_Block_Output_Drive
-                                     @note this value has to be set before enabling the audio block  
+                                     @note this value has to be set before enabling the audio block
                                      but after the audio block configuration.                                  */
 
   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
                                      This parameter can be a value of @ref SAI_Block_NoDivider
-                                     @note  If bit NODIV in the SAI_xCR1 register is cleared, the frame length 
+                                     @note  If bit NODIV in the SAI_xCR1 register is cleared, the frame length
                                             should be aligned to a number equal to a power of 2, from 8 to 256.
-                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can 
-                                            take any of the values without constraint since the input clock of 
+                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can
+                                            take any of the values without constraint since the input clock of
                                             the audio block should be equal to the bit clock.
                                              There is no MCLK_x clock which can be output.                     */
   
   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold            */
 
-  uint32_t ClockSource;         /*!< Specifies the SAI Block x Clock source.    
+  uint32_t ClockSource;         /*!< Specifies the SAI Block x Clock source.
                                      This parameter is not used for STM32F446xx devices.                       */
 
-  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.     
+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
                                      This parameter can be a value of @ref SAI_Audio_Frequency                 */
 
   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for 
-                                     AudioFrequency the user choice 
+                                     AudioFrequency the user choice
                                      This parameter must be a number between Min_Data = 0 and Max_Data = 15    */
 
-  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.     
+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode                */
 
-  uint32_t CompandingMode;      /*!< Specifies the companding mode type.     
+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.
                                      This parameter can be a value of @ref SAI_Block_Companding_Mode           */
 
-  uint32_t TriState;            /*!< Specifies the companding mode type.     
+  uint32_t TriState;            /*!< Specifies the companding mode type.
                                      This parameter can be a value of @ref SAI_TRIState_Management             */
 
-  /* This part of the structure is automatically filled if your are using the high level intialisation 
+  /* This part of the structure is automatically filled if your are using the high level intialisation
      function HAL_SAI_InitProtocol                                                                             */
 
   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
@@ -146,11 +149,14 @@ typedef struct
   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing                */
 }SAI_InitTypeDef;
-
-/** 
-  * @brief  SAI Block Frame Init structure definition
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+  * @brief  SAI Frame Init structure definition
+  * @{
   */
- 
 typedef struct
 {
   uint32_t FrameLength;         /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
@@ -160,7 +166,7 @@ typedef struct
                                             in an audio frame, an integer number of MCLK pulses by bit Clock. */
 
   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
-                                    This Parameter specifies the length in number of bit clock (SCK + 1)  
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)
                                     of the active level of FS signal in audio frame.
                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
 
@@ -173,11 +179,14 @@ typedef struct
   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
                                     This parameter can be a value of @ref SAI_Block_FS_Offset                 */
 }SAI_FrameInitTypeDef;
-
 /**
-  * @brief   SAI Block Slot Init Structure definition
-  */    
+  * @}
+  */
 
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+  * @brief   SAI Block Slot Init Structure definition
+  * @{
+  */
 typedef struct
 {
   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
@@ -193,8 +202,13 @@ typedef struct
                                  This parameter can be a value of @ref SAI_Block_Slot_Active            */
 }SAI_SlotInitTypeDef;
 
-/** 
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
   * @brief  SAI handle Structure definition
+  * @{
   */
 typedef struct __SAI_HandleTypeDef
 {
@@ -226,7 +240,6 @@ typedef struct __SAI_HandleTypeDef
 
   __IO uint32_t             ErrorCode;   /*!< SAI Error code                          */
 }SAI_HandleTypeDef;
-
 /**
   * @}
   */
@@ -248,6 +261,7 @@ typedef struct __SAI_HandleTypeDef
 #define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready                             */
 #define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration                   */
 #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error                               */
+#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error                                   */
 /**
   * @}
   */
@@ -255,9 +269,9 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
   * @{
   */
-#define SAI_SYNCEXT_DISABLE           ((uint32_t)0x00000000U)
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE  ((uint32_t)0x00000001U)
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE  ((uint32_t)0x00000002U)
+#define SAI_SYNCEXT_DISABLE          0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
 /**
   * @}
   */
@@ -265,11 +279,11 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Protocol SAI Supported protocol
   * @{
   */
-#define SAI_I2S_STANDARD      ((uint32_t)0x00000000U)
-#define SAI_I2S_MSBJUSTIFIED  ((uint32_t)0x00000001U)
-#define SAI_I2S_LSBJUSTIFIED  ((uint32_t)0x00000002U)
-#define SAI_PCM_LONG          ((uint32_t)0x00000004U)
-#define SAI_PCM_SHORT         ((uint32_t)0x00000008U)
+#define SAI_I2S_STANDARD      0U
+#define SAI_I2S_MSBJUSTIFIED  1U
+#define SAI_I2S_LSBJUSTIFIED  2U
+#define SAI_PCM_LONG          3U
+#define SAI_PCM_SHORT         4U
 /**
   * @}
   */
@@ -277,10 +291,10 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
   * @{
   */
-#define SAI_PROTOCOL_DATASIZE_16BIT          ((uint32_t)0x00000000U)
-#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED  ((uint32_t)0x00000001U)
-#define SAI_PROTOCOL_DATASIZE_24BIT          ((uint32_t)0x00000002U)
-#define SAI_PROTOCOL_DATASIZE_32BIT          ((uint32_t)0x00000004U)
+#define SAI_PROTOCOL_DATASIZE_16BIT         0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT         2U
+#define SAI_PROTOCOL_DATASIZE_32BIT         3U
 /**
   * @}
   */
@@ -347,7 +361,7 @@ typedef struct __SAI_HandleTypeDef
   * @}
   */
 
-/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission 
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
   * @{
   */
 #define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
@@ -359,8 +373,8 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
   * @{
   */
-#define SAI_CLOCKSTROBING_FALLINGEDGE     ((uint32_t)0x00000000U)
-#define SAI_CLOCKSTROBING_RISINGEDGE      ((uint32_t)0x00000001U)
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0U
+#define SAI_CLOCKSTROBING_RISINGEDGE      1U
 /**
   * @}
   */
@@ -368,10 +382,10 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
   * @{
   */
-#define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000U) /*!< Asynchronous */
-#define SAI_SYNCHRONOUS                   ((uint32_t)0x00000001U) /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1          ((uint32_t)0x00000002U) /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2          ((uint32_t)0x00000003U) /*!< Synchronous with other SAI, SAI2 */
+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous                             */
+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1         */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2         */
 /**
   * @}
   */
@@ -407,7 +421,7 @@ typedef struct __SAI_HandleTypeDef
   * @{
   */
 #define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
-#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPO)
+#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
 /**
   * @}
   */
@@ -474,14 +488,14 @@ typedef struct __SAI_HandleTypeDef
   * @}
   */
 
-/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold 
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
   * @{
   */
 #define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
-#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)SAI_xCR2_FTH_0)
-#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)SAI_xCR2_FTH_1) 
+#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
 #define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)SAI_xCR2_FTH_2)
+#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
 /**
   * @}
   */
@@ -489,11 +503,11 @@ typedef struct __SAI_HandleTypeDef
 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
   * @{
   */
-#define SAI_NOCOMPANDING                  ((uint32_t)0x00000000U)
-#define SAI_ULAW_1CPL_COMPANDING          ((uint32_t)SAI_xCR2_COMP_1)
-#define SAI_ALAW_1CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
-#define SAI_ULAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
-#define SAI_ALAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
+#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
+#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
 /**
   * @}
   */
@@ -558,10 +572,10 @@ typedef struct __SAI_HandleTypeDef
  *  @brief macros to handle interrupts and specific configurations
  * @{
  */
- 
+
 /** @brief Reset SAI handle state
   * @param  __HANDLE__: specifies the SAI Handle.
-  * @retval None
+  * @retval NoneS
   */
 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
 
@@ -575,7 +589,7 @@ typedef struct __SAI_HandleTypeDef
   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
-  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
   * @retval None
   */
 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
@@ -586,9 +600,13 @@ typedef struct __SAI_HandleTypeDef
   *         This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
   * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
   *         This parameter can be one of the following values:
-  *            @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
-  *            @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
-  *            @arg SAI_IT_ERR: Error interrupt enable.
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
   */
 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@@ -608,7 +626,7 @@ typedef struct __SAI_HandleTypeDef
   */
 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clears the specified SAI pending flag.
+/** @brief  Clear the specified SAI pending flag.
   * @param  __HANDLE__: specifies the SAI Handle.
   * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
@@ -710,33 +728,6 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 /**
   * @}
   */
-  
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SAI_Private_Types SAI Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Variables SAI Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Constants SAI Private Constants
-  * @{
-  */
 
 /**
   * @}
@@ -793,8 +784,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
 
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS)  || \
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
 
@@ -802,14 +793,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
 
 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
-                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) 
-
-#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \
-                                          ((STATUS) == SAI_FIFOSTATUS_HALFFULL)          || \
-                                          ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL)      || \
-                                          ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL)     || \
-                                          ((STATUS) == SAI_FIFOSTATUS_FULL)              || \
-                                          ((STATUS) == SAI_FIFOSTATUS_EMPTY))
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
 
 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
 
@@ -836,7 +820,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 
 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
 
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))  
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
 
 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
@@ -853,12 +837,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
 
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)    
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
 
 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
 
 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
 
+
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c
index 4ca7569b21..9e6b859dca 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sai_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SAI Extension HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of SAI extension peripheral:
@@ -120,25 +120,24 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
   /* This setting must be done with both audio block (A & B) disabled         */
   switch(hsai->Init.SynchroExt)
   {
-    case SAI_SYNCEXT_DISABLE :
-      tmpregisterGCR = 0U;
-      break;
-    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
-      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
-      break;
-    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
-      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
-      break;
-  default:
+  case SAI_SYNCEXT_DISABLE :
     tmpregisterGCR = 0U;
     break;
+  case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+    tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+    break;
+  case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+    tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+    break;
+  default:
+    break;
   }
 
   if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
   {
-        tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+    tmpregisterGCR |= SAI_GCR_SYNCIN_0;
   }
-  
+
   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
   {
     SAI1->GCR = tmpregisterGCR;
@@ -149,7 +148,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
   }
 #endif /* STM32F446xx */
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+  defined(STM32F469xx) || defined(STM32F479xx)
   /* This setting must be done with both audio block (A & B) disabled         */
   switch(hsai->Init.SynchroExt)
   {
@@ -163,7 +162,6 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
     tmpregisterGCR = SAI_GCR_SYNCOUT_1;
     break;
   default:
-    tmpregisterGCR = 0U;
     break;
   }
   SAI1->GCR = tmpregisterGCR;
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h
index d1f2f8010c..8205d1f5ce 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sai_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SAI Extension HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c
index a68328fee0..001fe6878e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sd.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SD card HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Secure Digital (SD) peripheral:
@@ -183,7 +183,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /** @addtogroup STM32F4xx_HAL_Driver
   * @{
   */
@@ -3494,7 +3495,8 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
+          STM32F412Rx || STM32F412Cx */
 #endif /* HAL_SD_MODULE_ENABLED */
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h
index bb865e2834..56a717a1d6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sd.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_ll_sdmmc.h"
 
@@ -783,7 +784,8 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
   * @}
   */ 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c
index 73d1d5fb6d..df99360b75 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sdram.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SDRAM HAL module driver.
   *          This file provides a generic firmware to drive SDRAM memories mounted 
   *          as external device.
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h
index 20f73703fd..2b913e6bba 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sdram.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SDRAM HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c
index d155ce2374..0e8b7076c5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SMARTCARD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the SMARTCARD peripheral:
@@ -153,6 +153,8 @@
 /** @addtogroup SMARTCARD_Private_Functions
   * @{
   */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
 static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -160,7 +162,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
 /**
   * @}
   */
@@ -268,14 +271,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
   /* In SmartCard mode, the following bits must be kept cleared: 
   - LINEN bit in the USART_CR2 register
   - HDSEL and IREN bits in the USART_CR3 register.*/
-  hsc->Instance->CR2 &= ~USART_CR2_LINEN;
-  hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
+  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
 
   /* Enable the SMARTCARD Parity Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+  SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
 
   /* Enable the SMARTCARD Framing Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+  SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
   /* Enable the Peripheral */
   __HAL_SMARTCARD_ENABLE(hsc);
@@ -425,6 +428,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
   
   if(hsc->gState == HAL_SMARTCARD_STATE_READY) 
   {
@@ -439,12 +443,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
        
+    /* Init tickstart for timeout managment */ 
+    tickstart = HAL_GetTick();
+    
     hsc->TxXferSize = Size;
     hsc->TxXferCount = Size;
     while(hsc->TxXferCount > 0U)
     {
       hsc->TxXferCount--;
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -453,7 +460,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
       pData +=1U;
     }
     
-    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -484,6 +491,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
   
   if(hsc->RxState == HAL_SMARTCARD_STATE_READY) 
   {
@@ -498,6 +506,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
     
+    /* Init tickstart for timeout managment */ 
+    tickstart = HAL_GetTick();
+  
     hsc->RxXferSize = Size;
     hsc->RxXferCount = Size;
 
@@ -505,16 +516,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
     while(hsc->RxXferCount > 0U)
     {
       hsc->RxXferCount--;
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
       tmp = (uint16_t*) pData;
-      *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FFU);
+      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
       pData +=1U;
     }
 
-	/* At end of Rx process, restore hsc->RxState to Ready */
+    /* At end of Rx process, restore hsc->RxState to Ready */
     hsc->RxState = HAL_SMARTCARD_STATE_READY;
     
     /* Process Unlocked */
@@ -560,13 +571,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
     __HAL_UNLOCK(hsc);
     
     /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
 
     /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the SMARTCARD Transmit data register empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
+    SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
@@ -608,13 +619,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
     __HAL_UNLOCK(hsc);
     
     /* Enable the SMARTCARD Data Register not empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); 
+    SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
 
     /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
 
     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
     return HAL_OK;
   }
@@ -659,6 +670,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
 
     /* Set the DMA error callback */
     hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+    
+    /* Set the DMA abort callback */
+    hsc->hdmatx->XferAbortCallback = NULL;
 
     /* Enable the SMARTCARD transmit DMA Stream */
     tmp = (uint32_t*)&pData;
@@ -666,13 +680,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
 
      /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the SMARTCARD CR3 register */
-    hsc->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
+    
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the SMARTCARD CR3 register */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
 
     return HAL_OK;
   }
@@ -717,17 +731,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
 
     /* Set the DMA error callback */
     hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+    
+    /* Set the DMA abort callback */
+    hsc->hdmatx->XferAbortCallback = NULL;
 
     /* Enable the DMA Stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
 
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-    in the SMARTCARD CR3 register */
-    hsc->Instance->CR3 |= USART_CR3_DMAR;
-
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
+    
+    /* Enable the SMARTCARD Parity Error Interrupt */
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+    
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+    in the SMARTCARD CR3 register */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
 
     return HAL_OK;
   }
@@ -745,70 +768,120 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
   */
 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
 {
-  uint32_t tmp1 = 0U, tmp2 = 0U; 
-  
-  tmp1 = hsc->Instance->SR;  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
+  uint32_t isrflags   = READ_REG(hsc->Instance->SR);
+  uint32_t cr1its     = READ_REG(hsc->Instance->CR1);
+  uint32_t cr3its     = READ_REG(hsc->Instance->CR3);
+  uint32_t dmarequest = 0x00U;
+  uint32_t errorflags = 0x00U;
 
-  /* SMARTCARD parity error interrupt occurred --------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD frame error interrupt occurred ---------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD noise error interrupt occurred ---------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if(errorflags == RESET)
+  {
+    /* SMARTCARD in mode Receiver -------------------------------------------------*/
+    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      SMARTCARD_Receive_IT(hsc);
+      return;
+    }
   }
 
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
-  /* SMARTCARD in mode Receiver ----------------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
-  { 
-    SMARTCARD_Receive_IT(hsc);
-  }
+  /* If some errors occur */
+  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+  {
+    /* SMARTCARD parity error interrupt occurred ---------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    { 
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
 
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
+    /* SMARTCARD frame error interrupt occurred ----------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    { 
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred ----------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    { 
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    { 
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+    /* Call the Error call Back in case of Errors */
+    if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver -----------------------------------------------*/
+      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        SMARTCARD_Receive_IT(hsc);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+      if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+          Set the SMARTCARD state ready to be able to start again the process,
+          Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsc);
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if(hsc->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+              will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+           if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsc);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsc);
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsc);
+        hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+  
   /* SMARTCARD in mode Transmitter -------------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_TXE) != RESET) && (tmp2 != RESET))
+  if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     SMARTCARD_Transmit_IT(hsc);
-  }
-
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
-  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
-  {
-    SMARTCARD_EndTransmit_IT(hsc);
+    return;
   }
   
-  /* Call the Error call Back in case of Errors */
-  if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+  if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
-    /* Set the SMARTCARD state ready to be able to start again the process */
-    hsc->gState= HAL_SMARTCARD_STATE_READY;
-    hsc->RxState= HAL_SMARTCARD_STATE_READY;
-    HAL_SMARTCARD_ErrorCallback(hsc);
+    SMARTCARD_EndTransmit_IT(hsc);
+    return;
   }
 }
 
@@ -854,7 +927,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
   UNUSED(hsc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -920,10 +993,10 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
   
   /* Disable the DMA transfer for transmit request by setting the DMAT bit
   in the USART CR3 register */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
 
-  /* Enable the SMARTCARD Transmit Complete Interrupt */    
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+  /* Enable the SMARTCARD Transmit Complete Interrupt */   
+  SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
 }
 
 /**
@@ -938,9 +1011,13 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 
   hsc->RxXferCount = 0U;
   
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+  
   /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
   in the USART CR3 register */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
   
   /* At end of Rx process, restore hsc->RxState to Ready */
   hsc->RxState = HAL_SMARTCARD_STATE_READY;
@@ -956,13 +1033,25 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   */
 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)   
 {
+  uint32_t dmarequest = 0x00U;
   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
   hsc->RxXferCount = 0U;
   hsc->TxXferCount = 0U;
   hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-  hsc->gState= HAL_SMARTCARD_STATE_READY;
-  hsc->RxState= HAL_SMARTCARD_STATE_READY;
+  
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
+  if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
+  {
+    SMARTCARD_EndTxTransfer(hsc);
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+  if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
+  {
+    SMARTCARD_EndRxTransfer(hsc);
+  }
 
   HAL_SMARTCARD_ErrorCallback(hsc);
 }
@@ -973,67 +1062,66 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
   * @param  Flag: specifies the SMARTCARD flag to check.
   * @param  Status: The new Flag status (SET or RESET).
   * @param  Timeout: Timeout duration
+  * @param  Tickstart: tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {    
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-          
-          hsc->gState= HAL_SMARTCARD_STATE_READY;
-		  hsc->RxState= HAL_SMARTCARD_STATE_READY;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
+  /* Wait until flag is set */   
+  while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-          
-          hsc->gState= HAL_SMARTCARD_STATE_READY;
-		  hsc->RxState= HAL_SMARTCARD_STATE_READY;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-          
-          return HAL_TIMEOUT;
-        }
+        /* Disable TXE and RXNE interrupts for the interrupt process */
+        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+        
+        hsc->gState= HAL_SMARTCARD_STATE_READY;
+        hsc->RxState= HAL_SMARTCARD_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsc);
+        
+        return HAL_TIMEOUT;
       }
     }
   }
   return HAL_OK;
 }
 
+/**
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsc: SMARTCARD handle.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* At end of Tx process, restore hsc->gState to Ready */
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
+  * @param  hsc: SMARTCARD handle.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* At end of Rx process, restore hsc->RxState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+}
+
 /**
   * @brief Send an amount of data in non blocking mode 
   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
@@ -1054,10 +1142,10 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
     if(--hsc->TxXferCount == 0U)
     {
       /* Disable the SMARTCARD Transmit data register empty Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
       
       /* Enable the SMARTCARD Transmit Complete Interrupt */
-      __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+      SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
     }
     
     return HAL_OK;
@@ -1076,11 +1164,11 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
   */
 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
 {
-  /* Disable the SMARTCARD Transmit Complete Interrupt */    
-  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+  /* Disable the SMARTCARD Transmit Complete Interrupt */   
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
   
   /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
     
   /* Tx process is ended, restore hsmartcard->gState to Ready */
   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1104,18 +1192,18 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
   if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) 
   {
     tmp = (uint16_t*) hsc->pRxBuffPtr;
-    *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FFU);
+    *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FFU);
     hsc->pRxBuffPtr += 1U;
     
     if(--hsc->RxXferCount == 0U)
     {
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
       
       /* Disable the SMARTCARD Parity Error Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
       
       /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+      CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
       
 	  /* Rx process is completed, restore hsc->RxState to Ready */
       hsc->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1132,6 +1220,21 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
   }
 }
 
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hsc->RxXferCount = 0x00U;
+  hsc->TxXferCount = 0x00U;
+
+  HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
 /**
   * @brief Configure the SMARTCARD peripheral 
   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
@@ -1156,7 +1259,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
 
   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  hsc->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
   
   /*---------------------------- USART CR2 Configuration ---------------------*/
   tmpreg = hsc->Instance->CR2;
@@ -1170,7 +1273,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
   tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | 
                       hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
   /* Write to USART CR2 */
-  hsc->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
   
   tmpreg = hsc->Instance->CR2;
 
@@ -1181,7 +1284,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
   tmpreg |= (uint32_t)(hsc->Init.StopBits);
   
   /* Write to USART CR2 */
-  hsc->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = hsc->Instance->CR1;
@@ -1197,11 +1300,11 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
   tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
 
   /* Write to USART CR1 */
-  hsc->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);  
 
   /*-------------------------- USART CR3 Configuration -----------------------*/  
   /* Clear CTSE and RTSE bits */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
 
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((hsc->Instance == USART1) || (hsc->Instance == USART6))
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h
index d22ad6a1c6..835b3839d6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
@@ -439,7 +439,7 @@ typedef struct
 /** @brief  Clear the SMARTCARD PE pending flag.
   * @param  __HANDLE__: specifies the USART Handle.
   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  *         SMARTCARD peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)     \
@@ -453,7 +453,7 @@ typedef struct
 /** @brief  Clear the SMARTCARD FE pending flag.
   * @param  __HANDLE__: specifies the USART Handle.
   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  *         SMARTCARD peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
@@ -461,7 +461,7 @@ typedef struct
 /** @brief  Clear the SMARTCARD NE pending flag.
   * @param  __HANDLE__: specifies the USART Handle.
   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  *         SMARTCARD peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
@@ -469,7 +469,7 @@ typedef struct
 /** @brief  Clear the SMARTCARD ORE pending flag.
   * @param  __HANDLE__: specifies the USART Handle.
   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  *         SMARTCARD peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
@@ -477,7 +477,7 @@ typedef struct
 /** @brief  Clear the SMARTCARD IDLE pending flag.
   * @param  __HANDLE__: specifies the USART Handle.
   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  *         SMARTCARD peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
@@ -580,6 +580,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+
 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
@@ -618,8 +619,8 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
 #define SMARTCARD_DIV(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
 #define SMARTCARD_DIVMANT(_PCLK_, _BAUD_)        (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
 #define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_)        (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+/* SMARTCARD BRR = mantissa + overflow + fraction
+            = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
 #define SMARTCARD_BRR(_PCLK_, _BAUD_)            (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c
index d56b5fed2b..a8a732a7e0 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c
@@ -2,24 +2,24 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_spdifrx.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
-  * @brief   This file provides firmware functions to manage the following 
+  * @version V1.5.0
+  * @date    06-May-2016
+  * @brief   This file provides firmware functions to manage the following
   *          functionalities of the SPDIFRX audio interface:
   *           + Initialization and Configuration
   *           + Data transfers functions
   *           + DMA transfers management
-  *           + Interrupts and flags management 
+  *           + Interrupts and flags management
   @verbatim
  ===============================================================================
-                  ##### How to use this driver #####
+                      ##### How to use this driver #####
  ===============================================================================
  [..]
     The SPDIFRX HAL driver can be used as follow:
-    
+
     (#) Declare SPDIFRX_HandleTypeDef handle structure.
     (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
-        (##) Enable the SPDIFRX interface clock.                      
+        (##) Enable the SPDIFRX interface clock.
         (##) SPDIFRX pins configuration:
             (+++) Enable the clock for the SPDIFRX GPIOs.
             (+++) Configure these SPDIFRX pins as alternate function pull-up.
@@ -28,51 +28,51 @@
             (+++) Enable the NVIC SPDIFRX IRQ handle.
         (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
-                      (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
             (+++) Configure the DMA Channel.
             (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
-                DMA CtrlRx/DataRx channel.
-  
+                  DMA CtrlRx/DataRx channel.
+
    (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
        using HAL_SPDIFRX_Init() function.
 
    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
-   -@- Make sure that ck_spdif clock is configured. 
-   
+   -@- Make sure that ck_spdif clock is configured.
+
    (#) Three operation modes are available within this driver :
-  
+
    *** Polling mode for reception operation (for debug purpose) ***
    ================================================================
-   [..]    
+   [..]
      (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
          (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
-   
+
    *** Interrupt mode for reception operation ***
    =========================================
    [..]    
      (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() 
-         (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() 
+     (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() 
      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can 
          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can 
+     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
-     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can 
+     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
 
    *** DMA mode for reception operation ***
    ========================================
-   [..] 
+   [..]
      (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() 
-         (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() 
-     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can 
+     (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
+     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
-     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can 
+     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
      (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
 
@@ -81,13 +81,13 @@
    [..]
      Below the list of most used macros in SPDIFRX HAL driver.
       (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
-      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) 
+      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
       (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
       (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
 
-    [..]
+   [..]
       (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
 
   @endverbatim
@@ -119,7 +119,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -143,6 +143,7 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
+
 /** @addtogroup SPDIFRX_Private_Functions
   * @{
   */
@@ -154,6 +155,7 @@ static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
 static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
 /**
   * @}
   */
@@ -163,37 +165,37 @@ static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
   * @{
   */
 
-/** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ===============================================================================
-  ##### Initialization and de-initialization functions #####
+           ##### Initialization and de-initialization functions #####
   ===============================================================================
-  [..]  This subsection provides a set of functions allowing to initialize and 
-  de-initialize the SPDIFRX peripheral:
-  
-  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures 
-  all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-  
-  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with 
-  the selected configuration:
-  (++) Input Selection (IN0, IN1,...)
-  (++) Maximum allowed re-tries during synchronization phase
-  (++) Wait for activity on SPDIF selected input
-  (++) Channel status selection (from channel A or B)
-  (++) Data format (LSB, MSB, ...)
-  (++) Stereo mode
-  (++) User bits masking (PT,C,U,V,...)
-  
-  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration 
-  of the selected SPDIFRXx peripheral. 
+  [..] This subsection provides a set of functions allowing to initialize and
+       de-initialize the SPDIFRX peripheral:
+
+     (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+         all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+     (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+         the selected configuration:
+         (++) Input Selection (IN0, IN1,...)
+         (++) Maximum allowed re-tries during synchronization phase
+         (++) Wait for activity on SPDIF selected input
+         (++) Channel status selection (from channel A or B)
+         (++) Data format (LSB, MSB, ...)
+         (++) Stereo mode
+         (++) User bits masking (PT,C,U,V,...)
+
+     (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+         of the selected SPDIFRXx peripheral.
   @endverbatim
   * @{
   */
 
 /**
-  * @brief Initializes the SPDIFRX according to the specified parameters 
+  * @brief Initializes the SPDIFRX according to the specified parameters
   *        in the SPDIFRX_InitTypeDef and create the associated handle.
   * @param hspdif: SPDIFRX handle
   * @retval HAL status
@@ -201,13 +203,13 @@ static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
 {
   uint32_t tmpreg = 0U;
-  
+
   /* Check the SPDIFRX handle allocation */
   if(hspdif == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the SPDIFRX parameters */
   assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
   assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
@@ -219,7 +221,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
   assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
   assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
   assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
-  
+
   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
@@ -227,21 +229,21 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
     HAL_SPDIFRX_MspInit(hspdif);
   }
-  
+
      /* SPDIFRX peripheral state is BUSY*/
-   hspdif->State = HAL_SPDIFRX_STATE_BUSY;  
-  
+   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
   /* Disable SPDIFRX interface (IDLE State) */
   __HAL_SPDIFRX_IDLE(hspdif);
-  
+
   /* Reset the old SPDIFRX CR configuration */
   tmpreg = hspdif->Instance->CR;
-  
+
   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
                          SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
                          SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
-                         SPDIFRX_CR_INSEL); 
-                  
+                         SPDIFRX_CR_INSEL);
+
   /* Sets the new configuration of the SPDIFRX peripheral */
   tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
                         hspdif->Init.InputSelection |
@@ -254,18 +256,18 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
                         hspdif->Init.ValidityBitMask |
                         hspdif->Init.ParityErrorMask);
 
-  hspdif->Instance->CR = tmpreg;  
-  
+  hspdif->Instance->CR = tmpreg;
+
   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-    
+
     /* SPDIFRX peripheral state is READY*/
   hspdif->State = HAL_SPDIFRX_STATE_READY;
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief DeInitializes the SPDIFRX peripheral 
+  * @brief DeInitializes the SPDIFRX peripheral
   * @param hspdif: SPDIFRX handle
   * @retval HAL status
   */
@@ -276,23 +278,23 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
 
   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-  
+
   /* Disable SPDIFRX interface (IDLE state) */
   __HAL_SPDIFRX_IDLE(hspdif);
 
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
   HAL_SPDIFRX_MspDeInit(hspdif);
-  
+
   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-    
-    /* SPDIFRX peripheral state is RESET*/
+
+  /* SPDIFRX peripheral state is RESET*/
   hspdif->State = HAL_SPDIFRX_STATE_RESET;
-  
+
   /* Release Lock */
   __HAL_UNLOCK(hspdif);
 
@@ -309,8 +311,8 @@ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_MspInit could be implemented in the user file
-  */ 
+            the HAL_SPDIFRX_MspInit could be implemented in the user file
+  */
 }
 
 /**
@@ -323,12 +325,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_MspDeInit could be implemented in the user file
-  */ 
+            the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+  */
 }
 
 /**
-  * @brief Sets the SPDIFRX  dtat format according to the specified parameters 
+  * @brief Sets the SPDIFRX  dtat format according to the specified parameters
   *        in the SPDIFRX_InitTypeDef.
   * @param hspdif: SPDIFRX handle
   * @param sDataFormat: SPDIFRX data format
@@ -337,13 +339,13 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat)
 {
   uint32_t tmpreg = 0U;
-  
+
   /* Check the SPDIFRX handle allocation */
   if(hspdif == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the SPDIFRX parameters */
   assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
   assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
@@ -351,20 +353,20 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
   assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
   assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
-  
+
   /* Reset the old SPDIFRX CR configuration */
   tmpreg = hspdif->Instance->CR;
-  
+
   if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
     (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
-    ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))  
+    ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
   {
-      return HAL_ERROR;    
-  }  
-  
+      return HAL_ERROR;
+  }
+
   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
-                         SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);   
-  
+                         SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+
   /* Sets the new configuration of the SPDIFRX peripheral */
   tmpreg |= ((uint16_t) sDataFormat.StereoMode |
                         sDataFormat.DataFormat |
@@ -373,8 +375,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
                         sDataFormat.ValidityBitMask |
                         sDataFormat.ParityErrorMask);
 
-  hspdif->Instance->CR = tmpreg;  
-  
+  hspdif->Instance->CR = tmpreg;
+
   return HAL_OK;
 }
 
@@ -382,25 +384,25 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   * @}
   */
 
-/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions 
-  *  @brief Data transfers functions 
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
+  *  @brief Data transfers functions
   *
-@verbatim   
+@verbatim
+===============================================================================
+                      ##### IO operation functions #####
 ===============================================================================
-##### IO operation functions #####
-===============================================================================  
     [..]
-    This subsection provides a set of functions allowing to manage the SPDIFRX data 
+    This subsection provides a set of functions allowing to manage the SPDIFRX data
     transfers.
 
     (#) There is two mode of transfer:
-        (++) Blocking mode : The communication is performed in the polling mode. 
-             The status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode : The communication is performed using Interrupts 
+        (++) Blocking mode : The communication is performed in the polling mode.
+             The status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) No-Blocking mode : The communication is performed using Interrupts
              or DMA. These functions return the status of the transfer start-up.
-             The end of the data processing will be indicated through the 
-             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when 
+             The end of the data processing will be indicated through the
+             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
              using DMA mode.
 
     (#) Blocking mode functions are :
@@ -425,7 +427,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   */
 
 /**
-  * @brief  Receives an amount of data (Data Flow) in blocking mode. 
+  * @brief  Receives an amount of data (Data Flow) in blocking mode.
   * @param  hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
   *                 the configuration information for SPDIFRX module.
   * @param  pData: Pointer to data buffer
@@ -435,50 +437,49 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
 {
- 
-  if((pData == NULL ) || (Size == 0U)) 
+  if((pData == NULL ) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
-  
+
   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
-  { 
+  {
     /* Process Locked */
     __HAL_LOCK(hspdif);
-    
-     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
 
-        /* Start synchronisation */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-            /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-    
-            /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
-            
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+    /* Start synchronisation */
+    __HAL_SPDIFRX_SYNC(hspdif);
+
+    /* Wait until SYNCD flag is set */
+    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Start reception */
+    __HAL_SPDIFRX_RCV(hspdif);
+
     /* Receive data flow */
     while(Size > 0U)
-    {      
+    {
       /* Wait until RXNE flag is set */
       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      { 
+      {
         return HAL_TIMEOUT;
-      }  
-      
+      }
+
       (*pData++) = hspdif->Instance->DR;
-      Size--; 
-    }      
+      Size--;
+    }
 
     /* SPDIFRX ready */
     hspdif->State = HAL_SPDIFRX_STATE_READY;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hspdif);
-    
+
     return HAL_OK;
   }
   else
@@ -488,7 +489,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
 }
 
 /**
-  * @brief  Receives an amount of data (Control Flow) in blocking mode. 
+  * @brief  Receives an amount of data (Control Flow) in blocking mode.
   * @param  hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
   *                 the configuration information for SPDIFRX module.
   * @param  pData: Pointer to data buffer
@@ -498,50 +499,49 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
 {
- 
-  if((pData == NULL ) || (Size == 0U)) 
+  if((pData == NULL ) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
-  
+
   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
-  { 
+  {
     /* Process Locked */
     __HAL_LOCK(hspdif);
-    
-     hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-        
-        /* Start synchronization */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-        /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-            
-        /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
-   
-        /* Receive control flow */
+
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+    /* Start synchronization */
+    __HAL_SPDIFRX_SYNC(hspdif);
+
+    /* Wait until SYNCD flag is set */
+    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Start reception */
+    __HAL_SPDIFRX_RCV(hspdif);
+
+    /* Receive control flow */
     while(Size > 0U)
-    {      
+    {
       /* Wait until CSRNE flag is set */
       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
-      { 
+      {
         return HAL_TIMEOUT;
-      }  
+      }
       
       (*pData++) = hspdif->Instance->CSR;
-      Size--; 
-    }      
+      Size--;
+    }
 
     /* SPDIFRX ready */
     hspdif->State = HAL_SPDIFRX_STATE_READY;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hspdif);
-    
+
     return HAL_OK;
   }
   else
@@ -558,9 +558,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
 {
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+  __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
   {
-    if((pData == NULL) || (Size == 0U)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -573,11 +575,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
     hspdif->RxXferCount = Size;
 
     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-    
-    /* Check if a receive process is ongoing or not */
-     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
 
-        
+    /* Check if a receive process is ongoing or not */
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
     /* Enable the SPDIFRX  PE Error Interrupt */
     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
 
@@ -589,27 +590,45 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
 
     /* Enable the SPDIFRX RXNE interrupt */
     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
-        
-        if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) 
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count-- == 0)
         {
-        /* Start synchronization */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-        /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-            
-        /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
         }
+      }
+      while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
@@ -622,9 +641,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
 {
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+  __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
   {
-    if((pData == NULL ) || (Size == 0U)) 
+    if((pData == NULL ) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -637,48 +658,65 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
     hspdif->CsXferCount = Size;
 
     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-    
-    /* Check if a receive process is ongoing or not */
-     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
 
+    /* Check if a receive process is ongoing or not */
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
 
     /* Enable the SPDIFRX PE Error Interrupt */
-     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
 
     /* Enable the SPDIFRX OVR Error Interrupt */
-     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hspdif);
 
     /* Enable the SPDIFRX CSRNE interrupt */
     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
-        
-        if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) 
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count-- == 0)
         {
-        /* Start synchronization */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-        /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-                        
-        /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
+        }
       }
-        
+      while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief Receive an amount of data (Data Flow) mode with DMA 
+  * @brief Receive an amount of data (Data Flow) mode with DMA
   * @param hspdif: SPDIFRX handle
   * @param pData: a 32-bit pointer to the Receive data buffer.
   * @param Size: number of data sample to be received :
@@ -686,67 +724,86 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
 {
-  
-  if((pData == NULL) || (Size == 0U)) 
+  __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  if((pData == NULL) || (Size == 0U))
   {
-    return  HAL_ERROR;                                    
-  } 
+    return  HAL_ERROR;
+  }
   
   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
-  {   
+  {
     hspdif->pRxBuffPtr = pData;
     hspdif->RxXferSize = Size;
     hspdif->RxXferCount = Size;
 
     /* Process Locked */
     __HAL_LOCK(hspdif);
-    
+
     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
-    
+
     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
     hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
-    
+
     /* Set the SPDIFRX Rx DMA transfer complete callback */
     hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
-    
+
     /* Set the DMA error callback */
     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
-       
+
     /* Enable the DMA request */
     HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
 
     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
-     hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
-             
-        if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) 
+    hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count-- == 0)
         {
-        /* Start synchronization */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-        /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-            
-        /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
         }
-    
+      }
+      while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
     /* Process Unlocked */
     __HAL_UNLOCK(hspdif);
-     
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief Receive an amount of data (Control Flow) with DMA 
+  * @brief Receive an amount of data (Control Flow) with DMA
   * @param hspdif: SPDIFRX handle
   * @param pData: a 32-bit pointer to the Receive data buffer.
   * @param Size: number of data (Control Flow) sample to be received :
@@ -754,61 +811,81 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
   */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
 {
-  if((pData == NULL) || (Size == 0U)) 
+  __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  if((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
   {
-    return  HAL_ERROR;                                    
-  } 
-  
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
-  {    
     hspdif->pCsBuffPtr = pData;
     hspdif->CsXferSize = Size;
     hspdif->CsXferCount = Size;
 
     /* Process Locked */
     __HAL_LOCK(hspdif);
-    
+
     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
-    
+
     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
     hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
-    
+
     /* Set the SPDIFRX Rx DMA transfer complete callback */
     hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
-    
+
     /* Set the DMA error callback */
     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
-       
+
     /* Enable the DMA request */
     HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
 
     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
-    
-        if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U) 
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count-- == 0)
         {
-        /* Start synchronization */
-        __HAL_SPDIFRX_SYNC(hspdif);
-        
-        /* Wait until SYNCD flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
-      { 
-        return HAL_TIMEOUT;
-      }  
-            
-        /* Start reception */    
-      __HAL_SPDIFRX_RCV(hspdif);
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
         }
-        
+      }
+      while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
     /* Process Unlocked */
     __HAL_UNLOCK(hspdif);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
@@ -821,23 +898,23 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
 {
   /* Process Locked */
   __HAL_LOCK(hspdif);
-  
+
   /* Disable the SPDIFRX DMA requests */
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
-  
+
   /* Disable the SPDIFRX DMA channel */
   __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
   __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
-  
+
   /* Disable SPDIFRX peripheral */
   __HAL_SPDIFRX_IDLE(hspdif);
-  
+
   hspdif->State = HAL_SPDIFRX_STATE_READY;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hspdif);
-  
+
   return HAL_OK;
 }
 
@@ -847,45 +924,44 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
   * @retval HAL status
   */
 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
-{  
+{
   /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
   {
-      __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
     SPDIFRX_ReceiveDataFlow_IT(hspdif);
   }
-  
-   /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
+
+  /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
   {
-        __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
     SPDIFRX_ReceiveControlFlow_IT(hspdif);
   }
-    
+
   /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
-    
-        /* Change the SPDIFRX error code */
+
+    /* Change the SPDIFRX error code */
     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
-    
-        /* the transfer is not stopped */
+
+    /* the transfer is not stopped */
     HAL_SPDIFRX_ErrorCallback(hspdif);
-  } 
-    
-      /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
+  }
+
+  /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
-    
-        /* Change the SPDIFRX error code */
+
+    /* Change the SPDIFRX error code */
     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
-        
-        /* the transfer is not stopped */
+
+    /* the transfer is not stopped */
     HAL_SPDIFRX_ErrorCallback(hspdif);
   } 
-  
 }
 
 /**
@@ -898,8 +974,8 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
-  */
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+   */
 }
 
 /**
@@ -912,8 +988,8 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
-  */
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+   */
 }
 
 /**
@@ -926,8 +1002,8 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
-  */
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+   */
 }
 
 /**
@@ -940,8 +1016,8 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
-  */
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+   */
 }
 
 /**
@@ -954,24 +1030,24 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspdif);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
-  */ 
+            the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   Peripheral State functions 
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   Peripheral State functions
   *
-@verbatim   
+@verbatim
+===============================================================================
+              ##### Peripheral State and Errors functions #####
 ===============================================================================
-##### Peripheral State and Errors functions #####
-===============================================================================  
 [..]
-This subsection permit to get in run-time the status of the peripheral 
-and the data flow.
+     This subsection permit to get in run-time the status of the peripheral
+     and the data flow.
 
 @endverbatim
   * @{
@@ -999,88 +1075,86 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
 
 /**
   * @}
-  */  
+  */
 
 /**
-  * @brief DMA SPDIFRX receive process (Data flow) complete callback 
+  * @brief DMA SPDIFRX receive process (Data flow) complete callback
   * @param hdma : DMA handle
   * @retval None
   */
 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
 {
   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
+
   /* Disable Rx DMA Request */
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
   hspdif->RxXferCount = 0U;
-  
-  hspdif->State = HAL_SPDIFRX_STATE_READY; 
-  HAL_SPDIFRX_RxCpltCallback(hspdif); 
+
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+  HAL_SPDIFRX_RxCpltCallback(hspdif);
 }
 
 /**
-  * @brief DMA SPDIFRX receive process (Data flow) half complete callback 
+  * @brief DMA SPDIFRX receive process (Data flow) half complete callback
   * @param hdma : DMA handle
   * @retval None
   */
 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  HAL_SPDIFRX_RxHalfCpltCallback(hspdif); 
+
+  HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
 }
 
-
 /**
-  * @brief DMA SPDIFRX receive process (Control flow) complete callback 
+  * @brief DMA SPDIFRX receive process (Control flow) complete callback
   * @param hdma : DMA handle
   * @retval None
   */
 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
 {
   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
+
   /* Disable Cb DMA Request */
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
   hspdif->CsXferCount = 0U;
-  
-  hspdif->State = HAL_SPDIFRX_STATE_READY; 
-  HAL_SPDIFRX_CxCpltCallback(hspdif); 
+
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+  HAL_SPDIFRX_CxCpltCallback(hspdif);
 }
 
 /**
-  * @brief DMA SPDIFRX receive process (Control flow) half complete callback 
+  * @brief DMA SPDIFRX receive process (Control flow) half complete callback
   * @param hdma : DMA handle
   * @retval None
   */
 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
 {
   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  HAL_SPDIFRX_CxHalfCpltCallback(hspdif); 
+
+  HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
 }
 
 /**
-  * @brief DMA SPDIFRX communication error callback 
+  * @brief DMA SPDIFRX communication error callback
   * @param hdma : DMA handle
   * @retval None
   */
 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
 {
   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
+
   /* Disable Rx and Cb DMA Request */
   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
   hspdif->RxXferCount = 0U;
-  
+
   hspdif->State= HAL_SPDIFRX_STATE_READY;
-  
+
   /* Set the error code and execute error callback*/
   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
   HAL_SPDIFRX_ErrorCallback(hspdif);
 }
 
-
 /**
   * @brief Receive an amount of data (Data Flow) with Interrupt
   * @param hspdif: SPDIFRX handle
@@ -1088,22 +1162,22 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
   */
 static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
 {
-    /* Receive data */
-    (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
-    hspdif->RxXferCount--;
+  /* Receive data */
+  (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+  hspdif->RxXferCount--;
 
-    if(hspdif->RxXferCount == 0U)
-    {            
-      /* Disable RXNE/PE and OVR interrupts */
-      __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
+  if(hspdif->RxXferCount == 0U)
+  {
+    /* Disable RXNE/PE and OVR interrupts */
+    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
 
-      hspdif->State = HAL_SPDIFRX_STATE_READY;
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspdif);
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
 
-      HAL_SPDIFRX_RxCpltCallback(hspdif);
-    }
+    HAL_SPDIFRX_RxCpltCallback(hspdif);
+  }
 }
 
 /**
@@ -1113,22 +1187,22 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
   */
 static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
 {
-    /* Receive data */
-    (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
-    hspdif->CsXferCount--;
+  /* Receive data */
+  (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+  hspdif->CsXferCount--;
 
-    if(hspdif->CsXferCount == 0U)
-    {        
-      /* Disable CSRNE interrupt */
-      __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+  if(hspdif->CsXferCount == 0U)
+  {
+    /* Disable CSRNE interrupt */
+    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
 
-       hspdif->State = HAL_SPDIFRX_STATE_READY; 
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspdif);
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
 
-      HAL_SPDIFRX_CxCpltCallback(hspdif);
-    }
+    HAL_SPDIFRX_CxCpltCallback(hspdif);
+  }
 }
 
 /**
@@ -1143,7 +1217,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
 {
   uint32_t tickstart = 0U;
 
-  /* Get tick */ 
+  /* Get tick */
   tickstart = HAL_GetTick();
 
   /* Wait until flag is set */
@@ -1189,7 +1263,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
-                    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h
index ee5d3f1eff..394f21a42e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_spdifrx.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SPDIFRX HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c
index 7e2e45e006..ba900173a7 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SPI HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -54,8 +54,8 @@
           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
      [..]
        Master Receive mode restriction:
-      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or 
-          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI 
+      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
           does not initiate a new transfer the following procedure has to be respected:
           (##) HAL_SPI_DeInit()
           (##) HAL_SPI_Init()
@@ -157,7 +157,6 @@
 /** @addtogroup STM32F4xx_HAL_Driver
   * @{
   */
-
 /** @defgroup SPI SPI
   * @brief SPI HAL module driver
   * @{
@@ -187,7 +186,9 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
@@ -196,16 +197,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif
+#endif /* USE_SPI_CRC */
 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_CheckForDisablingSPI(SPI_HandleTypeDef *hspi);
 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 /**
   * @}
@@ -278,7 +278,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
   }
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
@@ -286,7 +286,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
   }
 #else
   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif
+#endif /* USE_SPI_CRC */
 
   if(hspi->State == HAL_SPI_STATE_RESET)
   {
@@ -312,19 +312,19 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
   /* Configure : NSS management */
   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
   /* Configure : CRC Polynomial */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
 #if defined(SPI_I2SCFGR_I2SMOD)
   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif
+#endif /* USE_SPI_CRC */
 
   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   hspi->State     = HAL_SPI_STATE_READY;
@@ -381,7 +381,6 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
   */
 }
 
-
 /**
   * @brief  De-Initialize the SPI MSP.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -454,7 +453,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   /* Process Locked */
   __HAL_LOCK(hspi);
 
-  /* Init tickstart for timeout managment*/
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   if(hspi->State != HAL_SPI_STATE_READY)
@@ -489,13 +488,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
     SPI_1LINE_TX(hspi);
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Check if the SPI is already enabled */
   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -507,6 +506,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   /* Transmit data in 16 Bit mode */
   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
   {
+    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+    {
+      hspi->Instance->DR = *((uint16_t *)pData);
+      pData += sizeof(uint16_t);
+      hspi->TxXferCount--;
+    }
     /* Transmit data in 16 Bit mode */
     while (hspi->TxXferCount > 0U)
     {
@@ -531,6 +536,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   /* Transmit data in 8 Bit mode */
   else
   {
+    if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+    {
+      *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
+      pData += sizeof(uint8_t);
+      hspi->TxXferCount--;
+    }
     while (hspi->TxXferCount > 0U)
     {
       /* Wait until TXE flag is set to send data */
@@ -552,18 +563,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
     }
   }
 
-#ifdef USE_SPI_CRC
-  /* Enable CRC Transmission */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  /* Wait until TXE flag */
+  if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
   {
-     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+    errorcode = HAL_TIMEOUT;
+    goto error;
   }
-#endif
-
-  /* Check the end of the transaction */
+  
+  /* Check Busy flag */
   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
   {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    errorcode = HAL_ERROR;
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    goto error;
   }
 
   /* Clear overrun flag in 2 Lines communication mode because received is not read */
@@ -571,6 +583,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   {
     __HAL_SPI_CLEAR_OVRFLAG(hspi);
   }
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
 
   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
@@ -595,9 +614,9 @@ error:
   */
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   __IO uint16_t tmpreg = 0U;
-#endif
+#endif /* USE_SPI_CRC */
   uint32_t tickstart = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
@@ -611,7 +630,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   /* Process Locked */
   __HAL_LOCK(hspi);
 
-  /* Init tickstart for timeout managment*/
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   if(hspi->State != HAL_SPI_STATE_READY)
@@ -640,7 +659,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   hspi->RxISR       = NULL;
   hspi->TxISR       = NULL;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
@@ -648,7 +667,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     /* this is done to handle the CRCNEXT before the latest data */
     hspi->RxXferCount--;
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Configure communication direction: 1Line */
   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
@@ -712,7 +731,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     }
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Handle the CRC Transmission */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
@@ -751,29 +770,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     /* To avoid GCC warning */
     UNUSED(tmpreg);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
-  /* Check the end of the transaction */
-  if(SPI_CheckForDisablingSPI(hspi) != HAL_OK)
+  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
   {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
   }
 
-  /* Control the BSY flag */
-  if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    errorcode = HAL_ERROR;
-  }
-
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Check if CRC error occurred */
   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
@@ -798,10 +810,13 @@ error :
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
 {
-#ifdef USE_SPI_CRC
-  __IO uint16_t tmpreg = 0U;
-#endif
+  uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+  __IO uint16_t tmpreg1 = 0U;
+#endif /* USE_SPI_CRC */
   uint32_t tickstart = 0U;
+  /* Variable used to alternate Rx and Tx during transfer */
+  uint32_t txallowed = 1U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
@@ -810,11 +825,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   /* Process Locked */
   __HAL_LOCK(hspi);
 
-  /* Init tickstart for timeout managment*/
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
-
-  if(!((hspi->State == HAL_SPI_STATE_READY) || \
-    ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+  
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+  
+  if(!((tmp == HAL_SPI_STATE_READY) || \
+    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
   {
     errorcode = HAL_BUSY;
     goto error;
@@ -845,13 +863,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   hspi->RxISR       = NULL;
   hspi->TxISR       = NULL;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Check if the SPI is already enabled */
   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -863,22 +881,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   /* Transmit and Receive data in 16 Bit mode */
   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
   {
+    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+    {
+      hspi->Instance->DR = *((uint16_t *)pTxData);
+      pTxData += sizeof(uint16_t);
+      hspi->TxXferCount--;
+    }
     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
     {
       /* Check TXE flag */
-      if((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
       {
         hspi->Instance->DR = *((uint16_t *)pTxData);
         pTxData += sizeof(uint16_t);
         hspi->TxXferCount--;
+        /* Next Data is a reception (Rx). Tx not allowed */ 
+        txallowed = 0U;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
         /* Enable CRC Transmission */
         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
         {
           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
         }
-#endif
+#endif /* USE_SPI_CRC */
       }
 
       /* Check RXNE flag */
@@ -887,6 +913,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
         *((uint16_t *)pRxData) = hspi->Instance->DR;
         pRxData += sizeof(uint16_t);
         hspi->RxXferCount--;
+        /* Next Data is a Transmission (Tx). Tx is allowed */ 
+        txallowed = 1U;
       }
       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
       {
@@ -898,21 +926,29 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   /* Transmit and Receive data in 8 Bit mode */
   else
   {
+    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+    {
+      *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
+      pTxData += sizeof(uint8_t);
+      hspi->TxXferCount--;
+    }
     while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
     {
       /* check TXE flag */
-      if((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
       {
         *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
         hspi->TxXferCount--;
+        /* Next Data is a reception (Rx). Tx not allowed */ 
+        txallowed = 0U;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
         /* Enable CRC Transmission */
         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
         {
           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
         }
-#endif
+#endif /* USE_SPI_CRC */
       }
 
       /* Wait until RXNE flag is reset */
@@ -920,6 +956,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
       {
         (*(uint8_t *)pRxData++) = hspi->Instance->DR;
         hspi->RxXferCount--;
+        /* Next Data is a Transmission (Tx). Tx is allowed */ 
+        txallowed = 1U;
       }
       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
       {
@@ -929,7 +967,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
     }
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Read CRC from DR to close CRC calculation process */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
@@ -942,9 +980,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
       goto error;
     }
     /* Read CRC */
-    tmpreg = hspi->Instance->DR;
+    tmpreg1 = hspi->Instance->DR;
     /* To avoid GCC warning */
-    UNUSED(tmpreg);
+    UNUSED(tmpreg1);
   }
 
   /* Check if CRC error occurred */
@@ -956,15 +994,29 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
 
     errorcode = HAL_ERROR;
   }
-#endif
+#endif /* USE_SPI_CRC */
 
-  /* Check the end of the transaction */
+  /* Wait until TXE flag */
+  if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    errorcode = HAL_TIMEOUT;
+    goto error;
+  }
+  
+  /* Check Busy flag */
   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
   {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
     errorcode = HAL_ERROR;
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    goto error;
   }
 
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+  
 error :
   hspi->State = HAL_SPI_STATE_READY;
   __HAL_UNLOCK(hspi);
@@ -1030,13 +1082,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
     SPI_1LINE_TX(hspi);
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
   {
@@ -1088,6 +1140,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
     errorcode = HAL_BUSY;
     goto error;
   }
+
   if((pData == NULL) || (Size == 0U))
   {
     errorcode = HAL_ERROR;
@@ -1123,13 +1176,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
     SPI_1LINE_RX(hspi);
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Enable TXE and ERR interrupt */
   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -1162,6 +1215,7 @@ error :
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 {
+  uint32_t tmp = 0U, tmp1 = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
@@ -1170,8 +1224,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
   /* Process locked */
   __HAL_LOCK(hspi);
 
-  if(!((hspi->State == HAL_SPI_STATE_READY) || \
-    ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+  
+  if(!((tmp == HAL_SPI_STATE_READY) || \
+    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
   {
     errorcode = HAL_BUSY;
     goto error;
@@ -1210,13 +1267,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
     hspi->TxISR     = SPI_2linesTxISR_8BIT;
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Enable TXE, RXNE and ERR interrupt */
   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
@@ -1284,13 +1341,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
     SPI_1LINE_TX(hspi);
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Set the SPI TxDMA Half transfer complete callback */
   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
@@ -1301,6 +1358,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
   /* Set the DMA error callback */
   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
 
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmatx->XferAbortCallback = NULL;
+
   /* Enable the Tx DMA Stream */
   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
 
@@ -1311,6 +1371,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
     __HAL_SPI_ENABLE(hspi);
   }
 
+  /* Enable the SPI Error Interrupt Bit */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
   /* Enable Tx DMA Request */
   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 
@@ -1374,13 +1437,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
     SPI_1LINE_RX(hspi);
   }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Set the SPI RxDMA Half transfer complete callback */
   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
@@ -1391,6 +1454,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   /* Set the DMA error callback */
   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 
+ /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
   /* Enable the Rx DMA Stream */
   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
 
@@ -1401,6 +1467,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
     __HAL_SPI_ENABLE(hspi);
   }
 
+  /* Enable the SPI Error Interrupt Bit */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
   /* Enable Rx DMA Request */
   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 
@@ -1422,6 +1491,7 @@ error:
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 {
+  uint32_t tmp = 0U, tmp1 = 0U;
   HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
@@ -1430,8 +1500,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   /* Process locked */
   __HAL_LOCK(hspi);
 
-  if(!((hspi->State == HAL_SPI_STATE_READY) ||
-      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+  tmp  = hspi->State;
+  tmp1 = hspi->Init.Mode;
+  if(!((tmp == HAL_SPI_STATE_READY) ||
+      ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
   {
     errorcode = HAL_BUSY;
     goto error;
@@ -1462,13 +1534,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   hspi->RxISR       = NULL;
   hspi->TxISR       = NULL;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Reset CRC Calculation */
   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     SPI_RESET_CRC(hspi);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
   if(hspi->State == HAL_SPI_STATE_BUSY_RX)
@@ -1487,6 +1559,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   /* Set the DMA error callback */
   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
   /* Enable the Rx DMA Stream */
   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
 
@@ -1496,10 +1571,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
   is performed in DMA reception complete callback  */
   hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback = NULL;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+  hspi->hdmatx->XferCpltCallback     = NULL;
+  hspi->hdmatx->XferErrorCallback    = NULL;
+  hspi->hdmatx->XferAbortCallback    = NULL;
 
   /* Enable the Tx DMA Stream */
   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
@@ -1510,6 +1584,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
     /* Enable SPI peripheral */
     __HAL_SPI_ENABLE(hspi);
   }
+  /* Enable the SPI Error Interrupt Bit */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
 
   /* Enable Tx DMA Request */
   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1520,46 +1596,6 @@ error :
   return errorcode;
 }
 
-/**
-  * @brief  Pause the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resume the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
 /**
   * @brief Stop the DMA Transfer.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -1610,17 +1646,17 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
     return;
   }
 
-  /* SPI in mode Transmitter ---------------------------------------------------*/
+  /* SPI in mode Transmitter -------------------------------------------------*/
   if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
   {
     hspi->TxISR(hspi);
     return;
   }
 
-  /* SPI in Error Treatment ---------------------------------------------------*/
- if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+  /* SPI in Error Treatment --------------------------------------------------*/
+  if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
   {
-    /* SPI Overrun error interrupt occurred -------------------------------------*/
+    /* SPI Overrun error interrupt occurred ----------------------------------*/
     if((itflag & SPI_FLAG_OVR) != RESET)
     {
       if(hspi->State != HAL_SPI_STATE_BUSY_TX)
@@ -1630,27 +1666,59 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
       }
       else
       {
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
         return;
       }
     }
 
-    /* SPI Mode Fault error interrupt occurred -------------------------------------*/
+    /* SPI Mode Fault error interrupt occurred -------------------------------*/
     if((itflag & SPI_FLAG_MODF) != RESET)
     {
       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
       __HAL_SPI_CLEAR_MODFFLAG(hspi);
     }
 
-    /* SPI Frame error interrupt occurred ----------------------------------------*/
+    /* SPI Frame error interrupt occurred ------------------------------------*/
     if((itflag & SPI_FLAG_FRE) != RESET)
     {
       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
       __HAL_SPI_CLEAR_FREFLAG(hspi);
     }
 
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-    hspi->State = HAL_SPI_STATE_READY;
-    HAL_SPI_ErrorCallback(hspi);
+    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      /* Disable all interrupts */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+      hspi->State = HAL_SPI_STATE_READY;
+      /* Disable the SPI DMA requests if enabled */
+      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+      {
+        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+        /* Abort the SPI DMA Rx channel */
+        if(hspi->hdmarx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+          HAL_DMA_Abort_IT(hspi->hdmarx);
+        }
+        /* Abort the SPI DMA Tx channel */
+        if(hspi->hdmatx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+          HAL_DMA_Abort_IT(hspi->hdmatx);
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+        HAL_SPI_ErrorCallback(hspi);
+      }
+    }
     return;
   }
 }
@@ -1872,21 +1940,21 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   uint32_t tickstart = 0U;
   __IO uint16_t tmpreg = 0U;
 
-  /* Init tickstart for timeout managment*/
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
-#endif
+#endif /* USE_SPI_CRC */
 
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     /* CRC handling */
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      /* Wait until TXE flag */
+      /* Wait until RXNE flag */
       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
       {
         /* Error on the CRC reception */
@@ -1897,28 +1965,28 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
       /* To avoid GCC warning */
       UNUSED(tmpreg);
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 
-    /* Check the end of the transaction */
-    if(SPI_CheckForDisablingSPI(hspi)!=HAL_OK)
+    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
     {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      /* Disable SPI peripheral */
+      __HAL_SPI_DISABLE(hspi);
     }
 
     hspi->RxXferCount = 0U;
     hspi->State = HAL_SPI_STATE_READY;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     /* Check if CRC error occurred */
     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
     {
       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
     {
@@ -1939,16 +2007,15 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 {
   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
   uint32_t tickstart = 0U;
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   __IO int16_t tmpreg = 0U;
-#endif
-
-  /* Init tickstart for timeout managment*/
+#endif /* USE_SPI_CRC */
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     /* CRC handling */
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
@@ -1962,8 +2029,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
       /* To avoid GCC warning */
       UNUSED(tmpreg);
     }
-#endif
-
+#endif /* USE_SPI_CRC */
     /* Check the end of the transaction */
     if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
     {
@@ -1977,14 +2043,14 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
     hspi->RxXferCount = 0U;
     hspi->State = HAL_SPI_STATE_READY;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     /* Check if CRC error occurred */
     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
     {
       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
     {
@@ -2052,6 +2118,21 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
   HAL_SPI_ErrorCallback(hspi);
 }
 
+/**
+  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hspi->RxXferCount = 0;
+  hspi->TxXferCount = 0;
+
+  HAL_SPI_ErrorCallback(hspi);
+}
+
 /**
   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2067,13 +2148,13 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
   /* check end of the reception */
   if(hspi->RxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
       return;
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     /* Disable RXNE interrupt */
     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -2085,7 +2166,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
   }
 }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
 /**
   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2111,7 +2192,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
     SPI_CloseRxTx_ISR(hspi);
   }
 }
-#endif
+#endif /* USE_SPI_CRC */
 
 /**
   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
@@ -2127,12 +2208,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
   /* check the end of the transmission */
   if(hspi->TxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     /* Disable TXE interrupt */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
@@ -2159,13 +2242,13 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 
   if(hspi->RxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
       return;
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     /* Disable RXNE interrupt */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -2177,7 +2260,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
   }
 }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2200,7 +2283,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 
   SPI_CloseRxTx_ISR(hspi);
 }
-#endif
+#endif /* USE_SPI_CRC */
 
 /**
   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
@@ -2218,12 +2301,14 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
   /* Enable CRC Transmission */
   if(hspi->TxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
     }
-#endif
+#endif /* USE_SPI_CRC */
 
     /* Disable TXE interrupt */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
@@ -2235,7 +2320,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
   }
 }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 8-bit receive in Interrupt context.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2254,7 +2339,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 
   SPI_CloseRx_ISR(hspi);
 }
-#endif
+#endif /* USE_SPI_CRC */
 
 /**
   * @brief  Manage the receive 8-bit in Interrupt context.
@@ -2267,28 +2352,28 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
   hspi->RxXferCount--;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Enable CRC Transmission */
   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
   {
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   if(hspi->RxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       hspi->RxISR =  SPI_RxISR_8BITCRC;
       return;
     }
-#endif
+#endif /* USE_SPI_CRC */
     SPI_CloseRx_ISR(hspi);
   }
 }
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
 /**
   * @brief  Manage the CRC 16-bit receive in Interrupt context.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2310,7 +2395,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 
   SPI_CloseRx_ISR(hspi);
 }
-#endif
+#endif /* USE_SPI_CRC */
 
 /**
   * @brief  Manage the 16-bit receive in Interrupt context.
@@ -2324,23 +2409,23 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
   hspi->pRxBuffPtr += sizeof(uint16_t);
   hspi->RxXferCount--;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   /* Enable CRC Transmission */
   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
   {
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
   }
-#endif
+#endif /* USE_SPI_CRC */
 
   if(hspi->RxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       hspi->RxISR = SPI_RxISR_16BITCRC;
       return;
     }
-#endif
+#endif /* USE_SPI_CRC */
     SPI_CloseRx_ISR(hspi);
   }
 }
@@ -2358,13 +2443,13 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 
   if(hspi->TxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       /* Enable CRC Transmission */
       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
     }
-#endif
+#endif /* USE_SPI_CRC */
     SPI_CloseTx_ISR(hspi);
   }
 }
@@ -2384,13 +2469,13 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 
   if(hspi->TxXferCount == 0U)
   {
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
       /* Enable CRC Transmission */
       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
     }
-#endif
+#endif /* USE_SPI_CRC */
     SPI_CloseTx_ISR(hspi);
   }
 }
@@ -2446,18 +2531,52 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
 }
 
 /**
-  * @brief  Handle to disable SPI in specific condition.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
+  * @brief Handle SPI Communication Timeout.
+  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *              the configuration information for SPI module.
+  * @param Flag: SPI TXE flag to check
+  * @param State: flag state to check
+  * @param Timeout: Timeout duration
+  * @param Tickstart: tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SPI_CheckForDisablingSPI(SPI_HandleTypeDef *hspi)
+static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
 {
-  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET)
   {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
+      {
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+        on both master and slave sides in order to resynchronize the master
+        and slave for their respective CRC calculation */
+
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+        }
+
+        /* Reset CRC Calculation */
+        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
+
+        hspi->State= HAL_SPI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
+
+        return HAL_TIMEOUT;
+      }
+    }
   }
+
   return HAL_OK;
 }
 
@@ -2489,20 +2608,37 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim
 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
 {
   uint32_t tickstart = 0U;
-
+  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
   /* Init tickstart for timeout managment*/
   tickstart = HAL_GetTick();
 
   /* Disable ERR interrupt */
   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 
+  /* Wait until TXE flag is set */
+  do
+  {
+    if(count-- == 0)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      break;
+    }
+  }
+  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+  
   /* Check the end of the transaction */
   if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
   }
 
-#ifdef USE_SPI_CRC
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
   /* Check if CRC error occurred */
   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
   {
@@ -2513,7 +2649,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
   }
   else
   {
-#endif
+#endif /* USE_SPI_CRC */
     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
     {
       if(hspi->State == HAL_SPI_STATE_BUSY_RX)
@@ -2532,9 +2668,9 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
       hspi->State = HAL_SPI_STATE_READY;
       HAL_SPI_ErrorCallback(hspi);
     }
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
   }
-#endif
+#endif /* USE_SPI_CRC */
 }
 
 /**
@@ -2549,13 +2685,20 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 
     /* Check the end of the transaction */
-    if(SPI_CheckForDisablingSPI(hspi)!=HAL_OK)
+    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
     {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      /* Disable SPI peripheral */
+      __HAL_SPI_DISABLE(hspi);
+    }
+
+    /* Clear overrun flag in 2 Lines communication mode because received is not read */
+    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
     }
     hspi->State = HAL_SPI_STATE_READY;
 
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     /* Check if CRC error occurred */
     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
     {
@@ -2565,7 +2708,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
     }
     else
     {
-#endif
+#endif /* USE_SPI_CRC */
       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
       {
         HAL_SPI_RxCpltCallback(hspi);
@@ -2574,9 +2717,9 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
       {
         HAL_SPI_ErrorCallback(hspi);
       }
-#ifdef USE_SPI_CRC
+#if (USE_SPI_CRC != 0U)
     }
-#endif
+#endif /* USE_SPI_CRC */
 }
 
 /**
@@ -2588,15 +2731,27 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
 {
   uint32_t tickstart = 0U;
+  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
 
-  /* Init tickstart for timeout managment*/
+  /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
+  /* Wait until TXE flag is set */
+  do
+  {
+    if(count-- == 0)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      break;
+    }
+  }
+  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
   /* Disable TXE and ERR interrupt */
   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 
-  /* Check the end of the transaction */
-  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
+  /* Check Busy flag */
+  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
   }
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h
index d0bfc6d038..9a5d34d580 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
@@ -129,13 +129,13 @@ typedef struct __SPI_HandleTypeDef
 
   uint16_t                   TxXferSize;   /* SPI Tx Transfer size */
 
-  uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
+  __IO uint16_t              TxXferCount;  /* SPI Tx Transfer Counter */
 
   uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
 
   uint16_t                   RxXferSize;   /* SPI Rx Transfer size */
 
-  uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
+  __IO uint16_t              RxXferCount;  /* SPI Rx Transfer Counter */
 
   void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
 
@@ -369,10 +369,10 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
   do{                                              \
-    __IO uint32_t tmpreg = 0x00U;                  \
-    tmpreg = (__HANDLE__)->Instance->SR;           \
+    __IO uint32_t tmpreg_modf = 0x00U;             \
+    tmpreg_modf = (__HANDLE__)->Instance->SR;      \
     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
-    UNUSED(tmpreg);                                \
+    UNUSED(tmpreg_modf);                           \
   } while(0)
 
 /** @brief  Clear the SPI OVR pending flag.
@@ -382,10 +382,10 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
   do{                                              \
-    __IO uint32_t tmpreg = 0x00U;                  \
-    tmpreg = (__HANDLE__)->Instance->DR;           \
-    tmpreg = (__HANDLE__)->Instance->SR;           \
-    UNUSED(tmpreg);                                \
+    __IO uint32_t tmpreg_ovr = 0x00U;              \
+    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
+    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
+    UNUSED(tmpreg_ovr);                            \
   } while(0)
 
 /** @brief  Clear the SPI FRE pending flag.
@@ -395,9 +395,9 @@ typedef struct __SPI_HandleTypeDef
   */
 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
   do{                                              \
-  __IO uint32_t tmpreg = 0x00U;                    \
-  tmpreg = (__HANDLE__)->Instance->SR;             \
-  UNUSED(tmpreg);                                  \
+  __IO uint32_t tmpreg_fre = 0x00U;                \
+  tmpreg_fre = (__HANDLE__)->Instance->SR;         \
+  UNUSED(tmpreg_fre);                              \
   }while(0)
 
 /** @brief  Enable the SPI peripheral.
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c
index 4bba523c51..ef0008665e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sram.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SRAM HAL module driver.
   *          This file provides a generic firmware to drive SRAM memories  
   *          mounted as external device.
@@ -106,7 +106,8 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -678,7 +679,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx */
 #endif /* HAL_SRAM_MODULE_ENABLED */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h
index 22ead3fdbd..25b1fa18b8 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_sram.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
@@ -44,9 +44,9 @@
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
   #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx*/
 
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -60,7 +60,8 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx)
 
 /** @addtogroup SRAM
   * @{
@@ -192,7 +193,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
   */ 
 
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 
+          STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx */
 /**
   * @}
   */
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c
index fe63704839..90224f4497 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer (TIM) peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h
index 270ad5c2b0..a059329b04 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c
index ba620765f7..2b691e35ad 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer extension peripheral:
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h
index 7c12aec479..1fe0fae0f4 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of TIM HAL Extension module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c
index a2c2c6d1ad..be30ac4226 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   UART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -180,16 +180,19 @@
 /** @addtogroup UART_Private_Functions   UART Private Functions
   * @{
   */
-static void UART_SetConfig (UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma); 
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig (UART_HandleTypeDef *huart);
 /**
   * @}
   */
@@ -277,8 +280,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
   /* In asynchronous mode, the following bits must be kept cleared: 
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
   
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
@@ -330,11 +333,11 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
   /* In half-duplex mode, the following bits must be kept cleared: 
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
   
   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  huart->Instance->CR3 |= USART_CR3_HDSEL;
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
  
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
@@ -391,15 +394,15 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
   /* In LIN mode, the following bits must be kept cleared: 
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
   
   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  huart->Instance->CR2 |= USART_CR2_LINEN;
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
   
   /* Set the USART LIN Break detection length. */
-  huart->Instance->CR2 &= ~(USART_CR2_LBDL);
-  huart->Instance->CR2 |= BreakDetectLength; 
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
+  SET_BIT(huart->Instance->CR2, BreakDetectLength);
   
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
@@ -458,17 +461,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
   /* In Multi-Processor mode, the following bits must be kept cleared: 
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
   
   /* Clear the USART address */
-  huart->Instance->CR2 &= ~(USART_CR2_ADD);
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
   /* Set the USART address node */
-  huart->Instance->CR2 |= Address;
+  SET_BIT(huart->Instance->CR2, Address);
   
   /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  huart->Instance->CR1 &= ~(USART_CR1_WAKE);
-  huart->Instance->CR1 |= WakeUpMethod;
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
+  SET_BIT(huart->Instance->CR1, WakeUpMethod);
   
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
@@ -611,6 +614,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
   
   /* Check that a Tx process is not already ongoing */
   if(huart->gState == HAL_UART_STATE_READY) 
@@ -625,6 +629,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
     
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->gState = HAL_UART_STATE_BUSY_TX;
+	
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
 
     huart->TxXferSize = Size;
     huart->TxXferCount = Size;
@@ -633,7 +640,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
       huart->TxXferCount--;
       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -650,7 +657,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
       } 
       else
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -658,7 +665,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
       } 
     }
     
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     { 
       return HAL_TIMEOUT;
     }
@@ -689,6 +696,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 { 
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
   
   /* Check that a Rx process is not already ongoing */
   if(huart->RxState == HAL_UART_STATE_READY) 
@@ -703,6 +711,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
     
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->RxState = HAL_UART_STATE_BUSY_RX;
+	
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
         
     huart->RxXferSize = Size; 
     huart->RxXferCount = Size;
@@ -713,7 +724,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
       huart->RxXferCount--;
       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -732,7 +743,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
       } 
       else
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         { 
           return HAL_TIMEOUT;
         }
@@ -794,7 +805,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
     __HAL_UNLOCK(huart);
 
     /* Enable the UART Transmit data register empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
     
     return HAL_OK;
   }
@@ -831,18 +842,18 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
     
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->RxState = HAL_UART_STATE_BUSY_RX;
-        
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-    
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
     
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
+        
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
     
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
     /* Enable the UART Data Register not empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+     SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
     
     return HAL_OK;
   }
@@ -871,26 +882,29 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->pTxBuffPtr = pData;
     huart->TxXferSize = Size;
     huart->TxXferCount = Size;
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->gState = HAL_UART_STATE_BUSY_TX;
-        
+
     /* Set the UART DMA transfer complete callback */
     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-    
+
     /* Set the UART DMA Half transfer complete callback */
     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-    
+
     /* Set the DMA error callback */
     huart->hdmatx->XferErrorCallback = UART_DMAError;
 
+    /* Set the DMA abort callback */
+    huart->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the UART transmit DMA Stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
@@ -898,13 +912,13 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
     
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-    
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
     
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    
     return HAL_OK;
   }
   else
@@ -923,7 +937,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
+{  
   uint32_t *tmp;
   
   /* Check that a Rx process is not already ongoing */
@@ -951,14 +965,23 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
     
     /* Set the DMA error callback */
     huart->hdmarx->XferErrorCallback = UART_DMAError;
+    
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
 
     /* Enable the DMA Stream */
     tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
     
     /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
     in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
     
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
@@ -979,18 +1002,25 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
   */
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
 {
+   uint32_t dmarequest = 0x00U;
+
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  if(huart->gState == HAL_UART_STATE_BUSY_TX)
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
   {
     /* Disable the UART DMA Tx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
-  if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
   {
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    
     /* Disable the UART DMA Rx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
   
   /* Process Unlocked */
@@ -1013,14 +1043,19 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
   if(huart->gState == HAL_UART_STATE_BUSY_TX)
   {
     /* Enable the UART DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
   {
     /* Clear the Overrun flag before resuming the Rx transfer*/
     __HAL_UART_CLEAR_OREFLAG(huart);
+    
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    
     /* Enable the UART DMA Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
   
   /* Process Unlocked */
@@ -1037,30 +1072,41 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
   */
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
      and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
      */
   
-  /* Disable the UART Tx/Rx DMA requests */
-  huart->Instance->CR3 &= ~USART_CR3_DMAT;
-  huart->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  /* Abort the UART DMA tx Stream */
-  if(huart->hdmatx != NULL)
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
   {
-    HAL_DMA_Abort(huart->hdmatx);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if(huart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+    UART_EndTxTransfer(huart);
   }
-  /* Abort the UART DMA rx Stream */
-  if(huart->hdmarx != NULL)
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
   {
-    HAL_DMA_Abort(huart->hdmarx);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if(huart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+    UART_EndRxTransfer(huart);
   }
-  
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  
+
   return HAL_OK;
 }
 
@@ -1072,80 +1118,123 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
   */
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
 {
-  uint32_t tmp1 = 0U, tmp2 = 0U;
+   uint32_t isrflags   = READ_REG(huart->Instance->SR);
+   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+   uint32_t errorflags = 0x00U;
+   uint32_t dmarequest = 0x00U;
 
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);  
-  /* UART parity error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_PEFLAG(huart);
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if(errorflags == RESET)
+  {
+    /* UART in mode Receiver -------------------------------------------------*/
+    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      UART_Receive_IT(huart);
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+  {
+    /* UART parity error interrupt occurred ----------------------------------*/
+    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
     
-    huart->ErrorCode |= HAL_UART_ERROR_PE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART frame error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_FEFLAG(huart);
+    /* UART noise error interrupt occurred -----------------------------------*/
+    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
     
-    huart->ErrorCode |= HAL_UART_ERROR_FE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART noise error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_NEFLAG(huart);
+    /* UART frame error interrupt occurred -----------------------------------*/
+    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
     
-    huart->ErrorCode |= HAL_UART_ERROR_NE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART Over-Run interrupt occurred ----------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_ORE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
-  /* UART in mode Receiver ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    UART_Receive_IT(huart);
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
+    /* UART Over-Run interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    { 
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* Call UART Error Call back function if need be --------------------------*/    
+    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver -----------------------------------------------*/
+      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        UART_Receive_IT(huart);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+        
+        /* Disable the UART DMA Rx request if enabled */
+        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+          
+          /* Abort the UART DMA Rx channel */
+          if(huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback : 
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_UART_ErrorCallback(huart);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_UART_ErrorCallback(huart);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_UART_ErrorCallback(huart);
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
   /* UART in mode Transmitter ------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     UART_Transmit_IT(huart);
+    return;
   }
   
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
   /* UART in mode Transmitter end --------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     UART_EndTransmit_IT(huart);
+    return;
   }
-
-  if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-  {
-    /* Set the UART state ready to be able to start again the process */
-    huart->gState = HAL_UART_STATE_READY;
-    huart->RxState = HAL_UART_STATE_READY;
-    
-    HAL_UART_ErrorCallback(huart);
-  }  
 }
 
 /**
@@ -1261,7 +1350,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
   
   /* Send break characters */
-  huart->Instance->CR1 |= USART_CR1_SBK;
+  SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
  
   huart->gState = HAL_UART_STATE_READY;
   
@@ -1288,7 +1377,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
   
   /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  huart->Instance->CR1 |= USART_CR1_RWU;
+  SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
   
   huart->gState = HAL_UART_STATE_READY;
   
@@ -1315,7 +1404,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
   
   /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU);
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
   
   huart->gState = HAL_UART_STATE_READY;
   
@@ -1350,7 +1439,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
   tmpreg |= (uint32_t)USART_CR1_TE;
   
   /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
  
   huart->gState = HAL_UART_STATE_READY;
   
@@ -1385,7 +1474,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
   tmpreg |= (uint32_t)USART_CR1_RE;
   
   /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
   
   huart->gState = HAL_UART_STATE_READY;
   
@@ -1433,11 +1522,11 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
 }
 
 /**
-* @brief  Return the UART error code
-* @param  huart : pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Return the UART error code
+  * @param  huart : pointer to a UART_HandleTypeDef structure that contains
   *              the configuration information for the specified UART.
-* @retval UART Error Code
-*/
+  * @retval UART Error Code
+  */
 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
 {
   return huart->ErrorCode;
@@ -1462,10 +1551,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 
     /* Disable the DMA transfer for transmit request by setting the DMAT bit
        in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Enable the UART Transmit Complete Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 
   }
   /* DMA Circular mode */
@@ -1501,9 +1590,13 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   {
     huart->RxXferCount = 0U;
   
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    
     /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
        in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 	
     /* At end of Rx process, restore huart->RxState to Ready */
     huart->RxState = HAL_UART_STATE_READY;
@@ -1531,11 +1624,25 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void UART_DMAError(DMA_HandleTypeDef *hdma)
 {
+  uint32_t dmarequest = 0x00U;
   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0U;
-  huart->TxXferCount = 0U;
-  huart->gState= HAL_UART_STATE_READY;
-  huart->RxState= HAL_UART_STATE_READY;
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 
+  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
   huart->ErrorCode |= HAL_UART_ERROR_DMA;
   HAL_UART_ErrorCallback(huart);
 }
@@ -1546,72 +1653,82 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   *                the configuration information for the specified UART module.
   * @param  Flag: specifies the UART flag to check.
   * @param  Status: The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
+  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 
   {
-    while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->gState= HAL_UART_STATE_READY;
-	  	  huart->RxState= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->gState= HAL_UART_STATE_READY;
-	  	  huart->RxState= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
         
-          return HAL_TIMEOUT;
-        }
+        huart->gState  = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
+        
+        return HAL_TIMEOUT;
       }
     }
   }
+  
   return HAL_OK;
 }
 
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart: UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart: UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  huart->RxXferCount = 0;
+  huart->TxXferCount = 0;
+
+  HAL_UART_ErrorCallback(huart);
+}
+
 /**
   * @brief  Sends an amount of data in non blocking mode.
   * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
@@ -1646,10 +1763,10 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
     if(--huart->TxXferCount == 0U)
     {
       /* Disable the UART Transmit Complete Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
 
       /* Enable the UART Transmit Complete Interrupt */    
-      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
     }
     return HAL_OK;
   }
@@ -1659,7 +1776,6 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
   }
 }
 
-
 /**
   * @brief  Wraps up transmission in non blocking mode.
   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
@@ -1669,7 +1785,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
 {
   /* Disable the UART Transmit Complete Interrupt */    
-  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
   
   /* Tx process is ended, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
@@ -1720,15 +1836,13 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
 
     if(--huart->RxXferCount == 0U)
     {
-      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
-      /* Disable the UART Parity Error Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 
       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
-	  /* Rx process is completed, restore huart->RxState to Ready */
+      /* Rx process is completed, restore huart->RxState to Ready */
       huart->RxState = HAL_UART_STATE_READY;
      
       HAL_UART_RxCpltCallback(huart);
@@ -1769,7 +1883,7 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
   tmpreg |= (uint32_t)huart->Init.StopBits;
   
   /* Write to USART CR2 */
-  huart->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(huart->Instance->CR2, (uint32_t)tmpreg);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = huart->Instance->CR1;
@@ -1786,7 +1900,7 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
   tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
   
   /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
   
   /*-------------------------- USART CR3 Configuration -----------------------*/  
   tmpreg = huart->Instance->CR3;
@@ -1798,7 +1912,7 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
   tmpreg |= huart->Init.HwFlowCtl;
   
   /* Write to USART CR3 */
-  huart->Instance->CR3 = (uint32_t)tmpreg;
+  WRITE_REG(huart->Instance->CR3, (uint32_t)tmpreg);
   
   /* Check the Over Sampling */
   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h
index ef104e7a6c..39918fb147 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
@@ -653,6 +653,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c
index e648c16a25..ca753e48b5 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c
@@ -2,14 +2,14 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   USART HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -36,69 +36,69 @@
              (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
 
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
         flow control and Mode(Receiver/Transmitter) in the husart Init structure.
 
     (#) Initialize the USART registers by calling the HAL_USART_Init() API:
         (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_USART_MspInit(&husart) API.
-                    
-        -@@- The specific USART interrupts (Transmission complete interrupt, 
+
+        -@@- The specific USART interrupts (Transmission complete interrupt,
              RXNE interrupt and Error Interrupts) will be managed using the macros
              __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-          
-    (#) Three operation modes are available within this driver :     
-  
+
+    (#) Three operation modes are available within this driver :
+
      *** Polling mode IO operation ***
      =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_USART_Transmit() 
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
        (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-       
-     *** Interrupt mode IO operation ***    
+
+     *** Interrupt mode IO operation ***
      ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() 
-       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_USART_ErrorCallback
-    
-     *** DMA mode IO operation ***    
+
+     *** DMA mode IO operation ***
      ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_USART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_USART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_USART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_USART_DMAStop()      
-     
+       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+       (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
      *** USART HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in USART HAL driver.
-       
-       (+) __HAL_USART_ENABLE: Enable the USART peripheral 
-       (+) __HAL_USART_DISABLE: Disable the USART peripheral     
+
+       (+) __HAL_USART_ENABLE: Enable the USART peripheral
+       (+) __HAL_USART_DISABLE: Disable the USART peripheral
        (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
        (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
        (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
        (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-      
-     [..] 
+
+     [..]
        (@) You can refer to the USART HAL driver header file for more useful macros
 
   @endverbatim
@@ -161,6 +161,8 @@
 /** @addtogroup USART_Private_Functions
   * @{
   */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
@@ -170,8 +172,10 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
 /**
   * @}
   */
@@ -181,31 +185,31 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
   * @{
   */
 
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
 @verbatim
   ==============================================================================
               ##### Initialization and Configuration functions #####
   ==============================================================================
   [..]
-  This subsection provides a set of functions allowing to initialize the USART 
+  This subsection provides a set of functions allowing to initialize the USART
   in asynchronous and in synchronous modes.
-  (+) For the asynchronous mode only these parameters can be configured: 
+  (+) For the asynchronous mode only these parameters can be configured:
       (++) Baud Rate
-      (++) Word Length 
+      (++) Word Length
       (++) Stop Bit
       (++) Parity: If the parity is enabled, then the MSB bit of the data written
            in the data register is transmitted but is changed by the parity bit.
            Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           please refer to Reference manual for possible USART frame formats.   
+           please refer to Reference manual for possible USART frame formats.
       (++) USART polarity
       (++) USART phase
       (++) USART LastBit
       (++) Receiver/transmitter modes
 
   [..]
-    The HAL_USART_Init() function follows the USART  synchronous configuration 
+    The HAL_USART_Init() function follows the USART  synchronous configuration
     procedure (details for the procedure are available in reference manual (RM0329)).
 
 @endverbatim
@@ -237,17 +241,17 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
     /* Init the low level hardware */
     HAL_USART_MspInit(husart);
   }
-  
-  husart->State = HAL_USART_STATE_BUSY;  
+
+  husart->State = HAL_USART_STATE_BUSY;
 
   /* Set the USART Communication parameters */
   USART_SetConfig(husart);
 
-  /* In USART mode, the following bits must be kept cleared: 
+  /* In USART mode, the following bits must be kept cleared:
      - LINEN bit in the USART_CR2 register
      - HDSEL, SCEN and IREN bits in the USART_CR3 register */
-  husart->Instance->CR2 &= ~USART_CR2_LINEN;
-  husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
+  CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 
   /* Enable the Peripheral */
   __HAL_USART_ENABLE(husart);
@@ -267,7 +271,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
   */
 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
 {
-   /* Check the USART handle allocation */
+  /* Check the USART handle allocation */
   if(husart == NULL)
   {
     return HAL_ERROR;
@@ -305,7 +309,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   UNUSED(husart);
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_USART_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -320,15 +324,15 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   UNUSED(husart);
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_USART_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions 
-  *  @brief   USART Transmit and Receive functions 
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+  *  @brief   USART Transmit and Receive functions
   *
 @verbatim
   ==============================================================================
@@ -337,31 +341,31 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   [..]
     This subsection provides a set of functions allowing to manage the USART synchronous
     data transfers.
-      
-  [..] 
+
+  [..]
     The USART supports master mode only: it cannot receive or send data related to an input
     clock (SCLK is always an output).
 
     (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode. 
-             The HAL status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode: The communication is performed using Interrupts 
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) No-Blocking mode: The communication is performed using Interrupts
              or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the 
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when 
+             The end of the data processing will be indicated through the
+             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
              using DMA mode.
-             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() 
-              user callbacks 
+             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
+              user callbacks
              will be executed respectively at the end of the transmit or Receive process
-             The HAL_USART_ErrorCallback() user callback will be executed when a communication 
+             The HAL_USART_ErrorCallback() user callback will be executed when a communication
              error is detected
 
     (#) Blocking mode APIs are :
         (++) HAL_USART_Transmit() in simplex mode
         (++) HAL_USART_Receive() in full duplex receive only
         (++) HAL_USART_TransmitReceive() in full duplex mode
-        
+
     (#) Non Blocking mode APIs with Interrupt are :
         (++) HAL_USART_Transmit_IT()in simplex mode
         (++) HAL_USART_Receive_IT() in full duplex receive only
@@ -389,21 +393,22 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   */
 
 /**
-  * @brief  Simplex Send an amount of data in blocking mode. 
+  * @brief  Simplex Send an amount of data in blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data buffer
   * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration    
+  * @param  Timeout: Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
 
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -414,6 +419,9 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_TX;
 
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
+
     husart->TxXferSize = Size;
     husart->TxXferCount = Size;
     while(husart->TxXferCount > 0U)
@@ -422,7 +430,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -439,7 +447,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
       }
       else
       {
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -447,8 +455,8 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
       }
     }
 
-    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
       return HAL_TIMEOUT;
     }
 
@@ -466,21 +474,22 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
 }
 
 /**
-  * @brief  Full-Duplex Receive an amount of data in blocking mode. 
+  * @brief  Full-Duplex Receive an amount of data in blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pRxData: Pointer to data buffer
   * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration    
+  * @param  Timeout: Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
 
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0U)) 
+    if((pRxData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -490,6 +499,9 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_RX;
 
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
+
     husart->RxXferSize = Size;
     husart->RxXferCount = Size;
     /* Check the remain data to be received */
@@ -499,16 +511,16 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
         /* Send dummy byte in order to generate clock */
         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
-        
+
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
         tmp = (uint16_t*) pRxData ;
@@ -526,8 +538,8 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
       else
       {
         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
 
@@ -535,7 +547,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
 
         /* Wait until RXNE flag is set to receive the byte */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -549,7 +561,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
           /* Receive data */
           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
         }
-        
+
       }
     }
 
@@ -567,22 +579,23 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). 
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer  
+  * @param  pRxData: Pointer to data received buffer
   * @param  Size: Amount of data to be sent
-   * @param  Timeout: Timeout duration    
+   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
+  uint32_t tickstart = 0U;
 
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -592,6 +605,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_RX;
 
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
+
     husart->RxXferSize = Size;
     husart->TxXferSize = Size;
     husart->TxXferCount = Size;
@@ -605,7 +621,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -619,9 +635,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
         {
           pTxData += 1U;
         }
-        
+
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -636,18 +652,18 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
           pRxData += 1U;
         }
-      } 
+      }
       else
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
         husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FFU);
 
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -678,7 +694,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
 }
 
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @brief  Simplex Send an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data buffer
@@ -690,7 +706,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
 {
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -705,7 +721,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_TX;
 
-    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) 
+    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
        are not managed by the USART transmit process to avoid the overrun interrupt
        when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
        to benefit for the frame error and noise interrupts the USART mode should be
@@ -717,7 +733,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
     __HAL_UNLOCK(husart);
 
     /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
@@ -728,7 +744,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
 }
 
 /**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
+  * @brief  Simplex Receive an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pRxData: Pointer to data buffer
@@ -739,7 +755,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
 {
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0U)) 
+    if((pRxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -757,16 +773,16 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
     __HAL_UNLOCK(husart);
 
     /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
+    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
     /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
     /* Send dummy byte in order to generate the clock for the slave to send data */
-    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);    
+    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
 
     return HAL_OK;
   }
@@ -777,11 +793,11 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
+  * @param  pRxData: Pointer to data received buffer
   * @param  Size: Amount of data to be received
   * @retval HAL status
   */
@@ -789,7 +805,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
 {
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -808,29 +824,29 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
-    
+
     /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
+    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
     /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @brief  Simplex Send an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data buffer
@@ -840,15 +856,15 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
+
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
     /* Process Locked */
-    __HAL_LOCK(husart);  
+    __HAL_LOCK(husart);
 
     husart->pTxBuffPtr = pTxData;
     husart->TxXferSize = Size;
@@ -866,20 +882,23 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
     /* Set the DMA error callback */
     husart->hdmatx->XferErrorCallback = USART_DMAError;
 
+    /* Set the DMA abort callback */
+    husart->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the USART transmit DMA Stream */
     tmp = (uint32_t*)&pTxData;
     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
 
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
 
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -889,7 +908,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
 }
 
 /**
-  * @brief  Full-Duplex Receive an amount of data in non-blocking mode. 
+  * @brief  Full-Duplex Receive an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pRxData: Pointer to data buffer
@@ -901,10 +920,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
+
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0U)) 
+    if((pRxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -929,30 +948,50 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
     /* Set the USART DMA Rx transfer error callback */
     husart->hdmarx->XferErrorCallback = USART_DMAError;
 
+    /* Set the DMA abort callback */
+    husart->hdmarx->XferAbortCallback = NULL;
+
+    /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
+    is performed in DMA reception complete callback  */
+    husart->hdmatx->XferHalfCpltCallback = NULL;
+    husart->hdmatx->XferCpltCallback = NULL;
+
+    /* Set the DMA error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Set the DMA AbortCpltCallback */
+    husart->hdmatx->XferAbortCallback = NULL;
+
     /* Enable the USART receive DMA Stream */
     tmp = (uint32_t*)&pRxData;
     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
 
     /* Enable the USART transmit DMA Stream: the transmit stream is used in order
-       to generate in the non-blocking mode the clock to the slave device, 
+       to generate in the non-blocking mode the clock to the slave device,
        this mode isn't a simplex receive mode but a full-duplex receive one */
     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
 
     /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
        when using the USART in circular mode */
     __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAR;
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
 
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -962,11 +1001,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
 }
 
 /**
-  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode. 
+  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
+  * @param  pRxData: Pointer to data received buffer
   * @param  Size: Amount of data to be received
   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
   * @retval HAL status
@@ -974,10 +1013,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
+
   if(husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -1010,6 +1049,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
     /* Set the USART DMA Rx transfer error callback */
     husart->hdmarx->XferErrorCallback = USART_DMAError;
 
+    /* Set the DMA abort callback */
+    husart->hdmarx->XferAbortCallback = NULL;
+
     /* Enable the USART receive DMA Stream */
     tmp = (uint32_t*)&pRxData;
     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
@@ -1017,24 +1059,30 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
     /* Enable the USART transmit DMA Stream */
     tmp = (uint32_t*)&pTxData;
     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-    
+
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-    
+
     /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
     __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAR;
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
 
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -1053,14 +1101,14 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
 {
   /* Process Locked */
   __HAL_LOCK(husart);
-  
+
   /* Disable the USART DMA Tx request */
-  husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-  
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
   /* Process Unlocked */
   __HAL_UNLOCK(husart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
@@ -1073,13 +1121,13 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
 {
   /* Process Locked */
   __HAL_LOCK(husart);
-  
+
   /* Enable the USART DMA Tx request */
-  husart->Instance->CR3 |= USART_CR3_DMAT;
-  
+  SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
   /* Process Unlocked */
   __HAL_UNLOCK(husart);
-  
+
   return HAL_OK;
 }
 
@@ -1091,28 +1139,44 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
   */
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
      and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
      */
 
-  /* Abort the USART DMA Tx Stream */
-  if(husart->hdmatx != NULL)
+  /* Stop USART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+  if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
   {
-    HAL_DMA_Abort(husart->hdmatx);
+    USART_EndTxTransfer(husart);
+
+    /* Abort the USART DMA Tx channel */
+    if(husart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(husart->hdmatx);
+    }
+
+    /* Disable the USART Tx DMA request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
   }
-  /* Abort the USART DMA Rx Stream */
-  if(husart->hdmarx != NULL)
-  {  
-    HAL_DMA_Abort(husart->hdmarx);
+
+  /* Stop USART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+  if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+  {
+    USART_EndRxTransfer(husart);
+
+    /* Abort the USART DMA Rx channel */
+    if(husart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(husart->hdmarx);
+    }
+
+    /* Disable the USART Rx DMA request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
   }
-  
-  /* Disable the USART Tx/Rx DMA requests */
-  husart->Instance->CR3 &= ~USART_CR3_DMAT;
-  husart->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  husart->State = HAL_USART_STATE_READY;
 
   return HAL_OK;
 }
@@ -1125,71 +1189,122 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
   */
 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
 {
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-  
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
-  /* USART parity error interrupt occurred -----------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_PEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_PE;
-  }
+  uint32_t isrflags = READ_REG(husart->Instance->SR);
+  uint32_t cr1its   = READ_REG(husart->Instance->CR1);
+  uint32_t cr3its   = READ_REG(husart->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART frame error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if(errorflags == RESET)
   {
-    __HAL_USART_CLEAR_FEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_FE;
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART noise error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_NEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_NE;
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART Over-Run interrupt occurred ---------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_ORE;
-  }
-
-  if(husart->ErrorCode != HAL_USART_ERROR_NONE)
-  {
-    /* Set the USART state ready to be able to start again the process */
-    husart->State = HAL_USART_STATE_READY;
-    
-    HAL_USART_ErrorCallback(husart);
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
-  /* USART in mode Receiver --------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    /* USART in mode Receiver -------------------------------------------------*/
+    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
     {
-      USART_Receive_IT(husart);
-    }
-    else
-    {
-      USART_TransmitReceive_IT(husart);
+      if(husart->State == HAL_USART_STATE_BUSY_RX)
+      {
+        USART_Receive_IT(husart);
+      }
+      else
+      {
+        USART_TransmitReceive_IT(husart);
+      }
+      return;
     }
   }
+  /* If some errors occur */
+  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+  {
+    /* USART parity error interrupt occurred ----------------------------------*/
+    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_PE;
+    }
+
+    /* USART noise error interrupt occurred --------------------------------*/
+    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_NE;
+    }
+
+    /* USART frame error interrupt occurred --------------------------------*/
+    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_FE;
+    }
+
+    /* USART Over-Run interrupt occurred -----------------------------------*/
+    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_ORE;
+    }
+
+    if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+    {
+      /* USART in mode Receiver -----------------------------------------------*/
+      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        if(husart->State == HAL_USART_STATE_BUSY_RX)
+        {
+          USART_Receive_IT(husart);
+        }
+        else
+        {
+          USART_TransmitReceive_IT(husart);
+        }
+      }
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+      consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+      if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Set the USART state ready to be able to start again the process,
+        Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        USART_EndRxTransfer(husart);
+
+        /* Disable the USART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the USART DMA Rx channel */
+          if(husart->hdmarx != NULL)
+          {
+            /* Set the USART DMA Abort callback :
+            will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+            if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              husart->hdmarx->XferAbortCallback(husart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_USART_ErrorCallback(husart);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_USART_ErrorCallback(husart);
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+        HAL_USART_ErrorCallback(husart);
+        husart->ErrorCode = HAL_USART_ERROR_NONE;
+      }
+    }
+    return;
+  }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
   /* USART in mode Transmitter -----------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     if(husart->State == HAL_USART_STATE_BUSY_TX)
     {
@@ -1199,14 +1314,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
     {
       USART_TransmitReceive_IT(husart);
     }
+    return;
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
   /* USART in mode Transmitter (transmission end) ----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     USART_EndTransmit_IT(husart);
+    return;
   }
 }
 
@@ -1294,31 +1409,31 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
  __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
 {
   /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart); 
+  UNUSED(husart);
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_USART_ErrorCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   USART State and Errors functions 
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   USART State and Errors functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                   ##### Peripheral State and Errors functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection provides a set of functions allowing to return the State of 
+    This subsection provides a set of functions allowing to return the State of
     USART communication
     process, return Peripheral Errors occurred during communication process
-     (+) HAL_USART_GetState() API can be helpful to check in run-time the state 
+     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
          of the USART peripheral.
-     (+) HAL_USART_GetError() check in run-time errors that could be occurred during 
-         communication. 
+     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+         communication.
 @endverbatim
   * @{
   */
@@ -1348,10 +1463,9 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
 /**
   * @}
   */
-  
 
 /**
-  * @brief  DMA USART transmit process complete callback. 
+  * @brief  DMA USART transmit process complete callback.
   * @param  hdma: DMA handle
   * @retval None
   */
@@ -1367,9 +1481,9 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
          in the USART CR3 register */
       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-      
-      /* Enable the USART Transmit Complete Interrupt */    
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
     }
   }
   /* DMA Circular mode */
@@ -1383,7 +1497,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief DMA USART transmit process half complete callback 
+  * @brief DMA USART transmit process half complete callback
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
@@ -1396,7 +1510,7 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief  DMA USART receive process complete callback. 
+  * @brief  DMA USART receive process complete callback.
   * @param  hdma: DMA handle
   * @retval None
   */
@@ -1406,12 +1520,17 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   /* DMA Normal mode */
   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    husart->RxXferCount = 0U;
+    husart->RxXferCount = 0x00U;
+
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
     if(husart->State == HAL_USART_STATE_BUSY_RX)
     {
-      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
+      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
          in the USART CR3 register */
-      husart->Instance->CR3 &= ~(USART_CR3_DMAR);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
 
       husart->State= HAL_USART_STATE_READY;
       HAL_USART_RxCpltCallback(husart);
@@ -1419,11 +1538,11 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
     else
     {
-      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
+      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
          in the USART CR3 register */
-      husart->Instance->CR3 &= ~(USART_CR3_DMAR);
-      husart->Instance->CR3 &= ~(USART_CR3_DMAT);
- 
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
       husart->State= HAL_USART_STATE_READY;
       HAL_USART_TxRxCpltCallback(husart);
     }
@@ -1444,7 +1563,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief DMA USART receive process half complete callback 
+  * @brief DMA USART receive process half complete callback
   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
@@ -1453,99 +1572,131 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
 
-  HAL_USART_RxHalfCpltCallback(husart); 
+  HAL_USART_RxHalfCpltCallback(husart);
 }
 
 /**
-  * @brief  DMA USART communication error callback. 
+  * @brief  DMA USART communication error callback.
   * @param  hdma: DMA handle
   * @retval None
   */
 static void USART_DMAError(DMA_HandleTypeDef *hdma)
 {
+  uint32_t dmarequest = 0x00U;
   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  husart->RxXferCount = 0x00U;
+  husart->TxXferCount = 0x00U;
+
+  /* Stop USART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+  if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+  {
+    USART_EndTxTransfer(husart);
+  }
+
+  /* Stop USART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+  if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+  {
+    USART_EndRxTransfer(husart);
+  }
 
-  husart->RxXferCount = 0U;
-  husart->TxXferCount = 0U;
   husart->ErrorCode |= HAL_USART_ERROR_DMA;
   husart->State= HAL_USART_STATE_READY;
-  
+
   HAL_USART_ErrorCallback(husart);
 }
 
 /**
   * @brief  This function handles USART Communication Timeout.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
+  *                 the configuration information for the specified USART module.
   * @param  Flag: specifies the USART flag to check.
   * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  Tickstart: Tick start value.
+  * @param  Timeout: Timeout duration.
   * @retval HAL status
   */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
+  while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+        /* Disable the USART Transmit Complete Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
-          husart->State= HAL_USART_STATE_READY;
+        /* Disable the USART RXNE Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
+        /* Disable the USART Parity Error Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+        /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
-          husart->State= HAL_USART_STATE_READY;
+        husart->State= HAL_USART_STATE_READY;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
+        /* Process Unlocked */
+        __HAL_UNLOCK(husart);
 
-          return HAL_TIMEOUT;
-        }
+        return HAL_TIMEOUT;
       }
     }
   }
   return HAL_OK;
 }
 
-  
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
+  * @param  husart: USART handle.
+  * @retval None
+  */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
+  * @param  husart: USART handle.
+  * @retval None
+  */
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable RXNE, PE and ERR interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  husart->RxXferCount = 0x00U;
+  husart->TxXferCount = 0x00U;
+
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  Simplex Send an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
@@ -1554,7 +1705,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
 {
   uint16_t* tmp;
- 
+
   if(husart->State == HAL_USART_STATE_BUSY_TX)
   {
     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
@@ -1569,19 +1720,19 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
       {
         husart->pTxBuffPtr += 1U;
       }
-    } 
+    }
     else
-    { 
+    {
       husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
     }
-    
+
     if(--husart->TxXferCount == 0U)
     {
       /* Disable the USART Transmit data register empty Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
-      /* Enable the USART Transmit Complete Interrupt */    
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+      /* Enable the USART Transmit Complete Interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
     }
     return HAL_OK;
   }
@@ -1599,21 +1750,21 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
   */
 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
 {
-  /* Disable the USART Transmit Complete Interrupt */    
-  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-  
+  /* Disable the USART Transmit Complete Interrupt */
+  CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+
   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-    
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
   husart->State = HAL_USART_STATE_READY;
-   
+
   HAL_USART_TxCpltCallback(husart);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
+  * @brief  Simplex Receive an amount of data in non-blocking mode.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
@@ -1636,12 +1787,12 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
         husart->pRxBuffPtr += 1U;
       }
-      if(--husart->RxXferCount != 0x00U) 
+      if(--husart->RxXferCount != 0x00U)
       {
         /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU); 
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
       }
-    } 
+    }
     else
     {
       if(husart->Init.Parity == USART_PARITY_NONE)
@@ -1653,39 +1804,39 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
       }
 
-      if(--husart->RxXferCount != 0x00U) 
+      if(--husart->RxXferCount != 0x00U)
       {
         /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);  
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
       }
     }
 
     if(husart->RxXferCount == 0U)
     {
       /* Disable the USART RXNE Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
       /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
       husart->State = HAL_USART_STATE_READY;
       HAL_USART_RxCpltCallback(husart);
-      
+
       return HAL_OK;
     }
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
@@ -1712,7 +1863,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
           {
             husart->pTxBuffPtr += 1U;
           }
-        } 
+        }
         else
         {
           husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
@@ -1722,7 +1873,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
         /* Check the latest data transmitted */
         if(husart->TxXferCount == 0U)
         {
-           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+          CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
         }
       }
     }
@@ -1744,7 +1895,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
             husart->pRxBuffPtr += 1U;
           }
-        } 
+        }
         else
         {
           if(husart->Init.Parity == USART_PARITY_NONE)
@@ -1763,14 +1914,15 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
     /* Check the latest data received */
     if(husart->RxXferCount == 0U)
     {
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+      /* Disable the USART RXNE Interrupt */
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
       /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-      
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
       husart->State = HAL_USART_STATE_READY;
 
       HAL_USART_TxRxCpltCallback(husart);
@@ -1782,12 +1934,12 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Configures the USART peripheral. 
+  * @brief  Configures the USART pferipheral.
   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
@@ -1801,7 +1953,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
-  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));  
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
   assert_param(IS_USART_PARITY(husart->Init.Parity));
@@ -1809,7 +1961,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
 
   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  husart->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
 
   /*---------------------------- USART CR2 Configuration ---------------------*/
   tmpreg = husart->Instance->CR2;
@@ -1820,10 +1972,10 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
   /* Set CPHA bit according to husart->Init.CLKPhase value */
   /* Set LBCL bit according to husart->Init.CLKLastBit value */
   /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
-  tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | 
-                      husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
+  tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
+                       husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
   /* Write to USART CR2 */
-  husart->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = husart->Instance->CR1;
@@ -1832,19 +1984,19 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
                                    USART_CR1_RE | USART_CR1_OVER8));
 
-  /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to husart->Init.WordLength value 
+  /* Configure the USART Word Length, Parity and mode:
+     Set the M bits according to husart->Init.WordLength value
      Set PCE and PS bits according to husart->Init.Parity value
-     Set TE and RE bits according to husart->Init.Mode value 
+     Set TE and RE bits according to husart->Init.Mode value
      Force OVER8 bit to 1 in order to reach the max USART frequencies */
   tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
 
   /* Write to USART CR1 */
-  husart->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(husart->Instance->CR1, (uint32_t)tmpreg);
 
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Clear CTSE and RTSE bits */
-  husart->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
 
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((husart->Instance == USART1) || (husart->Instance == USART6))
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h
index 6caaf74633..520b7368cf 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
@@ -486,6 +486,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+
 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c
index 8d89914ccc..b8b6cafe83 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c
@@ -2,14 +2,14 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   WWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Window Watchdog (WWDG) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral State functions       
+  *           + Peripheral State functions
   @verbatim
   ==============================================================================
                       ##### WWDG specific features #####
@@ -36,35 +36,55 @@
     
     (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms 
 
+    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety 
+        operations or data logging must be performed before the actual reset is
+        generated. When the downcounter reaches the value 0x40, an EWI interrupt
+        is generated and the corresponding interrupt service routine (ISR) can 
+        be used to trigger specific actions (such as communications or data 
+        logging), before resetting the device.
+        In some applications, the EWI interrupt can be used to manage a software
+        system check and/or system recovery/graceful degradation, without 
+        generating a WWDG reset. In this case, the corresponding interrupt 
+        service routine (ISR) should reload the WWDG counter to avoid the WWDG 
+        reset, then trigger the required actions.
+        Note:When the EWI interrupt cannot be served, e.g. due to a system lock 
+        in a higher priority task, the WWDG reset will eventually be generated.
+
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the WWDG counter either continues to work normally or stops, depending 
+        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
 
                      ##### How to use this driver #####
   ==============================================================================
   [..]
     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-    (+) Set the WWDG prescaler, refresh window and counter value 
-        using HAL_WWDG_Init() function.
-    (+) Start the WWDG using HAL_WWDG_Start() function.
-        When the WWDG is enabled the counter value should be configured to 
-        a value greater than 0x40 to prevent generating an immediate reset.
-    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is 
-        generated when the counter reaches 0x40, and then start the WWDG using
-        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can 
-        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
-        Once enabled, EWI interrupt cannot be disabled except by a system reset.          
-    (+) Then the application program must refresh the WWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
+
+    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup 
+        Interrupt mode using using HAL_WWDG_Init() function.
+        This enables WWDG peripheral and the downcounter starts downcounting 
+        from given counter value.
+        Init function can be called again to modify all watchdog parameters, 
+        however if EWI mode has been set once, it can't be clear until next 
+        reset.
+
+    (+) The application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset using
         HAL_WWDG_Refresh() function. This operation must occur only when
-        the counter is lower than the refresh window value already programmed.
-        
+        the counter is lower than the window value already programmed.
+
+    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when 
+        the counter reaches 0x40. User can add his own code in weak function 
+        HAL_WWDG_EarlyWakeupCallback().
+
      *** WWDG HAL driver macros list ***
      ==================================
      [..]
        Below the list of most used macros in WWDG HAL driver.
-       
-      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral 
-      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
-      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags 
-      (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt 
+
+      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
 
   @endverbatim
   ******************************************************************************
@@ -95,7 +115,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
@@ -104,47 +124,45 @@
   * @{
   */
 
+#ifdef HAL_WWDG_MODULE_ENABLED
 /** @defgroup WWDG WWDG
   * @brief WWDG HAL module driver.
   * @{
   */
 
-#ifdef HAL_WWDG_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
   * @{
   */
 
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
   ==============================================================================
-          ##### Initialization and de-initialization functions #####
+          ##### Initialization and Configuration functions #####
   ==============================================================================
   [..]  
     This section provides functions allowing to:
-    (+) Initialize the WWDG according to the specified parameters 
-        in the WWDG_InitTypeDef and create the associated handle
-    (+) DeInitialize the WWDG peripheral
-    (+) Initialize the WWDG MSP
-    (+) DeInitialize the WWDG MSP 
- 
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the WWDG according to the specified
-  *         parameters in the WWDG_InitTypeDef and creates the associated handle.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
@@ -158,101 +176,39 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
   /* Check the parameters */
   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
-  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); 
-  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); 
-  
-  if(hwwdg->State == HAL_WWDG_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hwwdg->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_WWDG_MspInit(hwwdg);
-  }
-  
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
 
   /* Set WWDG Prescaler and Window */
-  MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
-  /* Set WWDG Counter */
-  MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
-
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the WWDG peripheral. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
-{ 
-  /* Check the WWDG handle allocation */
-  if(hwwdg == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_WWDG_MspDeInit(hwwdg);
-  
-  /* Reset WWDG Control register */
-  hwwdg->Instance->CR  = (uint32_t)0x0000007FU;
-  
-  /* Reset WWDG Configuration register */
-  hwwdg->Instance->CFR = (uint32_t)0x0000007FU;
-  
-  /* Reset WWDG Status register */
-  hwwdg->Instance->SR  = 0U; 
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hwwdg);
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
 
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Initializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
   * @retval None
   */
 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hwwdg);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_MspInit could be implemented in the user file
-   */
-}
 
-/**
-  * @brief  DeInitializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_MspDeInit could be implemented in the user file
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
    */
 }
 
@@ -260,184 +216,82 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
   * @}
   */
 
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions 
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
  *  @brief    IO operation functions 
  *
-@verbatim   
+@verbatim
   ==============================================================================
-                       ##### IO operation functions #####
+                      ##### IO operation functions #####
   ==============================================================================  
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Start the WWDG.
     (+) Refresh the WWDG.
-    (+) Handle WWDG interrupt request. 
+    (+) Handle WWDG interrupt request and associated function callback.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Starts the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
 {
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the WWDG with interrupt enabled.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Enable the Early Wakeup Interrupt */ 
-  __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
-
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Refreshes the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @param  Counter: value of counter to put in WWDG counter
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
-{
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  
   /* Write to WWDG CR the WWDG Counter value to refresh with */
-  MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Handles WWDG interrupt request.
-  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations 
-  *         or data logging must be performed before the actual reset is generated. 
-  *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
-  *         When the downcounter reaches the value 0x40, and EWI interrupt is 
-  *         generated and the corresponding Interrupt Service Routine (ISR) can 
-  *         be used to trigger specific actions (such as communications or data 
-  *         logging), before resetting the device. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with 
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval None
   */
 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{ 
+{
   /* Check if Early Wakeup Interrupt is enable */
   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
   {
     /* Check if WWDG Early Wakeup Interrupt occurred */
     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
     {
-      /* Early Wakeup callback */ 
-      HAL_WWDG_WakeupCallback(hwwdg);
-      
-      /* Change WWDG peripheral state */
-      hwwdg->State = HAL_WWDG_STATE_READY; 
-      
       /* Clear the WWDG Early Wakeup flag */
       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hwwdg);
+
+      /* Early Wakeup callback */ 
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
     }
   }
-} 
-
-/**
-  * @brief  Early Wakeup WWDG callback.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);  
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_WakeupCallback could be implemented in the user file
-   */
 }
 
 /**
-  * @}
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg : pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
   */
-
-/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the WWDG state.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL state
-  */
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
 {
-  return hwwdg->State;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
 }
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h
index d9860c0497..baab64b56d 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
@@ -58,62 +58,50 @@
 /** @defgroup WWDG_Exported_Types WWDG Exported Types
   * @{
   */
-   
-/**
-  * @brief  WWDG HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_WWDG_STATE_RESET     = 0x00U,  /*!< WWDG not yet initialized or disabled */
-  HAL_WWDG_STATE_READY     = 0x01U,  /*!< WWDG initialized and ready for use   */
-  HAL_WWDG_STATE_BUSY      = 0x02U,  /*!< WWDG internal process is ongoing     */
-  HAL_WWDG_STATE_TIMEOUT   = 0x03U,  /*!< WWDG timeout state                   */
-  HAL_WWDG_STATE_ERROR     = 0x04U   /*!< WWDG error state                     */
-}HAL_WWDG_StateTypeDef;
 
 /** 
-  * @brief  WWDG Init structure definition  
-  */ 
+  * @brief  WWDG Init structure definition
+  */
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
-                            This parameter can be a value of @ref WWDG_Prescaler */
-  
-  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
-                            This parameter must be a number lower than Max_Data = 0x80 */ 
-  
-  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
-                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
 
 }WWDG_InitTypeDef;
 
-/** 
-  * @brief  WWDG handle Structure definition  
-  */ 
+/**
+  * @brief  WWDG handle Structure definition
+  */
 typedef struct
 {
   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
-  
+
   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
-  
-  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
-  
+
 }WWDG_HandleTypeDef;
 /**
   * @}
-  */ 
+  */
 
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
   * @{
   */
 
 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
   * @{
-  */ 
-#define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
 /**
   * @}
   */
@@ -121,8 +109,8 @@ typedef struct
 /** @defgroup WWDG_Flag_definition WWDG Flag definition
   * @brief WWDG Flag definition
   * @{
-  */ 
-#define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
 /**
   * @}
   */
@@ -136,23 +124,48 @@ typedef struct
 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
 /**
   * @}
-  */ 
+  */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
+/**
+  * @}
+  */
 
 /**
   * @}
-  */ 
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
 
-/* Exported macro ------------------------------------------------------------*/
 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
   * @{
   */
 
-/** @brief Reset WWDG handle state
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
-
 /**
   * @brief  Enables the WWDG peripheral.
   * @param  __HANDLE__: WWDG handle
@@ -161,18 +174,20 @@ typedef struct
 #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
 
 /**
-  * @brief  Disables the WWDG peripheral.
+  * @brief  Enables the WWDG early wakeup interrupt.
   * @param  __HANDLE__: WWDG handle
-  * @note   WARNING: This is a dummy macro for HAL code alignment.
-  *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
   * @retval None
   */
-#define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
 
 /**
-  * @brief  Gets the selected WWDG's it status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the it to check.
+  * @brief  Checks whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
   *        This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
   * @retval The new state of WWDG_FLAG (SET or RESET).
@@ -189,32 +204,9 @@ typedef struct
 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
 
 /**
-  * @brief  Enables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-    
-/**
-  * @brief  Disables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to disable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   WARNING: This is a dummy macro for HAL code alignment. 
-  *         Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
-    
-/**
-  * @brief  Gets the selected WWDG's flag status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   * @retval The new state of WWDG_FLAG (SET or RESET).
@@ -253,11 +245,8 @@ typedef struct
   * @{
   */
 /* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
 /**
   * @}
   */
@@ -266,42 +255,17 @@ void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
   * @{
   */
 /* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
 /**
   * @}
   */
 
-/** @addtogroup WWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-/**
-  * @}
-  */ 
-
 /**
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup WWDG_Private_Constants WWDG Private Constants
-  * @{
-  */
-/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
-  * @brief WWDG registers bit address in the alias region
-  * @{
-  */
-
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define WWDG_CFR_BASE   (uint32_t)(WWDG_BASE + 0x04U)
-
 /**
   * @}
   */
@@ -310,36 +274,6 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
-  * @{
-  */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_8))
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7FU)
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup WWDG_Private_Functions WWDG Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
index 76a97022a4..46f08281e6 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_fmc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -1371,7 +1371,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
 
   /* Set SDRAM bank configuration parameters */
   if (Init->SDBank != FMC_SDRAM_BANK2) 
-  { 
+  {    
     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
     
     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
@@ -1397,9 +1397,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
     
     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
-                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
-                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+    tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
     
     tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
                         Init->ReadBurst          |\
@@ -1469,34 +1467,32 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim
                        (((Timing->RCDDelay)-1U) << 24U));
     Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
   }
-  else /* FMC_Bank2_SDRAM */
-  {  
-    tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
+   else /* FMC_Bank2_SDRAM */
+  {
+    tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
     
-    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
-    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
-                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
-                          FMC_SDTR1_TRCD));
+    /* Clear TRC and TRP bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
     
-    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U)           |\
-                       (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
-                       (((Timing->SelfRefreshTime)-1U) << 8U)      |\
-                       (((Timing->WriteRecoveryTime)-1U) <<16U)    |\
-                       (((Timing->RCDDelay)-1U) << 24U));   
+    tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
+                        (((Timing->RPDelay)-1) << 20)); 
     
-    tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
+    tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
     
     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
     tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
                           FMC_SDTR1_TRCD));
-    tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U)       |\
-                        (((Timing->RPDelay)-1U) << 20U)); 
+    
+    tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1)           |\
+                       (((Timing->ExitSelfRefreshDelay)-1) << 4)  |\
+                       (((Timing->SelfRefreshTime)-1) << 8)       |\
+                       (((Timing->WriteRecoveryTime)-1) <<16)     |\
+                       (((Timing->RCDDelay)-1) << 24)));   
 
-    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
-    Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
-  }   
-  
+    Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
+    Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
+  }
   return HAL_OK;
 }
 
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h
index ef40c7e53a..0b6070a76a 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_fmc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FMC HAL module.
   ******************************************************************************
   * @attention
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c
index 78d2320c69..91080606ef 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_fsmc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   FSMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -15,7 +15,7 @@
   @verbatim
   ==============================================================================
                         ##### FSMC peripheral features #####
-  ==============================================================================
+  ==============================================================================                  
     [..] The Flexible static memory controller (FSMC) includes two memory controllers:
          (+) The NOR/PSRAM memory controller
          (+) The NAND/PC Card memory controller
@@ -84,7 +84,7 @@
   */
 
 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -99,7 +99,7 @@
   * @brief    NORSRAM Controller functions 
   *
   @verbatim 
-  ==============================================================================   
+  ==============================================================================
                    ##### How to use NORSRAM device driver #####
   ==============================================================================
  
@@ -165,10 +165,15 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
-
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+  assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
+  assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#endif /* STM32F412Zx || TM32F412Vx */
+  
   /* Get the BTCR register value */
   tmpr = Device->BTCR[Init->NSBank];
 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
   /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
            WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
   tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN     | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP     | \
@@ -191,7 +196,32 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
                      Init->PageSize             |\
                      Init->WriteBurst
                      );
-
+#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+  /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
+           WAITEN, EXTMOD, ASYNCWAIT,CPSIZE,  CBURSTRW, CCLKEN and WFDIS bits */
+  tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN     | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP      | \
+                       FSMC_BCR1_MWID      | FSMC_BCR1_FACCEN   | FSMC_BCR1_BURSTEN   | \
+                       FSMC_BCR1_WAITPOL   | FSMC_BCR1_WAITCFG  | FSMC_BCR1_WREN      | \
+                       FSMC_BCR1_WAITEN    | FSMC_BCR1_EXTMOD   | FSMC_BCR1_ASYNCWAIT | \
+                       FSMC_BCR1_CPSIZE    | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN    | \
+                       FSMC_BCR1_WFDIS));
+  /* Set NORSRAM device control parameters */
+  tmpr |= (uint32_t)(Init->DataAddressMux       |\
+                     Init->MemoryType           |\
+                     Init->MemoryDataWidth      |\
+                     Init->BurstAccessMode      |\
+                     Init->WaitSignalPolarity   |\
+                     Init->WaitSignalActive     |\
+                     Init->WriteOperation       |\
+                     Init->WaitSignal           |\
+                     Init->ExtendedMode         |\
+                     Init->AsynchronousWait     |\
+                     Init->WriteBurst           |\
+                     Init->ContinuousClock      |\
+                     Init->PageSize             |\
+                     Init->WriteFifo);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 
+            
   if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
   {
     tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
@@ -199,6 +229,19 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
 
   Device->BTCR[Init->NSBank] = tmpr;
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
+  {
+    Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
+  }
+
+  if(Init->NSBank != FSMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
+  }
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+
   return HAL_OK;
 }
 
@@ -280,6 +323,16 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
   
   Device->BTCR[Bank + 1] = tmpr; 
 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U)); 
+    tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
+    Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
+  }
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
+
   return HAL_OK;
 }
 
@@ -646,7 +699,7 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 @verbatim   
   ==============================================================================
                        ##### FSMC_NAND Control functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control dynamically
     the FSMC NAND interface.
@@ -755,7 +808,7 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
   * @brief    PCCARD Controller functions 
   *
   @verbatim 
-  ==============================================================================  
+  ==============================================================================
                     ##### How to use PCCARD device driver #####
   ==============================================================================
   [..]
@@ -960,7 +1013,7 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 /**
   * @}
   */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h
index e2871f1fb0..b885ae5eb4 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_fsmc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of FSMC HAL module.
   ******************************************************************************
   * @attention
@@ -54,7 +54,7 @@
   * @{
   */
 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
 /* Private types -------------------------------------------------------------*/
 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
   * @{
@@ -114,9 +114,20 @@ typedef struct
   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
                                               This parameter can be a value of @ref FSMC_Write_Burst                      */
 
-  uint32_t PageSize;                     /*!< Specifies the memory page size.
-                                              This parameter can be a value of @ref FMC_Page_Size                         */
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care 
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock    
+                                              This mode is available only for the STM32F412Vx/Zx/Rx devices                 */
 
+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care 
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Write_FIFO
+                                              This mode is available only for the STM32F412Vx/Vx devices                    */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FMC_Page_Size                   */
 }FSMC_NORSRAM_InitTypeDef;
 
 /** 
@@ -192,7 +203,7 @@ typedef struct
                                         delay between ALE low and RE low.
                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 
-}FSMC_NAND_InitTypeDef;  
+}FSMC_NAND_InitTypeDef;
 
 /** 
   * @brief FSMC NAND/PCCARD Timing parameters structure definition
@@ -390,6 +401,16 @@ typedef struct
   * @}
   */
 
+/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
+  * @note  These values are available only for the STM32F412Vx/Zx/Rx devices.
+  * @{
+  */
+#define FSMC_WRITE_FIFO_DISABLE           ((uint32_t)FSMC_BCR1_WFDIS)
+#define FSMC_WRITE_FIFO_ENABLE            ((uint32_t)0x00000000U)
+/**
+  * @}
+  */
+
 /** @defgroup FSMC_Write_Burst FSMC Write Burst
   * @{
   */
@@ -398,6 +419,16 @@ typedef struct
 /**
   * @}
   */
+  
+/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
+  * @note  These values are available only for the STM32F412Vx/Zx/Rx devices.
+  * @{
+  */
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000U)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000U)
+/**
+  * @}
+  */
 
 /** @defgroup FSMC_Access_Mode FSMC Access Mode
   * @{
@@ -518,6 +549,10 @@ typedef struct
 #define FSMC_PCCARD_DEVICE                    FSMC_Bank4
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
 
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8           FSMC_NORSRAM_MEM_BUS_WIDTH_8
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16          FSMC_NORSRAM_MEM_BUS_WIDTH_16
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32          FSMC_NORSRAM_MEM_BUS_WIDTH_32
+
 #define FMC_NORSRAM_TypeDef                   FSMC_NORSRAM_TypeDef
 #define FMC_NORSRAM_EXTENDED_TypeDef          FSMC_NORSRAM_EXTENDED_TypeDef
 #define FMC_NORSRAM_InitTypeDef               FSMC_NORSRAM_InitTypeDef
@@ -995,7 +1030,7 @@ HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
 /**
   * @}
   */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
 
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c
index 09c6ccb615..06cd7eb7ca 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_sdmmc.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   SDMMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -181,7 +181,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -496,7 +497,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
 /**
   * @}
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h
index 273fde597f..c0acd1da9e 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
 
@@ -797,7 +798,8 @@ typedef struct
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
 /**
   * @brief  Enable the command completion signal.
   * @retval None
@@ -834,7 +836,8 @@ typedef struct
   */  
 #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
-          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+          STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
+          STM32F412Cx */
 /**
   * @}
   */
@@ -905,7 +908,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c
index 56e110954f..cf898e956f 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_usb.c
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   USB Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -66,7 +66,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -134,7 +135,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
  
   if(cfg.dma_enable == ENABLE)
   {
-    USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
     USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
   }  
 
@@ -206,7 +206,8 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   uint32_t i = 0U;
 
   /*Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
   USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
   
   if (cfg.vbus_sensing_enable == 0U)
@@ -225,7 +226,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   {
     USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
   }
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
   /* Restart the Phy Clock */
   USBx_PCGCCTL = 0U;
@@ -1137,13 +1138,14 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
   USBx_PCGCCTL = 0U;
   
   /* Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
   USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
 #else
   USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
   USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
   USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
 
   /* Disable the FS/LS support mode only */
   if((cfg.speed == USB_OTG_SPEED_FULL)&&
@@ -1411,7 +1413,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
   USBx_HC(ch_num)->HCCHAR = (((dev_address << 22U) & USB_OTG_HCCHAR_DAD)  |\
                              (((epnum & 0x7FU)<< 11U) & USB_OTG_HCCHAR_EPNUM)|\
                              ((((epnum & 0x80U) == 0x80U)<< 15U) & USB_OTG_HCCHAR_EPDIR)|\
-                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
+                             (((speed == USB_OTG_SPEED_LOW)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
                              ((ep_type << 18U) & USB_OTG_HCCHAR_EPTYP)|\
                              (mps & USB_OTG_HCCHAR_MPSIZ));
     
@@ -1566,15 +1568,15 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
   uint32_t count = 0U;
   
   /* Check for space in the request queue to issue the halt. */
-  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18U)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18U)))
+  if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || (((((USBx_HC(hc_num)->HCCHAR) & 
+  USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
   {
     USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
     
-    if ((USBx->HNPTXSTS & 0xFFFFU) == 0U)
+    if ((USBx->HNPTXSTS & 0xFF0000U) == 0U)
     {
       USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
       do 
       {
         if (++count > 1000U) 
@@ -1597,7 +1599,6 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
     {
       USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
       do 
       {
         if (++count > 1000U) 
@@ -1698,7 +1699,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
 
 /**
diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h
index b6657ca038..a4cf3606ef 100644
--- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h
+++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_usb.h
   * @author  MCD Application Team
-  * @version V1.4.4
-  * @date    22-January-2016
+  * @version V1.5.0
+  * @date    06-May-2016
   * @brief   Header file of USB Core HAL module.
   ******************************************************************************
   * @attention
@@ -45,7 +45,8 @@
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal_def.h"
 
@@ -464,7 +465,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
   * @}
   */
 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
+          STM32F412Vx || STM32F412Cx */
 #ifdef __cplusplus
 }
 #endif